a6897ecbb5
fix off by 1 (insn) error in eh.sjlj.setjmp thumb code sequence.
...
llvm-svn: 104661
2010-05-26 01:22:21 +00:00
4f48499d2c
Allow t2MOVsrl_flag and t2MOVsra_flag instructions to be predicated.
...
I don't know of any particular reason why that would be important, but
neither can I see any reason to disallow it.
llvm-svn: 104583
2010-05-25 04:51:47 +00:00
debbbe3fd9
Fix up instruction classes for Thumb2 RSB instructions to be consistent with
...
Thumb2 ADD and SUB instructions: allow RSB instructions be changed to set the
condition codes, and allow RSBS instructions to be predicated.
llvm-svn: 104582
2010-05-25 04:43:08 +00:00
91b2b8540c
Allow Thumb2 MVN instructions to set condition codes. The immediate operand
...
version of t2MVN already allowed that, but not the register versions.
llvm-svn: 104570
2010-05-24 22:41:19 +00:00
3eb7691858
Thumb2 RSBS instructions were being printed without the 'S' suffix.
...
Fix it by changing the T2I_rbin_s_is multiclass to handle the CPSR
output and 'S' suffix in the same way as T2I_bin_s_irs.
llvm-svn: 104531
2010-05-24 18:44:06 +00:00
daeca2d156
t2LEApcrel and tLEApcrel are re-materializable. This makes it possible to hoist more loads during machine LICM.
...
llvm-svn: 104115
2010-05-19 07:28:01 +00:00
dd7f566597
Mark pattern-less mayLoad / mayStore instructions neverHasSideEffects. These do not have other un-modeled side effects.
...
llvm-svn: 104111
2010-05-19 06:07:03 +00:00
2c452fcd14
Mark a few more pattern-less instructions with neverHasSideEffects. This is especially important on instructions like t2LEApcreal which are prime candidate for machine LICM.
...
llvm-svn: 104102
2010-05-19 01:52:25 +00:00
497d831966
Chris said that the comment char should be escaped. Fix all the occurences of "@" in *.td
...
llvm-svn: 103903
2010-05-16 09:15:36 +00:00
151cd8f159
Cleanup of ARMv7M support. Move hardware divide and Thumb2 extract/pack
...
instructions to subtarget features and update tests to reflect.
PR5717.
llvm-svn: 103136
2010-05-05 23:44:43 +00:00
92d999001c
Add initial support for ARMv7M subtarget and cortex-m3 cpu. Patch by
...
Jordy <snhjordy@gmail.com>.
Followup patches will add some tests and adjust to use Subtarget features
for the instructions.
llvm-svn: 103119
2010-05-05 20:44:35 +00:00
0106063556
Provide versions of the ARM eh_sjlj_setjmp instructions for non-VFP subtargets
...
such that the non-VFP versions have no implicit defs of VFP registers.
If any callee-saved VFP registers are marked as having been defined, the
prologue/epilogue code will try to save and restore them.
Radar 7770432.
llvm-svn: 100892
2010-04-09 20:41:18 +00:00
d6243b49d4
Remove the writeback flag from ARM's address mode 4. Now that we have separate
...
instructions for ld/st with writeback, the flag is completely redundant.
llvm-svn: 98643
2010-03-16 17:46:45 +00:00
947f04bad0
Change ARM ld/st multiple instructions to have variant instructions for
...
writebacks to the address register. This gets rid of the hack that the
first register on the list was the magic writeback register operand. There
was an implicit constraint that if that operand was not reg0 it had to match
the base register operand. The post-RA scheduler's antidependency breaker
did not understand that constraint and sometimes changed one without the
other. This also fixes Radar 7495976 and should help the verifier work
better for ARM code.
There are now new ld/st instructions explicit writeback operands and explicit
constraints that tie those registers together.
llvm-svn: 98409
2010-03-13 01:08:20 +00:00
c1d1229d78
Set the (Format)F filed of t2Int_MemBarrierV7 & t2Int_SyncBarrierV7 to ThumbFrm,
...
instead of Pseudo, which helps Thumb decoder to recognize them as Thumb instr.
llvm-svn: 98285
2010-03-11 21:02:50 +00:00
f5e81aeba5
Added Thumb2 LDRD/STRD pre/post variants for disassembly only.
...
Plus fixed the encoding of t2LDRDpci such that P = 1 and W = 0 (offset mode).
llvm-svn: 98217
2010-03-11 01:13:36 +00:00
9a3e2398ae
Factored out the disassembly printing of CPS option, MSR mask, and Negative Zero
...
operands into their own PrintMethod, in order not to pollute the printOperand()
impl with disassembly only Imm modifiers.
llvm-svn: 98172
2010-03-10 18:59:38 +00:00
15804db55c
MSR (Move to Special Register from ARM core register) requires a mask to specify
...
what fields of the CPSR or SPSR are affected.
llvm-svn: 98085
2010-03-09 21:39:34 +00:00
0bfbd9b68c
Fix a crash compiling 254.gap for Thumb2. The Thumb2 add/sub with 12-bit
...
immediate instructions cannot set the condition codes, so they do not have
the extra cc_out operand. We hit an assertion during tail duplication
because the instruction being duplicated had more operands that expected.
llvm-svn: 98001
2010-03-08 22:56:15 +00:00
70e01cd001
Trivial comment change.
...
llvm-svn: 97776
2010-03-05 01:45:46 +00:00
ece1797542
Drop the ".w" qualifier for t2UXTB16* instructions as there is no 16-bit version
...
of either sxtb16 or uxtb16, and the unified syntax does not specify ".w".
llvm-svn: 97760
2010-03-04 22:24:41 +00:00
334db0ce7f
Added 32-bit Thumb instructions for Preload Data (PLD, PLDW) and Preload
...
Instruction (PLI) for disassembly only.
According to A8.6.120 PLI (immediate, literal), for example, different
instructions are generated for "pli [pc, #0 ]" and "pli [pc, #-0"]. The
disassembler solves it by mapping -0 (negative zero) to -1, -1 to -2, ..., etc.
llvm-svn: 97731
2010-03-04 17:40:44 +00:00
f1e25c7163
Added 32-bit Thumb instructions LDRT, LDRBT, LDRHT,,LDRSBT, LDRSHT, STRT, STRBT,
...
and STRHT for disassembly only.
llvm-svn: 97655
2010-03-03 18:45:36 +00:00
f1ea86b567
Added 32-bit Thumb instructions t2NOP, t2YIELD, t2WFE, t2WFI, t2SEV, and t2DBG
...
for disassembly only.
llvm-svn: 97632
2010-03-03 02:09:43 +00:00
d8c50c67dc
Eliminate unused instruction classes.
...
llvm-svn: 97617
2010-03-03 00:43:15 +00:00
334af68052
Added 32-bit Thumb instructions t2DMB variants, t2DSB variants, and t2ISBsy for
...
disassembly only.
llvm-svn: 97614
2010-03-03 00:16:28 +00:00
7041f2cef6
Added 32-bit Thumb instruction CLREX (Clear-Exclusive) for disassembly only.
...
llvm-svn: 97595
2010-03-02 22:11:06 +00:00
9dc2105478
Removed the extra S from the multiclass def T2I_adde_sube_s_irs as well as from
...
the opc string passed in, since it's a given from the class inheritance of T2sI.
The fixed the extra 's' in adcss & sbcss when disassembly printing.
llvm-svn: 97582
2010-03-02 19:38:59 +00:00
44908a5e17
Added 32-bit Thumb instructions: CPS, SDIV, UDIV, SXTB16, SXTAB16, UXTAB16, SEL,
...
SMMULR, SMMLAR, SMMLSR, TBB, TBH, and 16-bit Thumb instruction CPS for
disassembly only.
llvm-svn: 97573
2010-03-02 18:14:57 +00:00
0dae1cbf1c
AL is an optional mnemonic extension for always, except in IT instructions.
...
Add printMandatoryPredicateOperand() PrintMethod for IT predicate printing.
Ref: A8.3 Conditional execution
llvm-svn: 97571
2010-03-02 17:57:15 +00:00
8c5d683aa9
The mayHaveSideEffects flag is no longer used.
...
llvm-svn: 97348
2010-02-27 23:47:46 +00:00
38e7bb6f34
Added the follwoing 32-bit Thumb instructions for disassembly only:
...
o Parallel addition and subtraction, signed/unsigned
o Miscellaneous operations: QADD, QDADD, QSUB, QDSUB
o Unsigned sum of absolute differences [and accumulate]: USAD8, USADA8
o Signed/Unsigned saturate: SSAT, SSAT16, USAT, USAT16
o Signed multiply accumulate long (halfwords): SMLAL<x><y>
o Signed multiply accumulate/subtract [long] (dual): SMLAD[x], SMLALD[X], SMLSD[X], SMLSLD[X]
o Signed dual multiply add/subtract [long]: SMUAD[X], SMUSD[X]
llvm-svn: 97276
2010-02-26 22:04:29 +00:00
3adff378cc
Added the following 32-bit Thumb instructions for disassembly only: SMC, RFE,
...
and SRS.
llvm-svn: 97164
2010-02-25 20:25:24 +00:00
871e5b0926
Added the 32-bit Thumb instructions (BXJ) for disassembly only.
...
llvm-svn: 97163
2010-02-25 19:05:29 +00:00
e285f70a42
Added the 32-bit Thumb instructions (MRS and MSR) for disassembly only.
...
llvm-svn: 97159
2010-02-25 18:46:43 +00:00
3e2cad3b1a
80 column cleanup
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llvm-svn: 96393
2010-02-16 21:23:02 +00:00
fba7fce5be
Remove trailing whitespace
...
llvm-svn: 96388
2010-02-16 21:07:46 +00:00
2284ddab56
Update Thumb2 to not use CarryDefIsUnused or CarryDefIsUsed predicates, but
...
to have the predicate on the pattern itself instead. Support for the new
ISel. Remove definitions of CarryDefIsUnused and CarryDefIsUsed since they are
no longer used anywhere.
llvm-svn: 96384
2010-02-16 20:42:29 +00:00
a570d05228
tighten up eh.setjmp sequence a bit.
...
llvm-svn: 95603
2010-02-08 23:22:00 +00:00
8487d65ea2
Added t2BFI (Bitfield Insert) entry for disassembler, with blank pattern field.
...
llvm-svn: 95112
2010-02-02 19:31:58 +00:00
267430f74d
Fix PR5694. The CMN instructions set the flags differently from CMP, so they
...
cannot be directly interchanged for comparisons against negated values.
Disable the CMN instructions for the time being.
llvm-svn: 94119
2010-01-22 00:08:13 +00:00
6c0fb92c03
Fix r93758. Use isel patterns instead of c++ selection code to select rbit and make sure we pick different instructions for ARM vs. Thumb2.
...
llvm-svn: 93829
2010-01-19 00:44:15 +00:00
8546ec9c14
Patch by David Conrad:
...
"On ARMv6T2 this turns cttz into rbit, clz instead of the 4 instruction
sequence it is now."
llvm-svn: 93758
2010-01-18 19:58:49 +00:00
ab6e6819b2
Minor change, change the order of two "let Inst{...}" stmts within multiclass
...
T2I_bin_ii12rs definition.
llvm-svn: 93006
2010-01-08 17:41:33 +00:00
567945636f
Undo r92785, it caused test failure.
...
llvm-svn: 92796
2010-01-05 22:37:28 +00:00
a9f39bdbb6
Add Rt2 to the asm format string for 32-bit Thumb load/store register dual
...
instructions. Thumb does not have the restriction that t2 = t+1.
llvm-svn: 92785
2010-01-05 21:51:46 +00:00
69461f50c1
Mark STREX* as earlyclobber for the success result register.
...
llvm-svn: 91555
2009-12-16 19:44:06 +00:00
466231ab92
Add encoding bits for some Thumb instructions. Plus explicitly set the top two
...
bytes of Inst to 0x0000 for the benefit of the Thumb decoder.
llvm-svn: 91496
2009-12-16 02:32:54 +00:00
c28e629c2d
Added encoding bits for the Thumb ISA. Initial checkin.
...
llvm-svn: 91434
2009-12-15 17:24:14 +00:00
3c4f04112a
Add ARMv6 memory and sync barrier instructions
...
llvm-svn: 91329
2009-12-14 21:24:16 +00:00
fed3d088ce
correct selection requirements for thumb2 vs. arm versions of the barrier intrinsics
...
llvm-svn: 91313
2009-12-14 19:24:11 +00:00
20ac87de13
add Thumb2 atomic and memory barrier instruction definitions
...
llvm-svn: 91310
2009-12-14 18:56:47 +00:00
2522908653
Materialize global addresses via movt/movw pair, this is always better
...
than doing the same via constpool:
1. Load from constpool costs 3 cycles on A9, movt/movw pair - just 2.
2. Load from constpool might stall up to 300 cycles due to cache miss.
3. Movt/movw does not use load/store unit.
4. Less constpool entries => better compiler performance.
This is only enabled on ELF systems, since darwin does not have needed
relocations (yet).
llvm-svn: 89720
2009-11-24 00:44:37 +00:00
f890f51666
80 column violations
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llvm-svn: 89718
2009-11-24 00:20:27 +00:00
04c0e76772
fold immediate of a + Const into the user as a subtract if it can fit as a negated two-part immediate.
...
llvm-svn: 89694
2009-11-23 20:35:53 +00:00
bdb43a9d99
Remat VLDRD from constpool. Clean up some instruction property specifications.
...
llvm-svn: 89478
2009-11-20 19:57:15 +00:00
207b246650
- Add pseudo instructions tLDRpci_pic and t2LDRpci_pic which does a pc-relative
...
load of a GV from constantpool and then add pc. It allows the code sequence to
be rematerializable so it would be hoisted by machine licm.
- Add a late pass to break these pseudo instructions into a number of real
instructions. Also move the code in Thumb2 IT pass that breaks up t2MOVi32imm
to this pass. This is done before post regalloc scheduling to allow the
scheduler to proper schedule these instructions. It also allow them to be
if-converted and shrunk by later passes.
llvm-svn: 86304
2009-11-06 23:52:48 +00:00
b376ce0169
Fix t2Int_eh_sjlj_setjmp. Immediate form of orr is a 32-bit instruction. So it should be 22 bytes instead of 20 bytes long.
...
llvm-svn: 85965
2009-11-03 23:13:34 +00:00
1c66e8a6b7
Put BlockAddresses into ARM constant pools.
...
llvm-svn: 85824
2009-11-02 20:59:23 +00:00
5ac6f244fd
Fix schedule model for BFC.
...
llvm-svn: 85809
2009-11-02 17:28:36 +00:00
cdbb70c065
It's safe to remat t2LDRpci; Add PseudoSourceValue to load / store's to enable more machine licm. More changes coming.
...
llvm-svn: 85643
2009-10-31 03:39:36 +00:00
1cf0b03064
Add ARM codegen for indirect branches.
...
clang/test/CodeGen/indirect-goto.c runs! (unoptimized)
llvm-svn: 85577
2009-10-30 05:45:42 +00:00
453d64c9f5
Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a
...
bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.
llvm-svn: 85517
2009-10-29 18:10:34 +00:00
b02bdb4552
Change Thumb1 and Thumb2 instructions to separate opcode from operands with a tab instead of a space.
...
llvm-svn: 85184
2009-10-27 00:08:59 +00:00
a93ca3c637
Improve handling of immediates by splitting 32-bit immediates into two 16-bit
...
immediate operands when they will fit into the using instruction.
llvm-svn: 84778
2009-10-21 20:44:34 +00:00
786b15fe12
Match more patterns to movt.
...
llvm-svn: 84751
2009-10-21 08:15:52 +00:00
423e42b371
Add ARMv6T2 SBFX/UBFX instructions. Approved by Anton Korobeynikov.
...
llvm-svn: 84009
2009-10-13 18:59:48 +00:00
1b2b64f618
Add hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq flags to ld / st multiple,
...
ld / st pairs, etc.
llvm-svn: 83197
2009-10-01 08:22:27 +00:00
3bbc6c3ae6
Change ld/st multiples to explicitly model the writeback to base register. This fixes most of the -ldstopti-before-sched2 regressions.
...
llvm-svn: 83191
2009-10-01 01:33:39 +00:00
bcad0c8421
Add "isBarrier = 1" to return instructions.
...
Patch by Sylvere Teissier.
llvm-svn: 83135
2009-09-30 01:35:11 +00:00
83e0d481ae
Make ARM and Thumb2 32-bit immediate materialization into a single 32-bit pseudo
...
instruction. This makes it re-materializable.
Thumb2 will split it back out into two instructions so IT pass will generate the
right mask. Also, this expose opportunies to optimize the movw to a 16-bit move.
llvm-svn: 82982
2009-09-28 09:14:39 +00:00
7c2b1e71c1
Use movt/movw pair to materialize 32 bit constants on ARMv6T2+.
...
This should be better than single load from constpool.
llvm-svn: 82948
2009-09-27 23:52:58 +00:00
a6b9cab822
Enable pre-regalloc load / store multiple pass for Thumb2.
...
llvm-svn: 82893
2009-09-27 09:46:04 +00:00
5f582b7290
RRX reads CPSR.
...
llvm-svn: 80699
2009-09-01 18:32:09 +00:00
4047b53a40
Print a nl before pic labels so they start at a new line. This makes assembly more readable.
...
llvm-svn: 80350
2009-08-28 06:59:37 +00:00
ceffeb6abd
Rename ARM "lane_cst" operands to "nohash_imm" since they are used for
...
several things other than Neon vector lane numbers. For inline assembly
operands with a "c" print code, check that they really are immediates.
llvm-svn: 79676
2009-08-21 21:58:55 +00:00
a7c2dfbca1
Update Cortex-A8 instruction itineraries for integer instructions.
...
llvm-svn: 79436
2009-08-19 18:00:44 +00:00
dd406177de
Fix revsh pattern.
...
llvm-svn: 79318
2009-08-18 05:43:23 +00:00
db73d68cbe
Shrink ADR and LDR from constantpool late during constantpool island pass.
...
llvm-svn: 78970
2009-08-14 00:32:16 +00:00
eba70d85cf
Add missing defs of R2 and D1.
...
llvm-svn: 78918
2009-08-13 16:59:44 +00:00
a9c2aad939
Finalize itineraries for cortex-a8 integer multiply
...
llvm-svn: 78908
2009-08-13 15:51:13 +00:00
695e1c6087
Remove unnecessary newline
...
llvm-svn: 78905
2009-08-13 15:12:16 +00:00
c96e88f8a5
Correct comment wording
...
llvm-svn: 78904
2009-08-13 15:11:43 +00:00
b369ee4c48
Enhance the InstrStage object to enable the specification of an Itinerary with overlapping stages. The default is to maintain the current behavior that the "next" stage immediately follows the previous one.
...
llvm-svn: 78827
2009-08-12 18:31:53 +00:00
a5fdfac6ca
register naming cleanup (s/ip/r12/)
...
llvm-svn: 78806
2009-08-12 15:21:13 +00:00
608d92c943
Remove an Darwin assembler workaround.
...
llvm-svn: 78777
2009-08-12 01:56:42 +00:00
cc9ca3500d
Shrinkify Thumb2 load / store multiple instructions.
...
llvm-svn: 78717
2009-08-11 21:11:32 +00:00
9f94459d24
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while
...
the latter is capable of representing either a primitive or an extended type.
llvm-svn: 78713
2009-08-11 20:47:22 +00:00
841850ed26
Add Thumb2 eh_sjlj_setjmp implementation
...
llvm-svn: 78701
2009-08-11 19:42:21 +00:00
d4d352c663
80 column violation.
...
llvm-svn: 78657
2009-08-11 08:47:46 +00:00
53aa7a960c
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type.
...
llvm-svn: 78610
2009-08-10 22:56:29 +00:00
51cbd2d6c4
Add support to reduce most of 32-bit Thumb2 arithmetic instructions.
...
llvm-svn: 78550
2009-08-10 02:37:24 +00:00
cfed3005e5
Use subclassing to print lane-like immediates (w/o hash) eliminating
...
'no_hash' modifier. Hopefully this will make Daniel happy :)
llvm-svn: 78514
2009-08-08 23:10:41 +00:00
6e130db3b7
Thumb2 32-bit ldm / stm needs .w suffix if submode is ia.
...
llvm-svn: 78410
2009-08-07 21:19:10 +00:00
b972e5633f
It turns out most of the thumb2 instructions are not allowed to touch SP. The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing.
...
This patch takes pain to ensure all the PEI lowering code does the right thing when lowering frame indices, insert code to manipulate stack pointers, etc. It's also custom lowering dynamic stack alloc into pseudo instructions so we can insert the right instructions at scheduling time.
This fixes PR4659 and PR4682.
llvm-svn: 78361
2009-08-07 00:34:42 +00:00
b062c236c5
Add parameter to pattern classes to enable an itinerary to be specified for instructions. For now just use the existing itineraries or NoItinerary.
...
llvm-svn: 78321
2009-08-06 16:52:47 +00:00
7cc6aca1e6
Fix part 1 of pr4682. PICADD is a 16-bit instruction even in thumb2 mode.
...
llvm-svn: 78126
2009-08-04 23:47:55 +00:00
03eb0e3c33
Emit sub r, #c instead of transforming it to add r, #-c if c fits in 8-bit. This is a bit of pre-mature optimization. 8-bit variant makes it likely it will be narrowed to a 16-bit instruction.
...
llvm-svn: 78030
2009-08-04 01:41:15 +00:00
e64f48ba8b
Workaround a couple of Darwin assembler bugs.
...
llvm-svn: 77781
2009-08-01 06:13:52 +00:00
e6e8289d72
Split t2MOVCCs since some assemblers do not recognize mov shifted register alias with predicate.
...
llvm-svn: 77764
2009-08-01 01:43:45 +00:00
Jim Grosbach