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3144 Commits

Author SHA1 Message Date
Evan Cheng e37da03e60 More pseudo instruction scheduling itinerary fixes. 
llvm-svn: 114768
 2010-09-24 22:41:41 +00:00
Evan Cheng 1d35ad62cc Fix scheduling itinerary for pseudo mov immediate instructions which expand into two real instructions. 
llvm-svn: 114766
 2010-09-24 22:03:46 +00:00
Jim Grosbach 4a6ab13fb9 Add ARM explicit MCInst lowering for the Thumb eh.sjlj.setjmp sequence. 
llvm-svn: 114758
 2010-09-24 20:47:58 +00:00
Evan Cheng dbcc4b4d4d Enable code placement optimization pass for ARM. 
llvm-svn: 114746
 2010-09-24 19:07:23 +00:00
Evan Cheng 40a4222996 Fix a potential null dereference bug. 
llvm-svn: 114723
 2010-09-24 05:18:35 +00:00
Owen Anderson 2c5df619c4 Revert r114703 and r114702, removing the isConditionalMove flag from instructions. After further 
reflection, this isn't going to achieve the purpose I intended it for.  Back to the drawing board!

llvm-svn: 114710
 2010-09-23 23:45:25 +00:00
Bob Wilson 7fbbe9a43a Set alignment operand for NEON VST instructions. 
llvm-svn: 114709
 2010-09-23 23:42:37 +00:00
Jim Grosbach c0aed7179a ARM-mode eh.sjlj.setjmp pseudo MC-inst lowering expansion 
llvm-svn: 114707
 2010-09-23 23:33:56 +00:00
Jim Grosbach 2f3728f576 #+4 --> #4 for consistency with other asm output 
llvm-svn: 114706
 2010-09-23 23:32:38 +00:00
Jim Grosbach 07f07290d8 Fix formatting of output .s code 
llvm-svn: 114705
 2010-09-23 23:03:26 +00:00
Owen Anderson bd57e0ce3d Add isConditionalMove bits to X86 and ARM instructions. 
llvm-svn: 114703
 2010-09-23 22:57:01 +00:00
Bob Wilson 9eeb890172 Set alignment operand for NEON VLD instructions. 
llvm-svn: 114696
 2010-09-23 21:43:54 +00:00
Jim Grosbach 7d34837676 never mind. I can't read, apparently 
llvm-svn: 114689
 2010-09-23 19:42:17 +00:00
Evan Cheng 1596f7f6f3 Fix r114632. Return if the only terminator is an unconditional branch after the redundant ones are deleted. 
llvm-svn: 114688
 2010-09-23 19:42:03 +00:00
Jim Grosbach 836341a17a Fix opcode value for the 'trap' instruction, keeping the type suffix on the 
constant. Hopefully the non-Darwin bots will like it...

llvm-svn: 114687
 2010-09-23 19:32:40 +00:00
Jim Grosbach 3d50a3e237 explicit 'unsigned long' on constant value. Hopefully make bots happier. 
llvm-svn: 114686
 2010-09-23 19:08:04 +00:00
Benjamin Kramer e38495dbc0 Unbreak build. Jim, please review. 
llvm-svn: 114684
 2010-09-23 18:57:26 +00:00
Jim Grosbach 8503054410 Clean up the 'trap' instruction printing a bit. Non-Darwin assemblers don't 
(yet) recognize the 'trap' mnemonic, so we use .short/.long to emit the
opcode directly. On Darwin, however, we do want the mnemonic for more
readable assembly code and better disassembly.

Adjust the .td file to use the 'trap' mnemonic and handle using the binutils
workaround in the assembly printer. Also tweak the formatting of the opcode
values to make them consistent between the MC printer and the old printer.

llvm-svn: 114679
 2010-09-23 18:05:37 +00:00
Jim Grosbach ea20e257b2 nuke unused var 
llvm-svn: 114676
 2010-09-23 17:58:00 +00:00
Evan Cheng 66c8cd2b32 If there are multiple unconditional branches terminating a block, eliminate all 
but the first one. Those will never be executed. There was logic to do this
but it was faulty.

llvm-svn: 114632
 2010-09-23 06:54:40 +00:00
Jim Grosbach 85dcd3d0f4 Add support for ELF PLT references for ARM MC asm printing. Adding a 
new VariantKind to the MCSymbolExpr seems like overkill, but I'm not sure
there's a more straightforward way to get the printing difference captured.
(i.e., x86 uses @PLT, ARM uses (PLT)).

llvm-svn: 114613
 2010-09-22 23:27:36 +00:00
Jim Grosbach a9424d4f2f Enable a few additional asserts in MC instruction lowering. 
llvm-svn: 114601
 2010-09-22 23:01:28 +00:00
Bob Wilson 463a05342a Change VDUPLANE DAG combiner to just return the result instead of calling 
CombineTo to avoid putting the result on the worklist.  I don't think it makes
much difference for now, but it might help someday as we add more DAG
combine optimizations.

llvm-svn: 114595
 2010-09-22 22:27:30 +00:00
Bob Wilson 2280674fa9 Combine both VMOVDRR(VMOVRRD) and VMOVRRD(VMOVDRR), instead of just doing one 
of those.  Refactor to share code for handling BUILD_VECTOR(VMOVRRD).
I don't have a testcase that exercises this, but it seems like an obvious
good thing to do.

llvm-svn: 114589
 2010-09-22 22:09:21 +00:00
Jim Grosbach 1f57cc4a59 add FIXME 
llvm-svn: 114578
 2010-09-22 20:55:15 +00:00
Jim Grosbach 003fd5b65e Remove a few commented out bits 
llvm-svn: 114576
 2010-09-22 20:32:34 +00:00
Jim Grosbach e12c8ba05b Add PrintSpecial() handling for in ARM MC instruction printer. 
llvm-svn: 114563
 2010-09-22 18:37:14 +00:00
Jim Grosbach 284eebc1ae Add MC instruction printer support for ARM and Thumb1 jump tables. 
llvm-svn: 114555
 2010-09-22 17:39:48 +00:00
Jim Grosbach 1573b29ea7 Add MC instruction printer support for TB[BH] style thumb2 jump tables. 
llvm-svn: 114553
 2010-09-22 17:15:35 +00:00
Jim Grosbach 754e1efffc Clean up comment. 
llvm-svn: 114550
 2010-09-22 16:45:13 +00:00
Evan Cheng d757c88bba OptimizeCompareInstr should avoid iterating pass the beginning of the MBB when the 'and' instruction is after the comparison. 
llvm-svn: 114506
 2010-09-21 23:49:07 +00:00
Jim Grosbach d64f9b8381 Add start of support for MC instruction printer of ARM jump tables. Filling in 
the rest of it is next up.

llvm-svn: 114500
 2010-09-21 23:28:16 +00:00
Owen Anderson 61158f98ab Enable target-specific mul-lowering on ARM, even at -Os. Remove a test that this makes 
irrelevant, but add a new test for the new, improved functionality.

llvm-svn: 114494
 2010-09-21 22:51:46 +00:00
Chris Lattner 0e023ea02a fix a long standing wart: all the ComplexPattern's were being 
passed the root of the match, even though only a few patterns
actually needed this (one in X86, several in ARM [which should
be refactored anyway], and some in CellSPU that I don't feel 
like detangling).   Instead of requiring all ComplexPatterns to
take the dead root, have targets opt into getting the root by
putting SDNPWantRoot on the ComplexPattern.

llvm-svn: 114471
 2010-09-21 20:31:19 +00:00
Chris Lattner 886250c8f0 convert a couple more places to use the new getStore() 
llvm-svn: 114463
 2010-09-21 18:51:21 +00:00
Bob Wilson 5549d496dd Define the TargetLowering::getTgtMemIntrinsic hook for ARM so that NEON load 
and store intrinsics are represented with MemIntrinsicSDNodes.

llvm-svn: 114454
 2010-09-21 17:56:22 +00:00
Jim Grosbach cbac342e1a Fix errant printing of [v]ldm instructions that aren't a pop 
llvm-svn: 114445
 2010-09-21 16:45:31 +00:00
Gabor Greif 1a25ae88ff Fix buglet when the TST instruction directly uses the AND result. 
I am unable to write a test for this case, help is solicited, though...
What I did is to tickle the code in the debugger and verify that we do the right thing.

llvm-svn: 114430
 2010-09-21 13:30:57 +00:00
Gabor Greif adbbb93d3d Move the search for the appropriate AND instruction 
into OptimizeCompareInstr.
This necessitates the passing of CmpValue around,
so widen the virtual functions to accomodate.

No functionality changes.

llvm-svn: 114428
 2010-09-21 12:01:15 +00:00
Chris Lattner 7727d05dbb convert the targets off the non-MachinePointerInfo of getLoad. 
llvm-svn: 114410
 2010-09-21 06:44:06 +00:00
Chris Lattner 2510de2bea reimplement memcpy/memmove/memset lowering to use MachinePointerInfo 
instead of srcvalue/offset pairs.  This corrects SV info for mem 
operations whose size is > 32-bits.

llvm-svn: 114401
 2010-09-21 05:40:29 +00:00
Chris Lattner e3d864b857 convert targets to the new MF.getMachineMemOperand interface. 
llvm-svn: 114391
 2010-09-21 04:39:43 +00:00
Jim Grosbach 94dfd6fc4f Simplify ARM callee-saved register handling by removing the distinction 
between the high and low registers for prologue/epilogue code. This was
a Darwin-only thing that wasn't providing a realistic benefit anymore.
Combining the save areas simplifies the compiler code and results in better
ARM/Thumb2 codegen.

For example, previously we would generate code like:
        push    {r4, r5, r6, r7, lr}
        add     r7, sp, #12
        stmdb   sp!, {r8, r10, r11}
With this change, we combine the register saves and generate:
        push    {r4, r5, r6, r7, r8, r10, r11, lr}
        add     r7, sp, #12

rdar://8445635

llvm-svn: 114340
 2010-09-20 19:32:20 +00:00
Michael J. Spencer abf60e3421 Fix build. 
llvm-svn: 114292
 2010-09-18 17:54:37 +00:00
Eric Christopher a6ba082cb6 Thumb opcodes for thumb calls. 
llvm-svn: 114263
 2010-09-18 02:32:38 +00:00
Eric Christopher aef6499bf1 Add addrmode5 fp load support. Swap float/thumb operand adding to handle 
thumb with floating point.

llvm-svn: 114256
 2010-09-18 01:59:37 +00:00
Eric Christopher 30f2300ed2 Floating point stores have a 3rd addressing mode type. 
llvm-svn: 114254
 2010-09-18 01:23:38 +00:00
Jim Grosbach af5d63583e factor out a simple helper function to create a label for PC-relative 
instructions (PICADD, PICLDR, et.al.)

llvm-svn: 114243
 2010-09-18 00:05:05 +00:00
Jim Grosbach 8a5a6a6c1e PC-relative pseudo instructions are lowered and printed directly. Any encounter 
with one in the generic printing code is an error.

llvm-svn: 114242
 2010-09-18 00:04:53 +00:00
Benjamin Kramer de636ca9a8 Fix vmov.f64 disassembly on targets where sizeof(long) != 8. 
llvm-svn: 114240
 2010-09-17 23:48:07 +00:00