Commit Graph

1203 Commits

Author SHA1 Message Date
Evandro Menezes 04abc14fb5 [AArch64] Change the preferred alignment for char and short to word alignment
Differential Revision: http://reviews.llvm.org/D21414

llvm-svn: 273280
2016-06-21 15:55:29 +00:00
Jan Vesely 9674bd4f97 NVPTX: Add supported CL features
Fixes libclc compilation broken by r269670

Reviewers: jholewinsky

Differential Revision: http://reviews.llvm.org/D20389

llvm-svn: 273031
2016-06-17 19:02:14 +00:00
Jan Vesely 211ba785d9 AMDGPU: Fix supported CL features
Reviewers: arsenm

Differential Revision: http://reviews.llvm.org/D20388

llvm-svn: 272986
2016-06-17 02:25:03 +00:00
Chris Dewhurst fe9e509b0c [Sparc] setjmp and longjmp intrinsic support update to add unit tests and remove accidentally checked-in code.
Related to revision r272782

llvm-svn: 272798
2016-06-15 16:08:13 +00:00
Chris Dewhurst 0381cd7dbf [Sparc] Change to let clang know that setjmp and longjmp intrinsics are implemented in the back-end.
Differential Revision: http://reviews.llvm.org/D19798

llvm-svn: 272782
2016-06-15 12:44:47 +00:00
Daniel Sanders 32b2d6b160 [mips] Defer validity check for CPU/ABI pairs and improve error message for invalid cases.
Summary:
The validity of ABI/CPU pairs is no longer checked on the fly but is
instead checked after initialization. As a result, invalid CPU/ABI pairs
can be reported as being known but invalid instead of being unknown. For
example, we now emit:
  error: ABI 'n32' is not supported on CPU 'mips32r2'
instead of:
  error: unknown target ABI 'n64'

Reviewers: atanasyan

Subscribers: sdardis, cfe-commits

Differential Revision: http://reviews.llvm.org/D21023

llvm-svn: 272645
2016-06-14 08:58:50 +00:00
Matt Arsenault 250024f905 AMDGPU: Verify subtarget specific builtins
Cleanup setup of subtarget features.

llvm-svn: 272091
2016-06-08 01:56:42 +00:00
Daniel Sanders 28d8637e25 [mips] The P5600 does not support N32/N64 since it's a 32-bit CPU.
Summary:

Reviewers: atanasyan

Subscribers: cfe-commits, sdardis

Differential Revision: http://reviews.llvm.org/D20963

llvm-svn: 271877
2016-06-06 09:47:32 +00:00
Daniel Sanders 26a56adaea [mips] Replace almost all Arch checks in MipsTargetInfo with ABI checks. NFC.
Summary:
setABI() is still tied to the Arch component of the Triple to preserve existing
behaviour.

Reviewers: atanasyan

Subscribers: cfe-commits

Differential Revision: http://reviews.llvm.org/D20961

llvm-svn: 271875
2016-06-06 09:07:08 +00:00
Daniel Sanders 55e4069702 [mips] Slightly simplify MipsTargetInfo::setDataLayout(). NFC.
Summary:

Reviewers: atanasyan

Subscribers: atanasyan, cfe-commits

Differential Revision: http://reviews.llvm.org/D20680

llvm-svn: 271647
2016-06-03 10:11:01 +00:00
Sjoerd Meijer 90df4a7c31 This adds target support and tests for Cortex-A73
Differential Revision: http://reviews.llvm.org/D20864

llvm-svn: 271507
2016-06-02 10:48:37 +00:00
Matt Arsenault 6dc455fb93 AMDGPU: Update datalayout string
llvm-svn: 271297
2016-05-31 16:58:18 +00:00
Daniel Sanders 07c8654284 [mips] Kill 'support' for untested EABI.
Summary:
There are no llvm backend tests* for EABI and no EABI buildbots. There were only
three clang tests, all of which checked that -mabi=eabi was passed to the
assembler.

*There is a single backend test that specifies EABI but it actually tests MIPS16.

Reviewers: atanasyan

Subscribers: emaste, sdardis, atanasyan, cfe-commits

Differential Revision: http://reviews.llvm.org/D20679

llvm-svn: 270998
2016-05-27 14:30:23 +00:00
Daniel Sanders 4672af6fec [mips] Fold MipsTargetInfoBase subclasses into MipsTargetInfoBase and rename to MipsTargetInfo. NFC
Summary:
This unifies mips/mipsel and mips64/mips64el into a single class so that we can
later support O32 on mips64/mips64el and N32/N64 on mips/mipsel (when an
appropriate CPU selected).

Reviewers: atanasyan

Subscribers: atanasyan, jfb, cfe-commits, dschuff

Differential Revision: http://reviews.llvm.org/D20678

llvm-svn: 270984
2016-05-27 11:51:02 +00:00
Renato Golin 3b8709c583 Revert "[AArch64] Using new TargetParser in Clang"
This reverts commit r270688 and r270689. The issue is not a random order, but a
different order for some targets and others (prob. Linux vs Darwin). Reverting until
we have a better fix.

llvm-svn: 270691
2016-05-25 12:36:31 +00:00
Renato Golin d4d4da74a6 [AArch64] Using new TargetParser in Clang
Using AArch64TargetParser in clang to avoid repetitive string parsing.

Use TargetParser to do ARCH/CPU/ArchExt parsing instead of local implementation.

Patch by Jojo Ma.

llvm-svn: 270688
2016-05-25 12:02:58 +00:00
Jacob Baungard Hansen 13a4937404 [Sparc] Add software float option -msoft-float
Summary:
Following patch D19265 which enable software floating point support in the Sparc backend, this patch enables the option to be enabled in the front-end using the -msoft-float option.

The user should ensure a library (such as the builtins from Compiler-RT) that includes the software floating point routines is provided.

Reviewers: jyknight, lero_chris

Subscribers: jyknight, cfe-commits

Differential Revision: http://reviews.llvm.org/D20419

llvm-svn: 270538
2016-05-24 08:30:08 +00:00
Dimitry Andric c6d924cd06 Make __FreeBSD_cc_version predefined macro configurable at build time
The `FreeBSDTargetInfo` class has always set the `__FreeBSD_cc_version`
predefined macro to a rather static value, calculated from the major OS
version.

In the FreeBSD base system, we will start incrementing the value of this
macro whenever we make any signifant change to clang, so we need a way
to configure the macro's value at build time.

Use `FREEBSD_CC_VERSION` for this, which we can define in the FreeBSD
build system using either the `-D` command line option, or an include
file.  Stock builds will keep the earlier value.

Differential Revision: http://reviews.llvm.org/D20037

llvm-svn: 270240
2016-05-20 17:27:22 +00:00
Benjamin Kramer f4c520d5d2 Add all the avx512 flavors to __builtin_cpu_supports's list.
This is matching what trunk gcc is accepting. Also adds a missing ssse3
case. PR27779. The amount of duplication here is annoying, maybe it
should be factored into a separate .def file?

llvm-svn: 270224
2016-05-20 15:21:08 +00:00
Krzysztof Parzyszek 89fb44147b [Hexagon] Recognize "s" constraint in inline-asm
llvm-svn: 270216
2016-05-20 13:50:32 +00:00
Artem Belevich ffa5fc51b8 [CUDA] Allow sm_50,52,53 GPUs
LLVM accepts them since r233575.

Differential Revision: http://reviews.llvm.org/D20405

llvm-svn: 270084
2016-05-19 17:47:47 +00:00
Krzysztof Parzyszek e0026e4e21 [Hexagon] Recognize "q" and "v" in inline-asm as register constraints
Clang follow-up to r269933.

llvm-svn: 269934
2016-05-18 14:56:14 +00:00
Ashutosh Nema 51c9dd0081 Add new intrinsic support for MONITORX and MWAITX instructions
Summary:
MONITORX/MWAITX instructions provide similar capability to the MONITOR/MWAIT
pair while adding a timer function, such that another termination of the MWAITX
instruction occurs when the timer expires. The presence of the MONITORX and 
MWAITX instructions is indicated by CPUID 8000_0001, ECX, bit 29.

The MONITORX and MWAITX instructions are intercepted by the same bits that
intercept MONITOR and MWAIT. MONITORX instruction establishes a range to be
monitored. MWAITX instruction causes the processor to stop instruction
execution and enter an implementation-dependent optimized state until
occurrence of a class of events.

Opcode of MONITORX instruction is "0F 01 FA". Opcode of MWAITX instruction is
"0F 01 FB". These opcode information is used in adding tests for the
disassembler.

These instructions are enabled for AMD's bdver4 architecture.

Patch by Ganesh Gopalasubramanian!

Reviewers: echristo, craig.topper

Subscribers: RKSimon, joker.eph, llvm-commits, cfe-commits

Differential Revision: http://reviews.llvm.org/D19796

llvm-svn: 269907
2016-05-18 11:56:23 +00:00
Paul Robinson 9d61361acb [PS4] Change the names of some "environmental" things to what our
licensees actually see in the toolchain we deliver to them.  This will
reduce the set of local patches we have to maintain.  The triple is
not changing.  (The term ORBIS is an internal code name for PS4.)

llvm-svn: 269671
2016-05-16 17:22:25 +00:00
Yaxun Liu 39cf40f6b4 [OpenCL] Add supported OpenCL extensions to target info.
Add supported OpenCL extensions to target info. It serves as default values to save the users of the burden setting each supported extensions and optional core features in command line.

Re-commit after fixing build error due to missing override attribute.

Differential Revision: http://reviews.llvm.org/D19484

llvm-svn: 269670
2016-05-16 17:06:34 +00:00
Tim Northover 862eaf8a12 ARM-MachO: stop claiming to be EABI
Embedded ARM MachO targets are AAPCS but not full EABI (we don't use
__aeabi_whatever and the functions are allowed to be hard-float).

Turns out there was already a test for this, but its original purpose had
become corrupted over the years.

llvm-svn: 269487
2016-05-13 21:26:45 +00:00
Yaxun Liu fa1df45c0d Revert "[OpenCL] Add supported OpenCL extensions to target info."
Revert r269431 due to build failure caused by warning msg:

  llvm/tools/clang/lib/Basic/Targets.cpp:2090:9: error: 'setSupportedOpenCLOpts' overrides a member function but is not marked 'override' [-Werror,-Winconsistent-missing-override]
   void setSupportedOpenCLOpts() {

llvm-svn: 269435
2016-05-13 17:16:26 +00:00
Yaxun Liu 64936ce91d [OpenCL] Add supported OpenCL extensions to target info.
Add supported OpenCL extensions to target info. It serves as default values to save the users of the burden setting each supported extensions and optional core features in command line.

Differential Revision: http://reviews.llvm.org/D19484

llvm-svn: 269431
2016-05-13 15:44:37 +00:00
Reid Kleckner 330fb175d4 Update clang support on recent Haiku
[ Copied from https://llvm.org/bugs/show_bug.cgi?id=26404 ]

clang support on Haiku is lagging a bit, and missing on x86_64.

This patch updates support for x86 and add support for x86_64. It should
apply directly to trunk and it's harmless in the sense that it only
affects Haiku.

Reviewers: rnk, rsmith

Patch by Jérôme Duval

Differential Revision: http://reviews.llvm.org/D16797

llvm-svn: 269201
2016-05-11 16:19:05 +00:00
Nemanja Ivanovic d99f21b0e6 [Power9] Enable -mcpu=pwr9 (-mcpu=power9) in the front end
This patch corresponds to review:
http://reviews.llvm.org/D19684

It simply adds the handling for the option and the corresponding macros.

llvm-svn: 268951
2016-05-09 18:58:02 +00:00
Nemanja Ivanovic bb1ea2d613 Enable support for __float128 in Clang and enable it on pertinent platforms
This patch corresponds to reviews:
http://reviews.llvm.org/D15120
http://reviews.llvm.org/D19125

It adds support for the __float128 keyword, literals and target feature to
enable it. Based on the latter of the two aforementioned reviews, this feature
is enabled on Linux on i386/X86 as well as SystemZ.
This is also the second attempt in commiting this feature. The first attempt
did not enable it on required platforms which caused failures when compiling
type_traits with -std=gnu++11.

If you see failures with compiling this header on your platform after this
commit, it is likely that your platform needs to have this feature enabled.

llvm-svn: 268898
2016-05-09 08:52:33 +00:00
Chris Dewhurst 69fa1926db [Sparc] Implement __builtin_setjmp, __builtin_longjmp back-end.
This code implements builtin_setjmp and builtin_longjmp exception handling intrinsics for 32-bit Sparc back-ends.

The code started as a mash-up of the PowerPC and X86 versions, although there are sufficient differences to both that had to be made for Sparc handling.

Note: I have manual tests running. I'll work on a unit test and add that to the rest of this diff in the next day.

Also, this implementation is only for 32-bit Sparc. I haven't focussed on a 64-bit version, although I have left the code in a prepared state for implementing this, including detecting pointer size and comments indicating where I suspect there may be differences.

Differential Revision: http://reviews.llvm.org/D19798

llvm-svn: 268483
2016-05-04 09:33:30 +00:00
Justin Lebar 76945b2f44 [CUDA] Copy host builtin types to NVPTXTargetInfo.
Summary:
Host and device types must match, otherwise when we pass values back and
forth between the host and device, we will get the wrong result.

This patch makes NVPTXTargetInfo inherit most of its type information
from the host's target info.

Reviewers: rsmith

Subscribers: cfe-commits, jhen, tra

Differential Revision: http://reviews.llvm.org/D19346

llvm-svn: 268131
2016-04-29 23:05:19 +00:00
Chris Bieneman 46977b62aa [Clang][Darwin] Define __ARM_DWARF_EH__ for WatchABI
Summary: The Darwin armv7k ABI uses Dwarf EH, so we need to set the OS define correctly. Without this the gcc_personality fails to build.

Reviewers: t.p.northover

Subscribers: aemerson, cfe-commits, rengolin

Differential Revision: http://reviews.llvm.org/D19693

llvm-svn: 268078
2016-04-29 17:53:00 +00:00
Tim Northover 28fc0e1fcd ARMv7k: define __ARM_PCS_VFP since we're hard-float.
It's a little debateable because we're not truly AAPCS, so I'm
certainly not going to define __ARM_PCS, but __ARM_PCS_VFP seems to be
really an "hard-float" define, which is a useful thing to have.

llvm-svn: 267880
2016-04-28 13:59:55 +00:00
Bryan Chan e3f1ed5805 [SystemZ] Support Swift calling convention
Summary:
Port rL265324 to SystemZ to allow using the 'swiftcall' attribute on that architecture.

Depends on D19414.

Reviewers: kbarton, rjmccall, uweigand

Subscribers: cfe-commits

Differential Revision: http://reviews.llvm.org/D19432

llvm-svn: 267879
2016-04-28 13:56:43 +00:00
Silviu Baranga 632fdc5919 PR27216: Only define __ARM_FEATURE_FMA when the target has VFPv4
Summary:
According to the ACLE spec, "__ARM_FEATURE_FMA is defined to 1 if
the hardware floating-point architecture supports fused floating-point
multiply-accumulate".

This changes clang's behaviour from emitting this macro for v7-A and v7-R
cores to only emitting it when the target has VFPv4 (and therefore support
for the floating point multiply-accumulate instruction).

Fixes PR27216

Reviewers: t.p.northover, rengolin

Subscribers: aemerson, rengolin, cfe-commits

Differential Revision: http://reviews.llvm.org/D18963

llvm-svn: 267869
2016-04-28 11:29:08 +00:00
Krzysztof Parzyszek a58ff5117a [Hexagon] Define architecture version macros for hexagonv55
llvm-svn: 266989
2016-04-21 14:30:04 +00:00
Krzysztof Parzyszek 7f0756cc1f [Hexagon] Define macros __HVX__ and __HVXDBL__ when appropriate
llvm-svn: 266647
2016-04-18 18:38:11 +00:00
Weiming Zhao b061313c5e [ARM] predefines __ELF__ macro for arm-none-eabi
Summary: predefines __ELF__ macro for arm-none-eabi

Reviewers: silviu.baranga, rengolin

Subscribers: aemerson, rengolin, cfe-commits

Differential Revision: http://reviews.llvm.org/D19225

llvm-svn: 266625
2016-04-18 16:25:46 +00:00
Nemanja Ivanovic d7d45bf8ce Revert 266186 as it breaks anything that includes type_traits on some platforms
Since this patch provided support for the __float128 type but disabled it
on all platforms by default, some platforms can't compile type_traits with
-std=gnu++11 since there is a specialization with __float128.
This reverts the patch until D19125 is approved (i.e. we know which platforms
need this support enabled).

llvm-svn: 266460
2016-04-15 18:04:13 +00:00
Nemanja Ivanovic 50f29e06a1 Enable support for __float128 in Clang
This patch corresponds to review:
http://reviews.llvm.org/D15120

It adds support for the __float128 keyword, literals and a target feature to
enable it. This support is disabled by default on all targets and any target
that has support for this type is free to add it.

Based on feedback that I've received from target maintainers, this appears to
be the right thing for most targets. I have not heard from the maintainers of
X86 which I believe supports this type. I will subsequently investigate the
impact of enabling this on X86.

llvm-svn: 266186
2016-04-13 09:49:45 +00:00
Saleem Abdulrasool c066d9cf55 Basic: fix profiling with GNU EABI
The GNU profiling support indicates that the interface is `_mcount` rather than
`mcount`.  Conditionalise the behaviour according to the `-meabi gnu` flag.

Resolves PR27311

llvm-svn: 266039
2016-04-12 03:05:03 +00:00
Saleem Abdulrasool 2a0932fb45 Correct pg instrumentation for AArch64
It seems that there was a miscommunication between Renato and I, and the
original behaviour of AArch64 was to be preserved and not to mirror the new
behaviour.  Restore the original behaviour for AArch64.  Addresses post-commit
review comments from Renato Golin.

llvm-svn: 265899
2016-04-10 14:29:55 +00:00
Saleem Abdulrasool 9b5ba547f1 Add support for __gnu_mcount_nc as the pg interface
This adds support to optionally support using `__gnu_mcount_nc` as the mcount
interface rather than `mcount` for Linux and EABI.  The other targets do not
provide an implementation for `__gnu_mcount_nc`.  This can be activated via the
`-meabi gnu` flag.

Resolves PR23969.

llvm-svn: 265888
2016-04-10 03:19:47 +00:00
Saleem Abdulrasool e86dd022c6 Basic: thread TargetOptions into TargetInfo
This threads TargetOptions into the TargetInfo hierarchy.  This is a rework of
the original attempt to thread additional information into the TargetInfo to
make decisions based on additional ABI related options.

llvm-svn: 265878
2016-04-09 19:09:25 +00:00
Saleem Abdulrasool 10a4972a8d revert SVN r265702, r265640
Revert the two changes to thread CodeGenOptions into the TargetInfo allocation
and to fix the layering violation by moving CodeGenOptions into Basic.
Code Generation is arguably not particularly "basic".  This addresses Richard's
post-commit review comments.  This change purely does the mechanical revert and
will be followed up with an alternate approach to thread the desired information
into TargetInfo.

llvm-svn: 265806
2016-04-08 16:52:00 +00:00
Saleem Abdulrasool 94cfc603d1 Basic: move CodeGenOptions from Frontend
This is a mechanical move of CodeGenOptions from libFrontend to libBasic.  This
fixes the layering violation introduced earlier by threading CodeGenOptions into
TargetInfo.  It should also fix the modules based self-hosting builds.  NFC.

llvm-svn: 265702
2016-04-07 17:49:44 +00:00
Saleem Abdulrasool 724275ba5f Basic: thread CodeGenOptions into TargetInfo
This threads CodeGenOptions into the TargetInfo hierarchy.  This is motivated by
ARM which can change some target information based on the EABI selected
(-meabi).  Similar options exist for other platforms (e.g. MIPS) and thus is
generally useful.  NFC.

llvm-svn: 265640
2016-04-07 05:41:11 +00:00
Andrey Turetskiy fd259ff9c4 [X86] Introduction of -march=lakemont.
Differential Revision: http://reviews.llvm.org/D18651

llvm-svn: 265405
2016-04-05 15:04:26 +00:00