Commit Graph

352229 Commits

Author SHA1 Message Date
Simon Pilgrim 7c7b77a341 MetadataLoader.h - remove unused MDNode forward declaration. NFC. 2020-04-22 14:01:52 +01:00
Simon Pilgrim 6f2d64696d [AsmParser] Remove unused forward declarations. NFC. 2020-04-22 14:01:51 +01:00
Simon Pilgrim 09ba6f9e69 X86TargetMachine.h - remove unused X86RegisterBankInfo forward declaration. NFC. 2020-04-22 14:01:51 +01:00
Sanjay Patel 6f19f0fb9a [InstCombine] add tests for min/max FP intrinsics with FMF (PR45478); NFC
https://bugs.llvm.org/show_bug.cgi?id=45478
2020-04-22 08:43:40 -04:00
David Green 48ac4e6938 [ARM] MVE FMA loop tests. NFC 2020-04-22 13:27:40 +01:00
Sebastian Neubauer bffd45bab1 [NFC][AMDGPU] Fix cmake when LLVM is a subproject
CMAKE_SOURCE_DIR is not the right directory if llvm is included in
another cmake project. PROJECT_SOURCE_DIR is always the same and should
be used instead.
2020-04-22 14:25:44 +02:00
Louis Dionne 8c61114c53 [libc++/abi/unwind] Rename Lit features for no exceptions to 'no-exceptions'
Instead of having different names for the same Lit feature accross code
bases, use the same name everywhere. This NFC commit is in preparation
for a refactor where all three projects will be using the same Lit
feature detection logic, and hence it won't be convenient to use
different names for the feature.

Differential Revision: https://reviews.llvm.org/D78370
2020-04-22 08:25:27 -04:00
Andrzej Warzynski 72f565899d [SveEmitter] Implement builtins for gathers/scatters
This patch adds builtins for:
  * regular, first-faulting and non-temporal gather loads
  * regular and non-temporal scatter stores

Differential Revision: https://reviews.llvm.org/D77735
2020-04-22 13:21:39 +01:00
Roman Lebedev 67266d879c
[InstCombine] Negator: shufflevector is negatible
All these folds are correct as per alive-tv
2020-04-22 15:14:23 +03:00
Roman Lebedev 4d44ce7437
[NFC][InstCombine] Add shuffle negation tests 2020-04-22 15:14:23 +03:00
Jay Foad dbdffe3ee9 [AMDGPU] Add 192-bit register classes
Differential Revision: https://reviews.llvm.org/D78312
2020-04-22 13:10:37 +01:00
Jay Foad d625b4b081 [AMDGPU] Add missing AReg classes
Add 96-bit, 160-bit and 256-bit AReg classes to match VReg and SReg.
NFC as far as I know, but it may avoid weird legalization problems.

Differential Revision: https://reviews.llvm.org/D78348
2020-04-22 13:10:37 +01:00
David Zarzycki b2f06bd20b [libc++ testing] Fix unused variable warning turned error 2020-04-22 08:05:31 -04:00
Peter Smith 673612a035 [LLD][ELF][ARM] Replace adr, ldr with .inst .reloc in test [NFC]
After D78301 MC no longer emits a relocation for this case. Change to use
.inst and .reloc to synthesize the same instruction and relocation. One
more test case I missed.
2020-04-22 12:55:26 +01:00
James Henderson e9aac2c3ef [llvm-objdump] Look in all viable sections for call/branch targets
Prior to this patch, llvm-objdump would only look in the last section
(according to the section header table order) that matched an address
for a symbol when identifying the target symbol of a call or branch
operation. If there are multiple sections with the same address, due to
some of them being empty, it did not look in those, even if the symbol
couldn't be found in the first section looked in.

This patch causes llvm-objdump to look in all sections for possible
candidate symbols. If there are multiple possible symbols, it picks one
from a non-empty section, if possible (as that is more likely to be the
"real" symbol since functions can't really be in emptiy sections),
before falling back to those in empty sections. If all else fails, it
falls back to absolute symbols as it did before.

Differential Revision: https://reviews.llvm.org/D78549

Reviewed by: grimar, Higuoxing
2020-04-22 12:28:30 +01:00
Lucas Prates 727e6fb84a [NFC][llvm][X86] Adding missing -mtiple to X86 test.
The modified test was missing the specification of the intended triple
in its run line, assuming X86 is the default.
2020-04-22 11:55:57 +01:00
Kerry McLaughlin 17f6e18acf [AArch64][SVE] Add SVE intrinsic for LD1RQ
Summary:
Adds the following intrinsic for contiguous load & replicate:
  - @llvm.aarch64.sve.ld1rq

The LD1RQ intrinsic only needs the SImmS16XForm added by this
patch. The others (SImmS2XForm, SImmS3XForm & SImmS4XForm)
were added for consistency.

Reviewers: andwar, sdesmalen, efriedma, cameron.mcinally, dancgr, rengolin

Reviewed By: sdesmalen

Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, danielkiss, cfe-commits, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D76929
2020-04-22 11:29:27 +01:00
Benjamin Kramer b198f1f86c Make some static class members constexpr
This allows them to be ODR used in C++17 mode. NFC.
2020-04-22 12:25:01 +02:00
Georgii Rymar 2bf5674317 [yaml2obj] - Program headers: add an additional check for `Offset`
The `Offset` field is used to set the file offset of a program header.
In a normal object it should not be greater than the minimal offset
of sections included into segment.

This patch adds a check for that and adds tests.

Differential revision: https://reviews.llvm.org/D78304
2020-04-22 12:49:05 +03:00
Georgii Rymar 87d33d9e09 [yaml2obj] - Change how p_offset is calculated when creating segments. NFCI.
This depends on D78361 and simplifies the computation of the `p_offset`.

Differential revision: https://reviews.llvm.org/D78363
2020-04-22 12:37:44 +03:00
Georgii Rymar 317c4913c6 [obj2yaml] - Fix the issue with dumping empty sections when dumping program headers.
Imagine we have:

```
ProgramHeaders:
  - Type:  PT_LOAD
    Flags: [ PF_W, PF_R ]
    Sections:
      - Section: .bar
    VAddr: 0x2000
Sections:
  - Name:    .foo
    Type:    SHT_PROGBITS
    Flags:   [ SHF_ALLOC, SHF_EXECINSTR ]
    Address: 0x1000
  - Name:    .bar
    Type:    SHT_PROGBITS
    Flags:   [ SHF_ALLOC, SHF_EXECINSTR ]
    Address: 0x2000
```

Both `.foo` and `.bar` share the same starting file offset,
but `VA(.foo)` < `VA(PT_LOAD)`, we should not include it into segment.

This patch fixes the issue.

Differential revision: https://reviews.llvm.org/D77652
2020-04-22 12:36:00 +03:00
Sjoerd Meijer 0736d1ccf3 [ARM][MVE] Tail-predication: some more comments and debug messages. NFC.
Finding the loop tripcount is the first crucial step in preparing a loop for
tail-predication, and this adds a debug message if a tripcount cannot be found.

And while I was at it, I added some more comments here and there.

Differential Revision: https://reviews.llvm.org/D78485
2020-04-22 10:34:23 +01:00
Sam McCall 161afc0106 [clangd] Remove vscode plugin: now https://github.com/clangd/vscode-clangd
Summary:
Moving this out of the monorepo for consistency with other editor plugins.
There's no version lock with clangd itself, and we never ran tests with lit.

The first version from the new repo has been published.

Reviewers: hokein

Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, kadircet, usaxena95, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D78598
2020-04-22 11:11:13 +02:00
Sjoerd Meijer 35cf2f42dd [Driver][docs] Document option -mtune as a no-op.
This documents that option -mtune is accepted for compatibility with GCC,
currently it has no effect, and thus does not currently perform any CPU type
specific tuning.

Corresponding discussion on the cfe dev list:
http://lists.llvm.org/pipermail/cfe-dev/2020-April/065169.html

Differential Revision: https://reviews.llvm.org/D78511
2020-04-22 09:15:48 +01:00
Jay Foad 7318625674 [AMDGPU] Remove obsolete special case for 1024-bit vector types. NFC. 2020-04-22 09:05:24 +01:00
Jay Foad 2fa17cdd7a [AMDGPU] Simplify definition of VReg and AReg classes. NFC.
Differential Revision: https://reviews.llvm.org/D78553
2020-04-22 08:59:28 +01:00
Frederik Gossen 0372db05bb [MLIR] Use nested symbol to identify kernel in `LaunchFuncOp`.
Summary:
Use a nested symbol to identify the kernel to be invoked by a `LaunchFuncOp` in the GPU dialect.
This replaces the two attributes that were used to identify the kernel module and the kernel within seperately.

Differential Revision: https://reviews.llvm.org/D78551
2020-04-22 07:44:29 +00:00
Frederik Gossen 648fc95083 [MLIR] Use `kernel` as a short hand for `gpu.kernel` attribute.
Summary:
Use the shortcu `kernel` for the `gpu.kernel` attribute of `gpu.func`.
The parser supports this and test cases are easier to read.

Differential Revision: https://reviews.llvm.org/D78542
2020-04-22 07:38:30 +00:00
Sam Parker 04ef154124 [NFC] Test changes
Add some more targets for the ARM cost model tests and add some tests
for icmps and bitcasts.
2020-04-22 08:28:52 +01:00
Frederik Gossen 2813802746 [MLIR] Fix test case for kernel attribute.
Summary:
Fix a broken test case in the `invalid.mlir` lit test case.
`expect` was missing its `e`.

Differential Revision: https://reviews.llvm.org/D78540
2020-04-22 07:27:39 +00:00
aartbik 5397f29087 [llvm] [X86] Make test more robust against different builds
Summary:
Rationale:
Using the --debug-only flag requires a debug build. Also, the debug output is not always consistent over different builds.
This change avoids all problems by just testing the generated assembly for AVX.

Reviewers: craig.topper, mehdi_amini, nicolasvasilache

Reviewed By: craig.topper

Subscribers: llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D78609
2020-04-22 00:23:46 -07:00
Raphael Isemann a53874b7e4 [lldb] Fix modules build by adding missing include
This header is using FileSpec so we should at least include the forward header.
2020-04-22 09:14:09 +02:00
Kazushi (Jam) Marukawa a6ef471919 [VE] Update shift operation instructions
Summary:
Changing all mnemonic to match assembly instructions to simplify mnemonic
naming rules. This time update all shift operation instructions.  This also
corrects instruction's operation kinds.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D78468
2020-04-22 09:10:10 +02:00
Kazushi (Jam) Marukawa ba4162c1c4 [VE] Add alternative names to registers
Summary:
VE uses identical names "%s0-63" to all generic registers.  Change to use
alternative name mechanism among all generic registers instead of hard-
coding them.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D78174
2020-04-22 09:07:42 +02:00
Craig Topper 05a11974ae [CallSite removal] Remove unneeded includes of CallSite.h. NFC 2020-04-22 00:07:13 -07:00
Alexander Belyaev 146d52e732 [MLIR] Verify there are no side-effecting ops in GenericAtomicRMWOp body.
Differential Revision: https://reviews.llvm.org/D78559
2020-04-22 09:02:58 +02:00
Stephan Herhut c22876b550 [MLIR] Add extra locking during cubin generation.
We also need to lock the LLVMDialect mutex when initializing
LLVM targets or destroying llvm modules concurrently. Added another
scoped lock to that effect.

Differential Revision: https://reviews.llvm.org/D78580
2020-04-22 08:57:45 +02:00
Alexander Belyaev 84e4c09995 [MLIR] Update documentation for loop.parallel.
Differential Revision: https://reviews.llvm.org/D78562
2020-04-22 08:48:49 +02:00
Johannes Doerfert ca59ff5af9 [Attributor] Replace AccessKind2Accesses map with an "array map"
The number of different access location kinds we track is relatively
small (8 so far). With this patch we replace the DenseMap that mapped
from index (0-7) to the access set pointer with an array of access set
pointers. This reduces memory consumption.

No functional change is intended.

---

Single run of the Attributor module and then CGSCC pass (oldPM)
for SPASS/clause.c (~10k LLVM-IR loc):

Before:
```
calls to allocation functions: 472499 (215654/s)
temporary memory allocations: 77794 (35506/s)
peak heap memory consumption: 35.28MB
peak RSS (including heaptrack overhead): 125.46MB
total memory leaked: 269.04KB
```

After:
```
calls to allocation functions: 472270 (308673/s)
temporary memory allocations: 77578 (50704/s)
peak heap memory consumption: 32.70MB
peak RSS (including heaptrack overhead): 121.78MB
total memory leaked: 269.04KB
```

Difference:
```
calls to allocation functions: -229 (346/s)
temporary memory allocations: -216 (326/s)
peak heap memory consumption: -2.58MB
peak RSS (including heaptrack overhead): 0B
total memory leaked: 0B
```

---
2020-04-22 01:35:27 -05:00
Johannes Doerfert f20ff4b17d [Attributor] Run IRPosition::verify only with EXPENSIVE_CHECKS 2020-04-22 01:35:12 -05:00
Craig Topper d22989c34e [CallSite removal][Target] Replace CallSite with CallBase. NFC
In some cases just delete an unneeded include.
2020-04-21 23:29:36 -07:00
Qiu Chaofan c12722cde8 [PowerPC] Exploit RLDIMI for OR with large immediates
This patch exploits rldimi instruction for patterns like
`or %a, 0b000011110000`, which saves number of instructions when the
operand has only one use, compared with `li-ori-sldi-or`.

Reviewed By: nemanjai

Differential Revision: https://reviews.llvm.org/D77850
2020-04-22 14:16:52 +08:00
Craig Topper daadb48553 [CallSite removal][TargetTransformInfoImpl] Replace CallSite with CallBase. NFC 2020-04-21 22:49:30 -07:00
Siva Chandra Reddy c08af2c11a [libc][NFC] Cleanup dependencies in src/signal and test/src/signal.
Reviewers: abrachet

Differential Revision: https://reviews.llvm.org/D78585
2020-04-21 22:25:01 -07:00
Igor Kudrin 1f48e22df8 [DebugInfo] Simplify DWARFUnit::determineStringOffsetsTableContribution(). NFC.
The method is called from only one place and the call is already guarded
by a condition which checks that IsDWO is false.

Differential Revision: https://reviews.llvm.org/D78482
2020-04-22 12:11:17 +07:00
Mehdi Amini 8dc790b933 Add `//` before the banner displayed in `--print-ir-before/after-all`
This is making the output file (when the stream is a file) a valid MLIR
file.

Differential Revision: https://reviews.llvm.org/D78604
2020-04-22 04:40:15 +00:00
Eli Friedman 46a52ff9ed [TargetPassConfig] Run MachineVerifier after more passes.
We were disabling verification for no reason in a bunch of places; just
turn it on.

At this point, there are two key places where we don't run verification:
during register allocation, and after addPreEmitPass.  Regalloc probably
isn't worth messing with; it has its own invariants, and verifying
afterwards is probably good enough.  For after addPreEmitPass, it's
probably worth investigating improvements.
2020-04-21 21:05:07 -07:00
Ian Levesque 5081468a66 [xray] Avoid text relocations in trampolines for ARM/AArch64
Summary: Switch to pc-relative lookup of the xray handler function to avoid text relocations.

Reviewers: MaskRay, dberris, johnislarry

Subscribers: kristof.beyls, danielkiss, #sanitizers

Tags: #sanitizers

Differential Revision: https://reviews.llvm.org/D78595
2020-04-21 23:21:02 -04:00
Ian Levesque eeaabe64e3 [xray] Use hidden symbol visibility for xray trampolines
Summary: We load multiple copies of the trampolines into memory when instrumenting DSOs.  Hidden visibility prevents conflicts in this scenario.

Reviewers: MaskRay, dberris, johnislarry

Subscribers: #sanitizers

Tags: #sanitizers

Differential Revision: https://reviews.llvm.org/D78593
2020-04-21 23:19:52 -04:00
Fangrui Song 8d45d6e39d [Frontend] Drop unneeded CC1 options 2020-04-21 19:59:28 -07:00