This implements a proper PPCAsmBackend::writeNopData routine
that actually writes PowerPC nop instructions.
This fixes the last remaining difference in object file output
(text section) between the integrated assembler and GNU as
that I've seen anywhere.
llvm-svn: 185662
* all transforms are in the same category
* all transforms' options are in the same category
* display the CommonOptionParser extra-help (which describe in more details the
compilation database stuff)
* add EXAMPLES section
Author: Guillaume Papin <guillaume.papin@epitech.eu>
llvm-svn: 185660
Some versions of python will expand the glob used in the test, others wont,
causing the test to fail when run with LIT_USE_INTERNAL_SHELL=1.
llvm-svn: 185653
This adds a new decoder table/namespace 'VFPV8', as these instructions have their
top 4 bits as 0b1111, while other Thumb instructions have 0b1110.
llvm-svn: 185642
The test was passing because clang would still print the ast before exiting
with an error. Since that didn't seem to be the intent of the test, I change
the test instead of adding 'not' to the command line.
llvm-svn: 185634
This adds support for specifying condition registers and
condition register fields via expressions using the symbols
defined by the PowerISA, like "4*cr2+eq".
llvm-svn: 185633
This allows us to create switches even if instcombine has munged two of the
incombing compares into one and some bit twiddling. This was motivated by enum
compares that are common in clang.
llvm-svn: 185632
Summary:
Always breaking before multiline strings can help format complex
expressions containing multiline strings more consistently, and avoid consuming
too much horizontal space.
Reviewers: djasper
Reviewed By: djasper
CC: cfe-commits, klimek
Differential Revision: http://llvm-reviews.chandlerc.com/D1097
llvm-svn: 185622
This is a follow-up patch for r185524. Being assert enabled does not mean
that DEBUG() is enabled, so we need to check the existence of DEBUG() itself.
llvm-svn: 185619
Stop using the ISD::EXCEPTIONADDR and ISD::EHSELECTION when lowering
landing pad arguments. These nodes were previously legalized into
CopyFromReg nodes, but that never worked properly because the
CopyFromReg node weren't guaranteed to be scheduled at the top of the
basic block.
This meant the exception pointer and selector registers could be
clobbered before being copied to a virtual register.
This patch copies the two physical registers to virtual registers at
the beginning of the basic block, and lowers the landingpad instruction
directly to two CopyFromReg nodes reading the *virtual* registers. This
is safe because virtual registers don't get clobbered.
A future patch will remove the ISD::EXCEPTIONADDR and ISD::EHSELECTION
nodes.
llvm-svn: 185617
Compute the insertion point from the end of the basic block instead of
skipping labels from the front.
This caused failures in landing pads when live-in copies where inserted
before instruction selection.
llvm-svn: 185616
Howard Hinnant