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105 Commits

Author SHA1 Message Date
Gabor Buella 3a7571259e [X86] ptwrite intrinsic 
Reviewers: craig.topper, RKSimon

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D46540

llvm-svn: 331962
 2018-05-10 07:28:54 +00:00
Gabor Buella b0f310d51d [x86] Introduce the pconfig intrinsic 
Reviewers: craig.topper, zvi

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D46431

llvm-svn: 331740
 2018-05-08 06:49:41 +00:00
Gabor Buella a51e0c2243 [X86] directstore and movdir64b intrinsics 
Reviewers: spatel, craig.topper, RKSimon

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D45984

llvm-svn: 331249
 2018-05-01 10:05:42 +00:00
Gabor Buella eba6c42e66 [X86] WaitPKG intrinsics 
Reviewers: craig.topper, zvi

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D45254

llvm-svn: 330463
 2018-04-20 18:44:33 +00:00
Gabor Buella f594ce739b [X86] Introduce archs: goldmont-plus & tremont 
Reviewers: craig.topper

Reviewed By: craig.topper

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D45613

llvm-svn: 330110
 2018-04-16 08:10:10 +00:00
Gabor Buella c9e976ce0c NFC - Indentation fixes in predefined-arch-macros.c 
Consistently separating tests with empty lines.
Helps while navigating this file.

Reviewers: craig.topper

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D45561

llvm-svn: 329932
 2018-04-12 18:15:39 +00:00
Gabor Buella a052016ef2 [x86] wbnoinvd intrinsic 
The WBNOINVD instruction writes back all modified
cache lines in the processor’s internal cache to main memory
but does not invalidate (flush) the internal caches.

Reviewers: craig.topper, zvi, ashlykov

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D43817

llvm-svn: 329848
 2018-04-11 20:09:09 +00:00
Gabor Buella 8701b18a25 [X86] Split up -march=icelake to -client & -server 
Reviewers: craig.topper, zvi, echristo

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D45056

llvm-svn: 329741
 2018-04-10 18:58:26 +00:00
Gabor Buella 5966507c4e [X86] Disable SGX for Skylake Server - CPP test 
Summary: Fix test case - corresponding to r329701

Reviewers: craig.topper, davezarzycki

Reviewed By: davezarzycki

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D45488

llvm-svn: 329710
 2018-04-10 15:03:03 +00:00
Craig Topper 94a940d2b4 [X86] Disable CLWB in Cannon Lake 
Cannon Lake does not support CLWB, therefore it
does not include all features listed under SKX.

Patch by Gabor Buella

Differential Revision: https://reviews.llvm.org/D43459

llvm-svn: 325655
 2018-02-21 00:16:50 +00:00
Walter Lee 637aafc451 [Myriad] Define __ma2x5x and __ma2x8x 
Summary: Add architecture defines for ma2x5x and ma2x8x.

Reviewers: jyknight

Subscribers: fedor.sergeev, MartinO

Differential Revision: https://reviews.llvm.org/D42882

llvm-svn: 324420
 2018-02-06 22:39:47 +00:00
Craig Topper ace5c37c57 [X86] Add 'rdrnd' feature to silvermont to match recent gcc bug fix. 
gcc recently fixed this bug https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83546

llvm-svn: 323552
 2018-01-26 19:34:45 +00:00
Craig Topper 8cdb94901d [X86] Add rdpid command line option and intrinsics. 
Summary: This patch adds -mrdpid/-mno-rdpid and the rdpid intrinsic. The corresponding LLVM commit has already been made.

Reviewers: RKSimon, spatel, zvi, AndreiGrischenko

Reviewed By: RKSimon

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D42272

llvm-svn: 323047
 2018-01-20 18:36:52 +00:00
Craig Topper c0b4aba786 [X86] Add missing check for RDSEED to ICL, CNL, SKX sections of test/Preprocessor/predefined-arch-macros.c 
llvm-svn: 322912
 2018-01-19 00:28:42 +00:00
Craig Topper d2fe244a6a Revert r321504 "[X86] Don't accidentally enable PKU on cannon lake and icelake or CLWB on cannonlake." 
I based that commit on what was in Intel's public documentation here https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf

Which specifically said CLWB wasn't until Icelake.

But I've since cross checked with SDE and it thinks these features exist on CNL and ICL. So now I don't know what to believe.

I've added test coverage of the current behavior as part of the revert so at least now have proof of what we're doing.

llvm-svn: 321547
 2017-12-29 06:39:16 +00:00
Craig Topper 520d055f66 [X86] Don't accidentally enable PKU on cannon lake and icelake or CLWB on cannonlake. 
We have cannonlake and icelake inheriting from skylake server in a switch using fallthroughs. But they aren't perfect supersets of skylake server.

llvm-svn: 321504
 2017-12-27 22:26:01 +00:00
Craig Topper 5bd93e99e2 [X86] Test that -march=skx enables PKU. 
llvm-svn: 321503
 2017-12-27 22:26:00 +00:00
Craig Topper b36447d346 [X86] Enable avx512vpopcntdq and clwb for icelake. 
Per table 1-1 of the October 2017 edition of Intel® Architecture Instruction Set Extensions and Future Features Programming Reference

llvm-svn: 321502
 2017-12-27 22:25:59 +00:00
Coby Tayree a09663a5c1 [x86][icelake][vbmi2] 
added vbmi2 feature recognition
added intrinsics support for vbmi2 instructions
_mm[128,256,512]_mask[z]_compress_epi[16,32]
_mm[128,256,512]_mask_compressstoreu_epi[16,32]
_mm[128,256,512]_mask[z]_expand_epi[16,32]
_mm[128,256,512]_mask[z]_expandloadu_epi[16,32]
_mm[128,256,512]_mask[z]_sh[l,r]di_epi[16,32,64]
_mm[128,256,512]_mask_sh[l,r]dv_epi[16,32,64]
matching a similar work on the backend (D40206)
Differential Revision: https://reviews.llvm.org/D41557

llvm-svn: 321487
 2017-12-27 11:25:07 +00:00
Coby Tayree 3d9c88cfec [x86][icelake][vnni] 
added vnni feature recognition
added intrinsics support for VNNI instructions
_mm256_mask_dpbusd_epi32
_mm256_maskz_dpbusd_epi32
_mm256_dpbusd_epi32
_mm256_mask_dpbusds_epi32
_mm256_maskz_dpbusds_epi32
_mm256_dpbusds_epi32
_mm256_mask_dpwssd_epi32
_mm256_maskz_dpwssd_epi32
_mm256_dpwssd_epi32
_mm256_mask_dpwssds_epi32
_mm256_maskz_dpwssds_epi32
_mm256_dpwssds_epi32
_mm128_mask_dpbusd_epi32
_mm128_maskz_dpbusd_epi32
_mm128_dpbusd_epi32
_mm128_mask_dpbusds_epi32
_mm128_maskz_dpbusds_epi32
_mm128_dpbusds_epi32
_mm128_mask_dpwssd_epi32
_mm128_maskz_dpwssd_epi32
_mm128_dpwssd_epi32
_mm128_mask_dpwssds_epi32
_mm128_maskz_dpwssds_epi32
_mm128_dpwssds_epi32
_mm512_mask_dpbusd_epi32
_mm512_maskz_dpbusd_epi32
_mm512_dpbusd_epi32
_mm512_mask_dpbusds_epi32
_mm512_maskz_dpbusds_epi32
_mm512_dpbusds_epi32
_mm512_mask_dpwssd_epi32
_mm512_maskz_dpwssd_epi32
_mm512_dpwssd_epi32
_mm512_mask_dpwssds_epi32
_mm512_maskz_dpwssds_epi32
_mm512_dpwssds_epi32
matching a similar work on the backend (D40208)
Differential Revision: https://reviews.llvm.org/D41558

llvm-svn: 321484
 2017-12-27 10:37:51 +00:00
Coby Tayree 2268576fa0 [x86][icelake][bitalg] 
added bitalg feature recognition
added intrinsics support for bitalg instructions
_mm512_popcnt_epi16
_mm512_mask_popcnt_epi16
_mm512_maskz_popcnt_epi16
_mm512_popcnt_epi8
_mm512_mask_popcnt_epi8
_mm512_maskz_popcnt_epi8
_mm512_mask_bitshuffle_epi64_mask
_mm512_bitshuffle_epi64_mask
_mm256_popcnt_epi16
_mm256_mask_popcnt_epi16
_mm256_maskz_popcnt_epi16
_mm128_popcnt_epi16
_mm128_mask_popcnt_epi16
_mm128_maskz_popcnt_epi16
_mm256_popcnt_epi8
_mm256_mask_popcnt_epi8
_mm256_maskz_popcnt_epi8
_mm128_popcnt_epi8
_mm128_mask_popcnt_epi8
_mm128_maskz_popcnt_epi8
_mm256_mask_bitshuffle_epi32_mask
_mm256_bitshuffle_epi32_mask
_mm128_mask_bitshuffle_epi16_mask
_mm128_bitshuffle_epi16_mask
matching a similar work on the backend (D40222)
Differential Revision: https://reviews.llvm.org/D41564

llvm-svn: 321483
 2017-12-27 10:01:00 +00:00
Coby Tayree cf96c876c6 [x86][icelake][vpclmulqdq] 
added vpclmulqdq feature recognition
added intrinsics support for vpclmulqdq instructions
  _mm256_clmulepi64_epi128
  _mm512_clmulepi64_epi128
matching a similar work on the backend (D40101)
Differential Revision: https://reviews.llvm.org/D41573

llvm-svn: 321480
 2017-12-27 09:00:31 +00:00
Coby Tayree f4811ebc39 [x86][icelake][gfni] 
added gfni feature recognition
added intrinsics support for gfni instructions
  _mm_gf2p8affineinv_epi64_epi8
  _mm_mask_gf2p8affineinv_epi64_epi8
  _mm_maskz_gf2p8affineinv_epi64_epi8
  _mm256_gf2p8affineinv_epi64_epi8
  _mm256_mask_gf2p8affineinv_epi64_epi8
  _mm256_maskz_gf2p8affineinv_epi64_epi8
  _mm512_gf2p8affineinv_epi64_epi8
  _mm512_mask_gf2p8affineinv_epi64_epi8
  _mm512_maskz_gf2p8affineinv_epi64_epi8
  _mm_gf2p8affine_epi64_epi8
  _mm_mask_gf2p8affine_epi64_epi8
  _mm_maskz_gf2p8affine_epi64_epi8
  _mm256_gf2p8affine_epi64_epi8
  _mm256_mask_gf2p8affine_epi64_epi8
  _mm256_maskz_gf2p8affine_epi64_epi8
  _mm512_gf2p8affine_epi64_epi8
  _mm512_mask_gf2p8affine_epi64_epi8
  _mm512_maskz_gf2p8affine_epi64_epi8
  _mm_gf2p8mul_epi8
  _mm_mask_gf2p8mul_epi8
  _mm_maskz_gf2p8mul_epi8
  _mm256_gf2p8mul_epi8
  _mm256_mask_gf2p8mul_epi8
  _mm256_maskz_gf2p8mul_epi8
  _mm512_gf2p8mul_epi8
  _mm512_mask_gf2p8mul_epi8
  _mm512_maskz_gf2p8mul_epi8
matching a similar work on the backend (D40373)
Differential Revision: https://reviews.llvm.org/D41582

llvm-svn: 321477
 2017-12-27 08:37:47 +00:00
Coby Tayree a1e5f0c339 [x86][icelake][vaes] 
added vaes feature recognition
added intrinsics support for vaes instructions, matching a similar work on the backend (D40078)
  _mm256_aesenc_epi128
  _mm512_aesenc_epi128
  _mm256_aesenclast_epi128
  _mm512_aesenclast_epi128
  _mm256_aesdec_epi128
  _mm512_aesdec_epi128
  _mm256_aesdeclast_epi128
  _mm512_aesdeclast_epi128

llvm-svn: 321474
 2017-12-27 08:16:54 +00:00
Craig Topper 921aff6e90 [X86] Add missing check lines for the silvermont cases in predefined-arch-macros.c test. 
llvm-svn: 321343
 2017-12-22 05:09:38 +00:00
Craig Topper 66b110edce [X86] Add 'prfchw' to the correct CPUs to match the backend. 
llvm-svn: 321341
 2017-12-22 04:51:00 +00:00
Craig Topper 546cee4170 [X86] Add icelake CPU support for -march. 
llvm-svn: 318617
 2017-11-19 02:55:15 +00:00
Craig Topper 222c1725cd [X86] Set __corei7__ preprocessor defines for skylake server and cannonlake. 
This is the resolution we came to in D38824.

llvm-svn: 318616
 2017-11-19 02:55:14 +00:00
Craig Topper a2b907a469 [X86] Define i586 and pentium preprocessor defines for -march=lakemont to match GCC 
llvm-svn: 317069
 2017-11-01 02:18:49 +00:00
Craig Topper a6021e3bc1 [X86] Make -march=i686 an alias of -march=pentiumpro 
I think the only reason they are different is because we don't set tune_i686 for -march=i686 to match GCC. But GCC 4.9.0 seems to have changed this behavior and they do set it now. So I think they can aliases now.

Differential Revision: https://reviews.llvm.org/D39349

llvm-svn: 316712
 2017-10-26 23:06:19 +00:00
Craig Topper 009cebfed8 [X86] Add avx512vpopcntdq to Knights Mill 
As indicated by Table 1-1 in Intel Architecture Instruction Set Extensions and Future Features Programming Reference from October 2017.

llvm-svn: 316593
 2017-10-25 17:10:58 +00:00
Jan Vesely cda72c9c3c AMDGPU: Parse r600 CPU name early and expose FMAF capability 
Improve amdgcn macro test
Differential Revision: https://reviews.llvm.org/D38667

llvm-svn: 316181
 2017-10-19 20:40:13 +00:00
Craig Topper 9c6a31ae1d [X86] Remove 'knm' defines from predefined-arch-macros.c test. 
Direction seems to be that we dont' want to keep adding these, but I forgot to remove it from the test before I committed r315723.

llvm-svn: 315729
 2017-10-13 18:38:10 +00:00
Craig Topper f8c10aa3a3 [X86] Add skeleton support for knm cpu 
This adds support Knights Mill CPU. Preprocessor defines match gcc's implementation.

Differential Revision: https://reviews.llvm.org/D38813

llvm-svn: 315723
 2017-10-13 18:14:24 +00:00
Craig Topper dfdafa2d32 [X86] Remove a few unnecessary check lines from the predefined-arch-macros test. 
These were testing OS macros and clang/llvm macros.

llvm-svn: 315547
 2017-10-12 02:06:17 +00:00
Walter Lee fc7f8f25f3 Add support for Myriad ma2x8x series of CPUs 
Summary:
Also:
- Add support for some older Myriad CPUs that were missing.
- Fix some incorrect compiler defines for exisitng CPUs.

Reviewers: jyknight

Subscribers: fedor.sergeev

Differential Revision: https://reviews.llvm.org/D37551

llvm-svn: 314706
 2017-10-02 18:50:57 +00:00
Michael Zuckerman 35731a0b84 [Clang] Adding missing feature to goldmont 
Change-Id: I6c22478d16b8e02ce60dae2f8c80d43bc5ab3a9c
llvm-svn: 314104
 2017-09-25 13:49:32 +00:00
Ulrich Weigand 76976a7920 [SystemZ] Add support for IBM z14 processor (2/3) 
This patch extends the -fzvector language feature to enable the new
"vector float" data type when compiling at -march=z14.  This matches
the updated extension definition implemented by other compilers for
the platform, which is indicated to applications by pre-defining
__VEC__ to 10302 (instead of 10301).

llvm-svn: 308198
 2017-07-17 17:46:47 +00:00
Ulrich Weigand cac24ab04c [SystemZ] Add support for IBM z14 processor (1/3) 
This patch series adds support for the IBM z14 processor.  This part includes:
- Basic support for the new processor and its features.
- Support for low-level builtins mapped to new LLVM intrinsics.

Support for the -fzvector extension to vector float and the new
high-level vector intrinsics is provided by separate patches.

llvm-svn: 308197
 2017-07-17 17:45:57 +00:00
Craig Topper 9dd7e808b3 [X86] Add RDRND feature to Goldmont. Add MOVBE to all Atom CPUs. 
Diffential Revision: https://reviews.llvm.org/D34842

llvm-svn: 306851
 2017-06-30 18:14:04 +00:00
Michael Zuckerman a046ef4c26 [Clang][X86][Goldmont]Adding new target-cpu: Goldmont 
[Clang-side] Connecting the GoldMont processor to his feature.


Reviewers:
1. igorb
2. delena
3. zvi


Differential Revision: https://reviews.llvm.org/D34807

llvm-svn: 306673
 2017-06-29 13:41:04 +00:00
Simon Pilgrim 0fd1b6c0dc [X86][LWP] Add __LWP__ macro tests 
Missed in rL302418

Differential Revision: https://reviews.llvm.org/D32770

llvm-svn: 302445
 2017-05-08 17:25:48 +00:00
Eric Christopher d26d8839d8 When we turn on vsx it should also turn on altivec explicitly, same 
with disabling it as well as disabling all vsx specific features when
turning off altivec.

Fixes PR32663.

llvm-svn: 300395
 2017-04-15 06:15:00 +00:00
Eric Christopher fc6ffede65 Default enable the rtm feature only on skylake and later for now because Intel disabled the feature on some haswell and broadwell processors: 
http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/core-m-processor-family-spec-update.pdf

the -mrtm option will still work normally.

llvm-svn: 298956
 2017-03-28 23:03:19 +00:00
Eric Christopher 74fa24ff27 Turn on HTM on power8 and later (including powerpc64le) since it's 
available by default on those cpus and configurations.

llvm-svn: 298307
 2017-03-20 21:12:53 +00:00
Craig Topper 4574226c3f [X86] Clzero flag addition and inclusion under znver1 
1. Adds the command line flag for clzero.
2. Includes the clzero flag under znver1.
3. Defines the macro for clzero.
4. Adds a new file which has the intrinsic definition for clzero instruction.

Patch by Ganesh Gopalasubramanian with some additional tests from me.

Differential revision: https://reviews.llvm.org/D29386

llvm-svn: 294559
 2017-02-09 06:10:14 +00:00
Craig Topper d2bf7b03e5 [X86] Add -mprefetchwt1/-mno-prefetchwt1 command line options and __PREFETCHWT1__ define to match gcc. 
llvm-svn: 294424
 2017-02-08 08:23:40 +00:00
Craig Topper 204ecffdb4 [X86] Add -msgx/-mno-sgx command line options and __SGX__ define to match gcc. 
llvm-svn: 294423
 2017-02-08 08:23:17 +00:00
Craig Topper b16cb82c93 [X86] Add -mmpx/-mno-mpx command line options and __MPX__ define to match gcc. 
llvm-svn: 294419
 2017-02-08 07:56:42 +00:00
Craig Topper 8c708cf6bc [X86] Add -mclwb/-mno-clwb command line arguments and __CLWB__ define to match gcc. 
In the future, we should also add a clwb intrinsic to the backend, a frontend builtin, and an instrinsic header file.

llvm-svn: 294416
 2017-02-08 07:36:58 +00:00