5b03f72292
Change X86 disassembly to print immediates values as signed by default. Special
...
case those instructions that the immediate is not sign-extend. radr://8795217
llvm-svn: 139028
2011-09-02 20:01:23 +00:00
370e923434
Thumb2 parsing and encoding for AND (register).
...
llvm-svn: 139021
2011-09-02 18:41:35 +00:00
2761155203
Thumb2 parsing and encoding for ADD (register).
...
llvm-svn: 139017
2011-09-02 18:14:46 +00:00
5c04c62765
Darwin wants ctors/dtors to be ordered the other way round to linux.
...
llvm-svn: 139015
2011-09-02 18:07:19 +00:00
54e09b4799
Fix the disassembly of the X86 "crc32w %ax, %eax" instruction. Bug 10702.
...
llvm-svn: 139014
2011-09-02 18:03:03 +00:00
b861b2b475
Tests for Thumb2 AND (immediate) instruction.
...
llvm-svn: 139013
2011-09-02 17:44:27 +00:00
63a3a0e010
Extra CHECK-NOT to make sure that GVN transform works properly.
...
llvm-svn: 139012
2011-09-02 17:40:39 +00:00
4a31ba3bae
-unroll-scev flag removal
...
llvm-svn: 139010
2011-09-02 17:36:14 +00:00
c302f5cce7
Add FIXME. Thumb2 ADR encoding choice is non-trivial.
...
llvm-svn: 139008
2011-09-02 17:21:59 +00:00
057d423e4b
ConstantVector returns arbitrary value for the wrong index.
...
This fixes PR10813.
llvm-svn: 139006
2011-09-02 15:43:43 +00:00
7470fb01d0
Compare type size instead of type _store_ size to make sure that BitCastInst
...
will be valid. This fixes PR10820.
llvm-svn: 139005
2011-09-02 14:57:37 +00:00
f5769c1070
Pass signed (not unsigned) 10 bit field to SPU 'ori' instruction.
...
llvm-svn: 139004
2011-09-02 10:05:01 +00:00
94ce535647
Make IC_VEX* not inherit from IC_*. Prevents instructions with no VEX form from disassembling to their non-VEX form. Also prevents weak filter collisons that were keeping valid VEX instructions from decoding properly. Make VEX_L* not inherit from VEX_* because the VEX.L bit always important. This stops packed int VEX encodings from being disassembled when specified with VEX.L=1. Fixes PR10831 and PR10806.
...
llvm-svn: 138997
2011-09-02 04:17:54 +00:00
723cec7a5f
Update to new EH scheme.
...
llvm-svn: 138989
2011-09-02 01:25:11 +00:00
3767be9aee
Revert r131152, r129796, r129761. This code is currently considered
...
to be unreliable on platforms which require memcpy calls, and it is
complicating broader legalize cleanups. It is hoped that these cleanups
will make memcpy byval easier to implement in the future.
llvm-svn: 138977
2011-09-01 23:07:08 +00:00
6397051ece
Don't drop alignment info on local common symbols.
...
- On COFF the .lcomm directive has an alignment argument.
- On ELF we fall back to .local + .comm
Based on a patch by NAKAMURA Takumi.
Fixes PR9337, PR9483 and PR10128.
llvm-svn: 138976
2011-09-01 23:04:27 +00:00
4028a51c74
Fix test; sorry for any inconvenience.
...
llvm-svn: 138966
2011-09-01 21:25:42 +00:00
71f5c2f158
Fix an issue with the IR sink pass found by inspection. (I'm not sure anyone is actually using this, but might as well fix it since I found the issue.)
...
llvm-svn: 138965
2011-09-01 21:21:24 +00:00
cc6e92892f
Add missing newline.
...
llvm-svn: 138964
2011-09-01 21:20:11 +00:00
c032617581
XFAIL this test on arm until the backend is fixed.
...
llvm-svn: 138955
2011-09-01 18:40:03 +00:00
0f6ff8cb2b
This test depends on cmov being available.
...
llvm-svn: 138954
2011-09-01 18:40:01 +00:00
5dc87d0f4d
Permit remat of partial register defs when it is safe.
...
An instruction may define part of a register where the other bits are
undefined. In that case, it is safe to rematerialize the instruction.
For example:
%vreg2:ssub_0<def> = VLDRS <cp#0>, 0, pred:14, pred:%noreg, %vreg2<imp-def>
The extra <imp-def> operand indicates that the instruction does not read
the other parts of the virtual register, so a remat is safe.
This patch simply allows multiple def operands for the virtual register.
It is MI->readsVirtualRegister() that determines if we depend on a
previous value so remat is impossible.
llvm-svn: 138953
2011-09-01 18:27:51 +00:00
f6d5d60f99
ARM 'rscs' mnemonic is carry-setting 'rsc', not 'rs' with a 'cs' condition code.
...
llvm-svn: 138952
2011-09-01 18:22:13 +00:00
f61d1c072e
Fix vbroadcast matching logic to early unmatch if the node doesn't have
...
only one use. Fix PR10825.
llvm-svn: 138951
2011-09-01 18:15:06 +00:00
35d240f9e8
t2Bcc is allowed to have a predicate without a preceding IT instruction.
...
llvm-svn: 138946
2011-09-01 17:47:45 +00:00
6357fa2f06
Prevent remat of partial register redefinitions.
...
An instruction that redefines only part of a larger register can never
be rematerialized since the virtual register value depends on the old
value in other parts of the register.
This was fixed for the inline spiller in r138794. This patch fixes the
problem for all register allocators, and includes a small test case.
<rdar://problem/10032939>
llvm-svn: 138944
2011-09-01 17:18:50 +00:00
185d377597
Update to new EH scheme.
...
llvm-svn: 138933
2011-09-01 01:28:25 +00:00
d33e3007fa
Update to new EH scheme.
...
llvm-svn: 138928
2011-09-01 01:08:21 +00:00
3b17c1b48d
Update to new EH scheme.
...
llvm-svn: 138927
2011-09-01 01:02:41 +00:00
e88632d667
Update some tests to the new EH scheme.
...
llvm-svn: 138925
2011-09-01 00:58:03 +00:00
832a6a1909
PreRA scheduler should avoid cloning compares.
...
Added canClobberReachingPhysRegUse() to handle a particular pattern in
which a two-address instruction could be forced to interfere with
EFLAGS, causing a compare to be unnecessarilly cloned.
Fixes rdar://problem/5875261
llvm-svn: 138924
2011-09-01 00:54:31 +00:00
1d3c137839
Thumb2 assembly parsing and encoding for ADD(immediate).
...
llvm-svn: 138922
2011-09-01 00:28:52 +00:00
080f40a49d
Reenable test.
...
llvm-svn: 138916
2011-08-31 23:08:05 +00:00
54b91028f0
Revert accidental commit
...
llvm-svn: 138915
2011-08-31 23:07:46 +00:00
c472975fd9
Disable this test until Bill fixes it properly.
...
llvm-svn: 138914
2011-08-31 23:03:30 +00:00
5624fe0cff
Update to new EH scheme.
...
llvm-svn: 138908
2011-08-31 21:50:07 +00:00
e336599f6d
Update to new EH scheme.
...
llvm-svn: 138906
2011-08-31 21:44:24 +00:00
55fb73a6e0
Remove old declare statements.
...
llvm-svn: 138905
2011-08-31 21:41:20 +00:00
22055c713f
Update more tests to the new EH scheme.
...
llvm-svn: 138904
2011-08-31 21:40:15 +00:00
d4e871404d
Update more tests to the new EH scheme.
...
llvm-svn: 138903
2011-08-31 21:39:05 +00:00
293c31b81c
Add tests for the transformations SCCP can do on atomic loads and stores (which are safe without any modifications).
...
llvm-svn: 138902
2011-08-31 21:37:06 +00:00
c4c24f03e9
Revert r138894. This was failing on cmake-clang-i686-msvc10.
...
llvm-svn: 138900
2011-08-31 21:20:25 +00:00
e6174a2c85
Update more tests to the new EH scheme.
...
llvm-svn: 138894
2011-08-31 21:04:11 +00:00
b1e680fd3f
Update the tests to the new EH scheme.
...
llvm-svn: 138891
2011-08-31 20:55:40 +00:00
a455a0b1e7
Fix encoding for tBcc with immediate offset operand.
...
llvm-svn: 138889
2011-08-31 20:26:14 +00:00
6a69d6902f
Run the Thumb1 parser tests in Thumb2 mode, as well.
...
Thumb2 is a superset of Thumb1, so all of the encodings should still work.
llvm-svn: 138883
2011-08-31 19:50:28 +00:00
6eb213c919
Thumb NOP encoding varies depending on ARCH revision.
...
llvm-svn: 138876
2011-08-31 18:35:46 +00:00
5c160fd243
Fix roundtripping of Thumb BL/BLX instructions with immediate offsets instead of labels.
...
llvm-svn: 138874
2011-08-31 18:30:20 +00:00
7c3bdede25
Generic expansion for atomic load/store into cmpxchg/atomicrmw xchg; implements 64-bit atomic load/store for ARM.
...
llvm-svn: 138872
2011-08-31 18:26:09 +00:00
af8c3cc710
Thumb2 parsing and encoding for ADC(register).
...
Also add instruction aliases for non-.w versions of SBC since they're the
same.
llvm-svn: 138871
2011-08-31 18:23:08 +00:00
Kevin Enderby