Commit Graph

346151 Commits

Author SHA1 Message Date
James Henderson b259ce998f [llvm-readobj] Derive dynamic symtab size from DT_HASH
If the section headers have been removed by a tool such as llvm-objcopy
or llvm-strip, previously llvm-readobj/llvm-readelf would not dump the
dynamic symbols when --dyn-symbols was specified. However, the nchain
value of the DT_HASH data specifies the number of dynamic symbols, so if
it is present, we can use that. This patch implements this behaviour.

Fixes https://bugs.llvm.org/show_bug.cgi?id=45089.

Reviewed by: grimar, MaskRay

Differential Revision: https://reviews.llvm.org/D76352
2020-03-23 12:21:20 +00:00
Simon Pilgrim 72d1419bfb [InstCombine] Add CTPOP -> CTTZ simplifications (PR43513)
As detailed on PR43513, we can simplify:

ctpop(x | -x) -> bitwidth - cttz(x, false)
Alive2: http://volta.cs.utah.edu:8080/z/caw49X

ctpop(~x & (x - 1)) -> cttz(x, false)
Alive2: http://volta.cs.utah.edu:8080/z/5zfVrx

I've tweaked the initial test cases I added at rG2d712fb75584 to increase commutativity testing.

Differential Revision: https://reviews.llvm.org/D76568
2020-03-23 11:04:33 +00:00
Momchil Velikov 6081ccf4a3 Apply function attributes through array declarators
There's inconsistency in handling array types between the
`distributeFunctionTypeAttrXXX` functions and the
`FunctionTypeUnwrapper` in `SemaType.cpp`.

This patch lets `FunctionTypeUnwrapper` apply function type attributes
through array types.

Differential Revision: https://reviews.llvm.org/D75109
2020-03-23 11:03:13 +00:00
Christian Sigg b43ae21e60 Fix all-reduce int tests by host-registering memrefs.
Reduce amount of boiler plate to register host memory.

Summary: Fix all-reduce int tests by host-registering memrefs.

Reviewers: herhut

Reviewed By: herhut

Subscribers: clementval, mehdi_amini, rriddle, jpienaar, burmako, shauheen, antiagainst, nicolasvasilache, arpith-jacob, mgester, lucyrfox, liufengdb, Joonsoo, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D76563
2020-03-23 11:48:13 +01:00
Guillaume Chatelet ea64ee0edb [Alignment][NFC] Deprecate ensureMaxAlignment
Summary:
This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790

Reviewers: courbet

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D76368
2020-03-23 11:31:33 +01:00
Simon Pilgrim 6a6a83c6e9 MergeFunctions.rst - multiply vs shift typo (PR44717)
The doc is suggesting that a mul-by-2 is the same as a ashr-by-1 instead of shl-by-1

Differential Revision: https://reviews.llvm.org/D76566
2020-03-23 10:13:25 +00:00
Whisperity df5fa48739 [clang-tidy][NFC] Add missing check group docs and order entries
Differential Revision: https://reviews.llvm.org/D76541
2020-03-23 11:05:34 +01:00
Jay Foad 7cdbf1ed4b Make use of APInt::countLeadingOnes. NFC. 2020-03-23 09:08:20 +00:00
Sam Parker 62fdb1f534 [DAGCombine] Skip PostInc combine with later users
When decided whether to generate a post-inc load/store, look at the
other memory nodes that use the same base address and, if any proceed
the current node, then don't do the combine.
The change only seems to be affecting the Arm backend, which I was
surprised at, but it appears to fix a lot of our issues around MVE
masked load/stores having to store a temporary address after an early
post-increment on a shared base address.

Differential Revision: https://reviews.llvm.org/D75847
2020-03-23 08:39:53 +00:00
Sam Parker 8e45eaf1da [NFC][DAGCombine] Refactor post-inc logic
Extract the decision to combine into a post-inc address into a
couple of functions to make the logic more clear and re-usable.

Differential Revision: https://reviews.llvm.org/D76060
2020-03-23 08:32:20 +00:00
Dominik Montada ccf49b9ef0 [GlobalISel] support widen unmerge if WideTy > SrcTy
Summary:
Widening G_UNMERGE_VALUES to a type which is larger than the
original source type is the same as widening it to the same
type as the source type: in both cases, G_UNMERGE_VALUES has
to be replaced with bit arithmetic which. Although the arithmetic
itself is independent of whether the source type is smaller
or equal to the widen type, widening the source type to the
widen type should result in less artifacts being emitted,
since this is the type that the user explicitly requested.

Reviewers: arsenm, dsanders, aemerson, aditya_nandakumar

Reviewed By: arsenm, dsanders

Subscribers: jvesely, wdng, nhaehnle, rovka, hiraditya, volkan, kerbowa, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D76494
2020-03-23 09:16:45 +01:00
Fangrui Song 0cc124c186 [llvm-objdump][test] Improve PowerPC branch offset tests 2020-03-23 00:07:21 -07:00
Alex Brachet a1762f9ceb [libc] Don't configure test and fuzzer when -DLLVM_INCLUDE_TESTS=OFF
Summary:  Fixes problem reported in D74397#1935863

Reviewers: nathanchance, gchatelet, sivachandra, MaskRay

Reviewed By: sivachandra, MaskRay

Subscribers: mgorny, MaskRay, tschuett

Differential Revision: https://reviews.llvm.org/D76577
2020-03-23 01:50:16 -04:00
David Blaikie 2ec59a0a40 Buildbot debugging of 0d0b90105f (lambda/function_ref lifetime issues)
This is failing on several buildbots with some inexplicable (to me,
right now) crashes. Let's see if this change is adequate to unblock the
buildbots & further understanding can be gained later.
2020-03-22 22:43:44 -07:00
Juneyoung Lee 5792c2236d Add test cases that are addressed by D76010 2020-03-23 13:49:29 +09:00
Qiu Chaofan 196b48a224 [NFC] [PowerPC] Prepare test for FMA negate check
This patch adds a test file, covering outputs when some operands in FMA
is negative.
2020-03-23 11:40:07 +08:00
Uday Bondhugula b873761496 [MLIR][NFC] Move some of the affine transforms / tests to dialect dirs
Move some of the affine transforms and their test cases to their
respective dialect directory. This patch does not complete the move, but
takes care of a good part.

Renames: prefix 'affine' to affine loop tiling cl options,
vectorize -> super-vectorize

Signed-off-by: Uday Bondhugula <uday@polymagelabs.com>

Differential Revision: https://reviews.llvm.org/D76565
2020-03-23 08:25:07 +05:30
Uday Bondhugula 56e1c20bfd [MLIR][NFC] rename ConvertStandardToLLVM, ConvertLoopToStandard to drop Convert prefix
This is in line with the convention agreed on https://llvm.discourse.group/t/rfc-canonical-file-paths-to-dialects/621

Signed-off-by: Uday Bondhugula <uday@polymagelabs.com>

Differential Revision: https://reviews.llvm.org/D76583
2020-03-23 08:24:11 +05:30
David Blaikie 0d0b90105f Revert "[FIX] Do not copy an llvm::function_ref if it has to be reused"
This fix doesn't seem to be right (function_ref can/should be passed by
value) so I'm reverted it to see if the buildbots decide to explain
what's wrong.

This reverts commit 857bf5da35.
2020-03-22 18:43:39 -07:00
David Blaikie 5d4c1c00e6 Roll an expression into an assert to remove the need for a (void) cast. 2020-03-22 18:18:27 -07:00
Craig Topper e2cb121374 [X86] Remove maximum vector length limit from combineBasicSADPattern.
createPSADBW uses SplitsOpsAndApply so should be able to handle
any size.

Restrict the extract result type to i32 or i64 since that's what
we have coverage for today and probably matches what the
isSimple() check gave us before.

Differential Revision: https://reviews.llvm.org/D76560
2020-03-22 15:02:05 -07:00
Sylvestre Ledru 986051749c doc: use the right url to bugzilla 2020-03-22 22:49:40 +01:00
Sylvestre Ledru 72fd1033ea Doc: Links should use https 2020-03-22 22:49:33 +01:00
Florian Hahn 006244152d [SCCP] Add a few more tests for conditional propagation,XOR. 2020-03-22 21:43:33 +00:00
Sylvestre Ledru ea4ec17208 update of the llvm doc: we moved to git 2020-03-22 22:36:21 +01:00
Craig Topper f4c67dfa92 [X86] More accurately model the cost of horizontal reductions.
This patch attempts to more accurately model the reduction of
power of 2 vectors of types we natively support. This takes into
account the narrowing of vectors that occur as we go from 512
bits to 256 bits, to 128 bits. It also takes into account the use
of wider elements in the shuffles for the first 2 steps of a
reduction from 128 bits. And uses a v8i16 shift for the final step
of vXi8 reduction.

The default implementation uses the legalized type for the arithmetic
for all levels. And uses the single source permute cost of the
legalized type for all levels. This penalizes things like
lack of v16i8 pshufb on pre-sse3 targets and the splitting and
joining that needs to be done for integer types on AVX1. We never
need v16i8 shuffle for a reduction and we only need split AVX1 ops
when type the type wide and needs to be split. I think we're still
over costing splits and joins for AVX1, but we're closer now.

I've also removed all pairwise special casing because I don't
think we ever want to generate that on X86. I've also adjusted
the add handling to more accurately account for any type splitting
that occurs before we reach a legal type.

Differential Revision: https://reviews.llvm.org/D76478
2020-03-22 14:20:15 -07:00
Sylvestre Ledru 7cfd5de61b clang/release notes: s/Subversion/git/ 2020-03-22 22:18:40 +01:00
Simon Atanasyan 2dc4eb08cd [mips] Implement .cpadd directive
This directive inserts code to add $gp to the argument's register when
support for position independent code is enabled.

For example, this code:
  .cpadd $4
expands to:
  addu $4, $4, $gp
2020-03-22 23:34:32 +03:00
Simon Atanasyan 9bbddfbeaa [mips] Implement sne pseudo instruction
The `sne Dst, Src1, Src2/Imm` pseudo instruction sets register `Dst` to
1 if register `Src1` is not equal to `Src2/Imm` and to 0 otherwise.
2020-03-22 23:34:31 +03:00
Simon Atanasyan dca9e40c0c [mips] Implement sle/sleu pseudo instructions
The `sle/sleu Dst, Src1, Src2/Imm` pseudo instructions set register
`Dst` to 1 if register `Src1` is less than or equal `Src2/Imm` and
to 0 otherwise.
2020-03-22 23:34:31 +03:00
Simon Atanasyan 862f120fdb [mips] Remove instructions related to "wired paired single" from the P5600 model. 2020-03-22 23:34:31 +03:00
Simon Atanasyan ecc92fd018 [mips] Add HasMips3D to the list of features unsupported by P5600 model. 2020-03-22 23:34:31 +03:00
Simon Atanasyan 0f15ace018 [mips] Rename target feature Mips3D => HasMips3D. NFC 2020-03-22 23:34:31 +03:00
Jacques Pienaar bb621cac3d [mlir] Change include image to be toplevel
This will match the changes mlir.llvm.org side.
2020-03-22 13:13:17 -07:00
Alex Brachet 0e1e9b9a81 [libc][NFC] Fix typo in milliseconds 2020-03-22 15:11:22 -04:00
Yaxun (Sam) Liu 78957bab55 [NFC] Refactor handling of Xarch option
Extract common code to a function. To prepare for
adding an option for CUDA/HIP host and device only
option.

Differential Revision: https://reviews.llvm.org/D76455
2020-03-22 14:42:09 -04:00
Yaxun (Sam) Liu 314deab9af Add Triple::isAMDGPU
Differential Revision: https://reviews.llvm.org/D57707
2020-03-22 14:20:28 -04:00
Alex Brachet ca04d0c8fd [libc] Add signal
Summary:
This patch adds a Linux implementation for `signal`
It also fixes `ASSERT|EXPECT_THAT` macros

Reviewers: sivachandra, PaulkaToast, MaskRay

Reviewed By: sivachandra

Subscribers: mgorny, tschuett, libc-commits

Differential Revision: https://reviews.llvm.org/D76536
2020-03-22 14:15:47 -04:00
Craig Topper b89ae50795 [X86] Remove maximum vector width restriction from combineLoopSADPattern.
SplitsOpsAndApply will take care of any needed splitting correctly.
All that we need to check is that the vector element count is a
power of 2.

Differential Revision: https://reviews.llvm.org/D76558
2020-03-22 11:09:14 -07:00
Nico Weber 2655d1b457 Remove a dead function. 2020-03-22 13:27:51 -04:00
Matt Arsenault b76bbcc60d Verifier: Check bswap is supported size
Make sure it is a multiple of 2 bytes as specified in the LangRef.
2020-03-22 12:15:25 -04:00
Nikita Popov dc81923659 [InstCombine] Remove ExpensiveCombines option
D75801 removed the last and only user of this option, so we can
drop it now. The original idea behind this was to only run expensive
transforms under -O3, but apart from the one known bits transform,
this has never really taken off. I believe nowadays the recommendation
is to put expensive transforms in AggressiveInstCombine instead,
though that isn't terribly popular either :)

Differential Revision: https://reviews.llvm.org/D76540
2020-03-22 16:56:28 +01:00
Matt Arsenault 830cfda19f Utils: Mostly convert memcpy expansion to use Align
The TTI hooks aren't converted. I also think the intrinsics should
have mandatory alignment and never return MaybeAlign.
2020-03-22 11:21:44 -04:00
Qiu Chaofan 763871053c [DAGCombiner] Require nsz for aggressive fma fold
For folding pattern `x-(fma y,z,u*v) -> (fma -y,z,(fma -u,v,x))`, if
`yz` is 1, `uv` is -1 and `x` is -0, sign of result would be changed.

Differential Revision: https://reviews.llvm.org/D76419
2020-03-22 23:10:07 +08:00
Qiu Chaofan 996dc13dc4 [NFC] [PowerPC] Remove unsafe-fp-math in FMA test 2020-03-22 22:40:49 +08:00
Simon Pilgrim 0105e9cd92 [X86][SSE] Add some additional irregular AVG tests
Finally resurrecting D56506 and want to improve test coverage.
2020-03-22 14:28:31 +00:00
Bjorn Pettersson d077d678d3 [ValueTracking] Avoid blind cast from Operator to Instruction
Summary:
Avoid blind cast from Operator to ExtractElementInst in
computeKnownBitsFromOperator. This resulted in some crashes
in downstream fuzzy testing. Instead we use getOperand directly
on the Operator when accessing the vector/index operands.

Haven't seen any problems with InsertElement and ShuffleVector,
but I believe those could be used in constant expressions as well.
So the same kind of fix as for ExtractElement was also applied for
InsertElement.

When it comes to ShuffleVector we now simply bail out if a dynamic
cast of the Operator to ShuffleVectorInst fails. I've got no
reproducer indicating problems for ShuffleVector, and a fix would be
slightly more complicated as getShuffleDemandedElts is involved.

Reviewers: RKSimon, nikic, spatel, efriedma

Reviewed By: RKSimon

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D76564
2020-03-22 14:45:31 +01:00
Nikita Popov a63eaa5449 [SLP] Avoid repeated visitation in getVectorElementSize(); NFC
We need to insert into the Visited set at the same time we insert
into the worklist. Otherwise we may end up pushing the same
instruction to the worklist multiple times, and only adding it to
the visited set later.
2020-03-22 14:34:29 +01:00
Qiu Chaofan c1bc56bf4f [NFC] [PowerPC] Update FMA association test 2020-03-22 20:55:32 +08:00
River Riddle e8f5c072f6 [mlir] Move the testing pass for GpuKernelToCubin to the test/ directory
Summary:
This removes the static pass registration, and also cleans up some lingering technical debt.

Differential Revision: https://reviews.llvm.org/D76554
2020-03-22 03:38:09 -07:00