Commit Graph

33 Commits

Author SHA1 Message Date
Fangrui Song 6b3351792c [test] Add {{.*}} to make tests immune to dso_local/dso_preemptable/(none) differences
For a definition (of most linkage types), dso_local is set for ELF -fno-pic/-fpie
and COFF, but not for Mach-O.  This nuance causes unneeded binary format differences.

This patch replaces (function) `define ` with `define{{.*}} `,
(variable/constant/alias) `= ` with `={{.*}} `, or inserts appropriate `{{.*}} `
if there is an explicit linkage.

* Clang will set dso_local for Mach-O, which is currently implied by TargetMachine.cpp. This will make COFF/Mach-O and executable ELF similar.
* Eventually I hope we can make dso_local the textual LLVM IR default (write explicit "dso_preemptable" when applicable) and -fpic ELF will be similar to everything else. This patch helps move toward that goal.
2020-12-30 20:52:01 -08:00
Matt Arsenault 0a7cd99a70 Reapply "OpaquePtr: Add type to sret attribute"
This reverts commit eb9f7c28e5.

Previously this was incorrectly handling linking of the contained
type, so this merges the fixes from D88973.
2020-10-16 11:05:02 -04:00
Tres Popp eb9f7c28e5 Revert "OpaquePtr: Add type to sret attribute"
This reverts commit 55c4ff91bd.

Issues were introduced as discussed in https://reviews.llvm.org/D88241
where this change made previous bugs in the linker and BitCodeWriter
visible.
2020-09-29 10:31:04 +02:00
Matt Arsenault 55c4ff91bd OpaquePtr: Add type to sret attribute
Make the corresponding change that was made for byval in
b7141207a4. Like byval, this requires a
bulk update of the test IR tests to include the type before this can
be mandatory.
2020-09-25 14:07:30 -04:00
Erik Pilkington de98cf92e3 [CodeGen] Add an alignment attribute to all sret parameters
This fixes a miscompile when the parameter is actually underaligned.
rdar://58316406

Differential revision: https://reviews.llvm.org/D74183
2020-03-24 15:31:57 -04:00
Fangrui Song dbc96b518b Revert "[CodeGenModule] Assume dso_local for -fpic -fno-semantic-interposition"
This reverts commit 789a46f2d7.

Accidentally committed.
2020-02-03 10:09:39 -08:00
Fangrui Song 789a46f2d7 [CodeGenModule] Assume dso_local for -fpic -fno-semantic-interposition
Summary:
Clang -fpic defaults to -fno-semantic-interposition (GCC -fpic defaults
to -fsemantic-interposition).
Users need to specify -fsemantic-interposition to get semantic
interposition behavior.

Semantic interposition is currently a best-effort feature. There may
still be some cases where it is not handled well.

Reviewers: peter.smith, rnk, serge-sans-paille, sfertile, jfb, jdoerfert

Subscribers: dschuff, jyknight, dylanmckay, nemanjai, jvesely, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, sabuasal, niosHD, jrtc27, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, arphaman, PkmX, jocewei, jsji, Jim, lenary, s.egerton, pzheng, sameer.abuasal, apazos, luismarques, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D73865
2020-02-03 09:52:48 -08:00
Tim Northover c46827c7ed LLVM IR: Generate new-style byval-with-Type from Clang
LLVM IR recently added a Type parameter to the byval Attribute, so that
when pointers become opaque and no longer have an element type the
information will still be present in IR.

For now the Type parameter is optional (which is why Clang didn't need
this change at the time), but it will become mandatory soon.

llvm-svn: 362652
2019-06-05 21:12:14 +00:00
Shoaib Meenai c4cf3daad8 [ARM] Remove redundant #if in test. NFC
Both sides of this #if #include the same file. Drop the #if, leaving only the #include.

Patch by Matt Glazar.

Differential Revision: https://reviews.llvm.org/D45779

llvm-svn: 331305
2018-05-01 20:38:05 +00:00
Tim Northover d157e19562 ARM: use ABI-specified alignment for byval parameters.
When passing a type with large alignment byval, we were specifying the type's
alignment rather than the alignment that the backend is actually capable of
producing (ABIAlign).

This would be OK (if odd) assuming the backend dealt with it prooperly,
unfortunately it doesn't and trying to pass types with "byval align 16" can
cause it to set fp incorrectly and trash the stack during the prologue. I'll be
fixing that in a separate patch, but Clang should still be emitting IR that's
as close to its intent as possible.

rdar://20059039

llvm-svn: 231706
2015-03-09 21:40:42 +00:00
Tim Northover bc784d1caa ARM: Simplify PCS handling.
The backend should now be able to handle all AAPCS rules based on argument
type, which means Clang no longer has to duplicate the register-counting logic
and the CodeGen can be significantly simplified.

llvm-svn: 230349
2015-02-24 17:22:40 +00:00
Tim Northover b047bfae32 AArch64: simplify PCS mapping.
Now that LLVM can count the registers needed to implement AAPCS rules, we don't
need to duplicate that logic here. This means we can drop the explicit padding
and also use more natural types in many cases (e.g. "struct { float arr[3]; }"
used to end up as "[2 x double]" to avoid holes on the stack.

The one wrinkle is that AAPCS va_arg was also using the register counting
machinery. But the local replacement isn't too bad.

llvm-svn: 222904
2014-11-27 21:02:49 +00:00
Eric Christopher 8be702dbaa This test also requires an aarch64 target.
llvm-svn: 222268
2014-11-18 22:36:11 +00:00
Tim Northover 5a1558ec31 ARM ABI: simplify decisions on whether args can be expanded.
Homogeneous aggregates on AAPCS_VFP ARM need to be passed *without* being
flattened (e.g. [2 x float] rather than "float, float") for various weird ABI
reasons. However, this isn't the case for anything else; further, we know at
the ABIArgInfo::getDirect callsites whether this flattening is allowed.

So, we can get more unified ARM code, with a simpler Clang, by just using that
knowledge directly.

llvm-svn: 221559
2014-11-07 22:30:50 +00:00
Oliver Stannard e022851f3b [ARM] Fix AAPCS regression caused by r211898
r211898 introduced a regression where a large struct, which would
normally be passed ByVal, was causing padding to be inserted to
prevent the backend from using some GPRs, in order to follow the
AAPCS. However, the type of the argument was not being set correctly,
so the backend cannot align 8-byte aligned struct types on the stack.

The fix is to not insert the padding arguments when the argument is
being passed ByVal.

llvm-svn: 213359
2014-07-18 09:09:31 +00:00
Oliver Stannard 3f32b9be7f [ARM] Fix AAPCS non-compliance caused by very large structs
This is a fix to the code in clang which inserts padding arguments to
ensure that the ARM backend can emit AAPCS-VFP compliant code. This code
needs to track the number of registers which have been allocated in order
to do this. When passing a very large struct (>64 bytes) by value, clang
emits IR which takes a pointer to the struct, but the backend converts this
back to passing the struct in registers and on the stack. The bug was that
this was being considered by clang to only use one register, meaning that
there were situations in which padding arguments were incorrectly emitted
by clang.

llvm-svn: 211898
2014-06-27 13:59:27 +00:00
Oliver Stannard a3afc69b94 ARM: PCS non-compliance when struct is padded to avoid register/stack split, and requires internal padding
When we were padding a struct to avoid splitting it between registers and
the stack, we were throwing away the type which the argument should be coerced
to.

llvm-svn: 209122
2014-05-19 13:10:05 +00:00
James Molloy 6f244b6f78 Reapply r208417 (olista01 'ARM: HFAs must be passed in consecutive registers'). Bots are now pacified.
llvm-svn: 208425
2014-05-09 16:21:39 +00:00
James Molloy 1aa0d5f3b2 Revert r208417 (olista01 'ARM: HFAs must be passed in consecutive registers'). This is a followon commit from r208413 which broke the LLVM bots.
llvm-svn: 208422
2014-05-09 16:17:09 +00:00
Oliver Stannard 19f3b4f2ce ARM: HFAs must be passed in consecutive registers
This is the clang counterpart to 208413, which ensures that Homogeneous
Floating-point Aggregates are passed in consecutive registers on ARM.

llvm-svn: 208417
2014-05-09 15:14:56 +00:00
Oliver Stannard 39d26c98c5 ARM: Fix assertion caused by passing bitfield struct using ABIArgInfo::getExpandWithPadding
In cases where a struct must, according to the AAPCS, not be split between
general purpose and floating point registers, we use
ABIArgInfo::getExpandWithPadding to add the padding arguments. However,
ExpandWithPadding does not work if the struct contains bitfields, so we
instead must use ABIArgInfo::getDirect.

llvm-svn: 208185
2014-05-07 10:39:12 +00:00
James Molloy 75f5f9e629 [ARM64] Allow the disabling of NEON and crypto instructions. Update tests to pass -target-feature +neon.
llvm-svn: 206394
2014-04-16 15:33:48 +00:00
Tim Northover a2ee433c8d ARM64: initial clang support commit.
This adds Clang support for the ARM64 backend. There are definitely
still some rough edges, so please bring up any issues you see with
this patch.

As with the LLVM commit though, we think it'll be more useful for
merging with AArch64 from within the tree.

llvm-svn: 205100
2014-03-29 15:09:45 +00:00
Oliver Stannard 7c3c09e23f ARM: Correct alignment of structs passed as byval pointer
When a struct has bitfields overlapping with other members
(as required by the AAPCS), clang uses a packed struct to
represent this. If such a struct is large enough for clang to
pass it as a byval pointer (>64 bytes), we need to set the
alignment of the argument to match the original type.

llvm-svn: 203660
2014-03-12 14:02:50 +00:00
Oliver Stannard 405bdeddd1 AAPCS: Do not split structs after CPRC allocated on stack
According to the AAPCS, we can split structs between GPRs and the stack,
except for when an argument has already been allocated on the stack. This
can occur when a large number of floating-point arguments fill up the VFP
registers, and are alllocated on the stack before the general-purpose argument
registers are full.

llvm-svn: 201137
2014-02-11 09:25:50 +00:00
Amara Emerson 9dc7878ac5 [ARM] Fix AAPCS-VFP non-compliance when returning HFA from variadic functions.
Arguments and return values must always be marshalled as for the base
AAPCS when the callee is a variadic function.

Patch by Oliver Stannard!

llvm-svn: 200307
2014-01-28 10:56:36 +00:00
Stephen Lin 4362261b00 CHECK-LABEL-ify some code gen tests to improve diagnostic experience when tests fail.
llvm-svn: 188447
2013-08-15 06:47:53 +00:00
Derek Schuff 57b7e8f63f Properly factor Native Client defines to support NaCl as an OS
with x86/ARM architecture

llvm-svn: 165722
2012-10-11 16:55:58 +00:00
Manman Ren 6c30e137d0 ARM: enable struct byval for AAPCS-VFP.
rdar://9877866

llvm-svn: 161790
2012-08-13 21:23:55 +00:00
Tim Northover eb752d43c9 Add "long double" to permitted list of ARM complex homogeneous aggregates.
Under AAPCS, long double is the same as double, which means it should be
allowed as part of a homogeneous aggregate.

llvm-svn: 160586
2012-07-20 22:29:29 +00:00
Jim Grosbach 2987c57924 Tests: check for target availability for target-specific tests.
Lots of tests are using an explicit target triple w/o first checking that the
target is actually available. Add a REQUIRES clause to a bunch of them. This should
hopefully unbreak bots which don't configure w/ all targets enabled.

llvm-svn: 159949
2012-07-09 18:34:21 +00:00
Bob Wilson 1d9269a8d6 Check for homogeneous aggregate return values with ARM's AAPCS-VFP ABI.
llvm-svn: 143530
2011-11-02 04:51:36 +00:00
Bob Wilson e826a2a56b Handle "homogeneous aggregates" as required by the ARM AAPCS-VFP ABI.
A homogeneous aggregate is an aggregate data structure where after flattening
any nesting there are 1 to 4 elements of the same base type that is either a
float, double, or Neon vector.  All Neon vectors of the same size, either 64
or 128 bits, are treated as equivalent for this purpose.  When using the
AAPCS-VFP ABI, check for homogeneous aggregates and pass them as arguments by
expanding them into a sequence of their base types.  This requires extending
the existing support for expanded arguments to handle not only structs, but
also constant arrays and complex types.

llvm-svn: 136767
2011-08-03 05:58:22 +00:00