llvm-project

Commit Graph

Author	SHA1	Message	Date
Weiming Zhao	5930ae6cc2	[Thumbv8] Fix the value of BLXOperandIndex of isV8EligibleForIT Originally, BLX was passed as operand #0 in MachineInstr and as operand #2 in MCInst. But now, it's operand #2 in both cases. This patch also removes unnecessary FileCheck in the test case added by r199127. llvm-svn: 199928	2014-01-23 19:55:33 +00:00
Weiming Zhao	f66be56bf7	Fix PR 18369: [Thumbv8] asserts due to inconsistent CPSR liveness of IT blocks The issue is caused when Post-RA scheduler reorders a bundle instruction (IT block). However, it only flips the CPSR liveness of the bundle instruction, leaves the instructions inside the bundle unchanged, which causes inconstancy and crashes Thumb2SizeReduction.cpp::ReduceMBB(). llvm-svn: 199127	2014-01-13 18:47:54 +00:00
Evan Cheng	903231bc58	Fix a CPSR liveness tracking bug introduced when I converted IT block to bundle. llvm-svn: 146805	2011-12-17 01:25:34 +00:00

Author

SHA1

Message

Date

Weiming Zhao

5930ae6cc2

[Thumbv8] Fix the value of BLXOperandIndex of isV8EligibleForIT

Originally, BLX was passed as operand #0 in MachineInstr and as operand
#2 in MCInst. But now, it's operand #2 in both cases.

This patch also removes unnecessary FileCheck in the test case added by r199127.

llvm-svn: 199928

2014-01-23 19:55:33 +00:00

Weiming Zhao

f66be56bf7

Fix PR 18369: [Thumbv8] asserts due to inconsistent CPSR liveness of IT blocks

The issue is caused when Post-RA scheduler reorders a bundle instruction
(IT block). However, it only flips the CPSR liveness of the bundle instruction,
leaves the instructions inside the bundle unchanged, which causes inconstancy and crashes
Thumb2SizeReduction.cpp::ReduceMBB().

llvm-svn: 199127

2014-01-13 18:47:54 +00:00

Evan Cheng

903231bc58

Fix a CPSR liveness tracking bug introduced when I converted IT block to bundle.

llvm-svn: 146805

2011-12-17 01:25:34 +00:00

3 Commits