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19869 Commits

Author SHA1 Message Date
Craig Topper bac86038ac Remove some of the special classes that worked around an old tablegen limitation of not being able to remove redundant bitconverts from patterns. 
llvm-svn: 145003
 2011-11-19 21:01:54 +00:00
Craig Topper 3af6ae089f Custom lower AVX2 variable shift intrinsics to shl/srl/sra nodes and remove the intrinsic patterns. 
llvm-svn: 144999
 2011-11-19 17:46:46 +00:00
Craig Topper f984efbfce Synthesize SSSE3/AVX 128-bit horizontal integer add/sub instructions from add/sub of appropriate shuffle vectors. 
llvm-svn: 144989
 2011-11-19 09:02:40 +00:00
Craig Topper 81390be00f Collapse X86 PSIGNB/PSIGNW/PSIGND node types. 
llvm-svn: 144988
 2011-11-19 07:33:10 +00:00
Craig Topper de6b73bb4d Extend VPBLENDVB and VPSIGN lowering to work for AVX2. 
llvm-svn: 144987
 2011-11-19 07:07:26 +00:00
Craig Topper 66e2b5a61e Remove unused parameters from the AVX maskmov classes. 
llvm-svn: 144985
 2011-11-19 04:49:22 +00:00
Nadav Rotem 1ec141d0f9 Add AVX2 vpbroadcast support 
llvm-svn: 144967
 2011-11-18 02:49:55 +00:00
Chad Rosier ee93ff736a Guard call to getRegForValue with isTypeLegal check to avoid unnecessary work/dead code. 
llvm-svn: 144959
 2011-11-18 01:17:34 +00:00
Chad Rosier 0eff3e5c21 Add TODO comment. 
llvm-svn: 144920
 2011-11-17 21:46:13 +00:00
Craig Topper f41e1d0246 Fix SSE/AVX integer comparison patterns to understand that all integer vector loads are promoted to i64 vector loads so patterns need a bitconvert. Also slightly simplify the AVX2 variable shift patterns by using the predefined bitconvert pattern fragments. 
llvm-svn: 144896
 2011-11-17 07:49:38 +00:00
Chad Rosier 15b2498e88 Dead code. 
llvm-svn: 144888
 2011-11-17 07:24:49 +00:00
Craig Topper f17b600577 Remove seemingly unnecessary duplicate VROUND definitions. 
llvm-svn: 144885
 2011-11-17 07:04:00 +00:00
Eli Friedman 489c0ff4a4 Add support for custom names for library functions in TargetLibraryInfo. Add a custom name for fwrite and fputs on x86-32 OSX. Make SimplifyLibCalls honor the custom 
names for fwrite and fputs.

Fixes <rdar://problem/9815881>.

llvm-svn: 144876
 2011-11-17 01:27:36 +00:00
Chad Rosier ce619ddfc5 Don't unconditionally set the kill flag. 
rdar://10456186

llvm-svn: 144872
 2011-11-17 01:16:53 +00:00
Eli Friedman 20439a42b0 Turn on vzeroupper insertion on call boundaries for AVX; it works as far as I know, and I'd like to see wider testing. 
llvm-svn: 144867
 2011-11-17 00:21:52 +00:00
Jim Grosbach d3f02cbce9 Generalize the fixup info for ARM mode. 
We don't (yet) have the granularity in the fixups to be specific about which
bitranges are affected. That's a future cleanup, but we're not there yet.

llvm-svn: 144852
 2011-11-16 22:48:37 +00:00
Akira Hatanaka b31abde0f3 Lower 64-bit constant pool node. 
llvm-svn: 144849
 2011-11-16 22:44:38 +00:00
Akira Hatanaka eb42071721 Lower 64-bit block address. 
llvm-svn: 144847
 2011-11-16 22:42:10 +00:00
Jim Grosbach 7ccdb7c0ae Fix encoding of NOP used for padding in ARM mode .align. 
llvm-svn: 144842
 2011-11-16 22:40:25 +00:00
Akira Hatanaka 7b8547c4d0 Add patterns for 64-bit tglobaladdr, tblockaddress, tjumptable and tconstpool 
nodes.

llvm-svn: 144841
 2011-11-16 22:39:56 +00:00
Akira Hatanaka 6d617ceca2 64-bit jump register instruction. 
llvm-svn: 144840
 2011-11-16 22:36:01 +00:00
Evan Cheng 011538dc79 Another missing X86ISD::MOVLPD pattern. rdar://10450317 
llvm-svn: 144839
 2011-11-16 22:24:44 +00:00
Jim Grosbach bfe5c5c968 ARM assembly parsing for shifted register operands for MOV instruction. 
llvm-svn: 144837
 2011-11-16 21:50:05 +00:00
Jim Grosbach 01e0439240 Clean up debug printing of ARM shifted operands. 
llvm-svn: 144836
 2011-11-16 21:46:50 +00:00
Jim Grosbach 3127ab6d8f ARM assmebly two operand forms for LSR, ASR, LSL, ROR register. 
llvm-svn: 144814
 2011-11-16 19:12:24 +00:00
Jim Grosbach 1a2f9ee3c8 ARM assembly parsing for RRX mnemonic. 
rdar://9704684

llvm-svn: 144812
 2011-11-16 19:05:59 +00:00
Pete Cooper 48784ed5b7 Added missing comment about new custom lowering of DEC64 
llvm-svn: 144811
 2011-11-16 19:03:23 +00:00
Chad Rosier 80979b6ea6 Check to make sure we can select the instruction before trying to put the 
operands into a register.  Otherwise, we may materialize dead code.

llvm-svn: 144805
 2011-11-16 18:39:44 +00:00
Jim Grosbach abcac56869 ARM mode aliases for bitwise instructions w/ register operands. 
rdar://9704684

llvm-svn: 144803
 2011-11-16 18:31:45 +00:00
Bob Wilson 0ca7ce389c Fix tablegen warning: hasSideEffects is inferred for eh_sjlj_dispatchsetup. 
llvm-svn: 144798
 2011-11-16 17:09:59 +00:00
NAKAMURA Takumi b345060a85 lib/Target/ARM/CMakeLists.txt: Disable optimization in ARMISelLowering.cpp also on MSC15(aka VS9). Seems miscompiled. 
llvm-svn: 144794
 2011-11-16 09:18:28 +00:00
Evan Cheng ecb2908bf9 Sink codegen optimization level into MCCodeGenInfo along side relocation model 
and code model. This eliminates the need to pass OptLevel flag all over the
place and makes it possible for any codegen pass to use this information.

llvm-svn: 144788
 2011-11-16 08:38:26 +00:00
Craig Topper 3ed7d9ee5a Fix the execution domain on a bunch of SSE/AVX instructions. 
llvm-svn: 144784
 2011-11-16 07:30:46 +00:00
Bob Wilson f6d1728d8f Fix ARM SjLj-EH dispatch setup code. <rdar://problem/10444602> 
The EmitBasePointerRecalculation function has 2 problems, one minor and one
fatal.  The minor problem is that it inserts the code at the setjmp
instead of in the dispatch block.  The fatal problem is that at the point
where this code runs, we don't know whether there will be a base pointer,
so the entire function is a no-op.  The base pointer recalculation needs to
be handled as it was before, by inserting a pseudo instruction that gets
expanded late.

Most of the support for the old approach is still here, but it no longer
has any connection to the eh_sjlj_dispatchsetup intrinsic.  Clean up the
parts related to the intrinsic and just generate the pseudo instruction
directly.

llvm-svn: 144781
 2011-11-16 07:11:57 +00:00
Craig Topper 07d8b5e2c9 Remove code to enable execution dependency fix pass on VR256. VR128 is sufficient after r144636. 
llvm-svn: 144777
 2011-11-16 05:02:04 +00:00
Chad Rosier af13d767a2 Add FIXME comment. 
llvm-svn: 144743
 2011-11-16 00:32:20 +00:00
Jakob Stoklund Olesen 653183fd5c Enable -widen-vmovs by default. 
This will widen 32-bit register vmov instructions to 64-bit when
possible.  The 64-bit vmovd instructions can then be translated to NEON
vorr instructions by the execution dependency fix pass.

The copies are only widened if they are marked as clobbering the whole
D-register.

llvm-svn: 144734
 2011-11-15 23:53:18 +00:00
Jim Grosbach e891fe8d6c ARM assembly parsing for register range syntax for VLD/VST register lists. 
For example,
vld1.f64 {d2-d5}, [r2,:128]!

Should be equivalent to:
vld1.f64 {d2,d3,d4,d5}, [r2,:128]!

It's not documented syntax in the ARM ARM, but it is consistent with what's
accepted for VLDM/VSTM and is unambiguous in meaning, so it's a good thing to
support.

rdar://10451128

llvm-svn: 144727
 2011-11-15 23:19:15 +00:00
Jim Grosbach 003cea6011 ARM assembly parsing for data type suffices on NEON VMOV aliases. 
llvm-svn: 144722
 2011-11-15 22:54:42 +00:00
Nadav Rotem 37010002f2 AVX: Add support for vbroadcast from BUILD_VECTOR and refactor some of the vbroadcast code. 
llvm-svn: 144720
 2011-11-15 22:50:37 +00:00
Jim Grosbach 75fb4abcdc ARM assembly parsing two operand forms for shift instructions. 
llvm-svn: 144713
 2011-11-15 22:27:54 +00:00
Jim Grosbach a01033709f ARM VFP assembly parsing for VADD and VSUB two-operand forms. 
llvm-svn: 144710
 2011-11-15 22:15:10 +00:00
Jim Grosbach 8279c1828f ARM accept an immediate offset in memory operands w/o the '#'. 
llvm-svn: 144709
 2011-11-15 22:14:41 +00:00
Pete Cooper 7c7ba1baa1 Added custom lowering for load->dec->store sequence in x86 when the EFLAGS registers is used 
by later instructions.

Only done for DEC64m right now.

Fixes <rdar://problem/6172640>

llvm-svn: 144705
 2011-11-15 21:57:53 +00:00
Jim Grosbach 8d579230c6 ARM enclosing curly braces optional on one-register VLD/VST instruction lists. 
'vld1.f32 d4, [r7]' should be parsed as equivalent to 'vld1.f32 {d4}, [r7]'

rdar://10450488.

llvm-svn: 144701
 2011-11-15 21:45:55 +00:00
Jim Grosbach 84f0ba5747 ARM size suffix on VFP single-precision 'vmov' is optional. 
rdar://10435114

llvm-svn: 144698
 2011-11-15 21:18:35 +00:00
Jim Grosbach a92a5d8548 Fix typo. 
llvm-svn: 144695
 2011-11-15 21:01:30 +00:00
Jim Grosbach 131b45e632 ARM alternate size suffices for VTRN instructions. 
rdar://10435076

llvm-svn: 144694
 2011-11-15 20:49:46 +00:00
Owen Anderson 05060f0748 Fix a misplaced paren bug. 
llvm-svn: 144692
 2011-11-15 20:30:41 +00:00
Jim Grosbach 5803f6d5a2 ARM assembly parsing for optional datatype suffix on VFP VMOV GPR<->VFP insns. 
Yet more of rdar://10435076.

llvm-svn: 144691
 2011-11-15 20:29:42 +00:00