7 Commits

Author	SHA1	Message	Date
Che-Liang Chiou	59515dc703	Add 64-bit addressing to PTX backend ... - Add '64bit' sub-target option. - Select 32-bit/64-bit loads/stores based on '64bit' option. - Fix function parameter order. Patch by Justin Holewinski llvm-svn: 126837	2011-03-02 07:36:48 +00:00
Che-Liang Chiou	65b1476031	Extend initial support for primitive types in PTX backend ... - Allow i16, i32, i64, float, and double types, using the native .u16, .u32, .u64, .f32, and .f64 PTX types. - Allow loading/storing of all primitive types. - Allow primitive types to be passed as parameters. - Allow selection of PTX Version and Shader Model as sub-target attributes. - Merge integer/floating-point test cases for load/store. - Use .u32 instead of .s32 to conform to output from NVidia nvcc compiler. Patch by Justin Holewinski llvm-svn: 126824	2011-03-02 03:20:28 +00:00
Che-Liang Chiou	84fde9ef2b	ptx: add passing parameter to kernel functions ... llvm-svn: 125279	2011-02-10 12:01:24 +00:00
Che-Liang Chiou	5451fc9195	ptx: remove reg-reg addressing mode and st.const ... llvm-svn: 122653	2011-01-01 11:58:58 +00:00
Che-Liang Chiou	aaedf8be1c	ptx: add ld instruction and test ... llvm-svn: 122398	2010-12-22 10:38:51 +00:00
Che-Liang Chiou	d816204056	ptx: add ld instruction ... support register and register-immediate addressing mode todo: immediate and register-register addressing mode llvm-svn: 120407	2010-11-30 07:34:44 +00:00
Eric Christopher	dbb199d89b	Add the exit instruction to the PTX target. ... Patch by Che-Liang Chiou <clchiou@gmail.com>! llvm-svn: 114294	2010-09-18 18:52:28 +00:00