Commit Graph

2091 Commits

Author SHA1 Message Date
Akira Hatanaka c13ed945aa Add lit.local.cfg to run the tests in test/MC/Disassembler/Mips.
llvm-svn: 157725
2012-05-31 00:49:56 +00:00
Benjamin Kramer ef479ea854 Add intrinsics, code gen, assembler and disassembler support for the SSE4a extrq and insertq instructions.
This required light surgery on the assembler and disassembler
because the instructions use an uncommon encoding. They are
the only two instructions in x86 that use register operands
and two immediates.

llvm-svn: 157634
2012-05-29 19:05:25 +00:00
Jim Grosbach 4b63d2ae1d Refactor data-in-code annotations.
Use a dedicated MachO load command to annotate data-in-code regions.
This is the same format the linker produces for final executable images,
allowing consistency of representation and use of introspection tools
for both object and executable files.

Data-in-code regions are annotated via ".data_region"/".end_data_region"
directive pairs, with an optional region type.

data_region_directive := ".data_region" { region_type }
region_type := "jt8" | "jt16" | "jt32" | "jta32"
end_data_region_directive := ".end_data_region"

The previous handling of ARM-style "$d.*" labels was broken and has
been removed. Specifically, it didn't handle ARM vs. Thumb mode when
marking the end of the section.

rdar://11459456

llvm-svn: 157062
2012-05-18 19:12:01 +00:00
Kevin Enderby badd100c26 Fixed a bug in llvm-objdump when disassembling using -macho option for a binary
containing no symbols.  Fixed the crash and fixed it not disassembling anything.

llvm-svn: 157031
2012-05-18 00:13:56 +00:00
Kevin Enderby f1b225d0e0 Fix the encoding of the armv7m (MClass) for MSR APSR writes which was missing
the 0b10 mask encoding bits.  Make MSR APSR writes without a _<bits> qualifier
an alias for MSR APSR_nzcvq even though ARM as deprecated it use.  Also add
support for suffixes (_nzcvq, _g, _nzcvqg) for APSR versions.  Some FIXMEs in
the code for better error checking when versions shouldn't be used.
rdar://11457025

llvm-svn: 157019
2012-05-17 22:18:01 +00:00
Kevin Enderby a414bcc0e3 Add a test case for r156840, a fix to llvm-objdump when disassembling using
-macho to disassemble the last symbol to the end of the section.

llvm-svn: 156850
2012-05-15 20:20:50 +00:00
Rafael Espindola 47b7dac220 Add support for the .rept directive. Patch by Vladmir Sorokin. I added support
for nesting.

llvm-svn: 156714
2012-05-12 16:31:10 +00:00
Benjamin Kramer 6bee7f750d ELF: Add support for the asm .version directive.
llvm-svn: 156712
2012-05-12 14:30:47 +00:00
Benjamin Kramer 95d31bcba5 AsmParser: Add support for the .purgem directive.
Based on a patch by Team PaX.

llvm-svn: 156709
2012-05-12 11:21:46 +00:00
Benjamin Kramer 66b8d4d28f AsmParser: ignore the .extern directive.
llvm-svn: 156707
2012-05-12 11:18:59 +00:00
Benjamin Kramer e297b9f506 AsmParser: Add support for .ifc and .ifnc directives.
Based on a patch from PaX Team.

llvm-svn: 156706
2012-05-12 11:18:51 +00:00
Benjamin Kramer 62c18b0881 AsmParser: Add support for .ifb and .ifnb directives.
Based on a patch from PaX Team.

llvm-svn: 156705
2012-05-12 11:18:42 +00:00
Akira Hatanaka 8f3573034b Make the following changes in MipsAsmPrinter.cpp:
- Remove code which lowers pseudo SETGP01.
- Fix LowerSETGP01. The first two of the three instructions that are emitted to
  initialize the global pointer register now use register $2.
- Stop emitting .cpload directive.

llvm-svn: 156689
2012-05-12 00:48:43 +00:00
Akira Hatanaka d918f77ba3 Insert instructions to the entry basic block which initializes the global
pointer register. 


This is the first of the series of patches which clean up the way global pointer
register is used. The patches will make the following improvements:

- Make $gp an allocatable temporary register rather than reserving it.
- Use a virtual register as the global pointer register and let the register
  allocator decide which register to assign to it or whether spill/reloads are
  needed.
- Make sure $gp is valid at the entry of a called function, which is necessary
  for functions using lazy binding.
- Remove the need for emitting .cprestore and .cpload directives.

llvm-svn: 156671
2012-05-12 00:17:17 +00:00
Silviu Baranga ddc67a7655 Added the missing bit definition for the 4th bit of the STR (post reg) instruction. It is now set to 0. The patch also sets the unpredictable mask for SEL and SXTB-type instructions.
llvm-svn: 156609
2012-05-11 09:28:27 +00:00
Silviu Baranga 5a719f9b9a Fixed the LLVM ARM v7 assembler and instruction printer for 8-bit immediate offset addressing. The assembler and instruction printer were not properly handeling the #-0 immediate.
llvm-svn: 156608
2012-05-11 09:10:54 +00:00
Kevin Enderby 914223010c Fix issues with the ARM bl and blx thumb instructions and the J1 and J2 bits
for the assembler and disassembler.  Which were not being set/read correctly
for offsets greater than 22 bits in some cases.

Changes to lib/Target/ARM/ARMAsmBackend.cpp from Gideon Myles!

llvm-svn: 156118
2012-05-03 22:41:56 +00:00
Silviu Baranga 9560af848c Fixed disassembler for vstm/vldm ARM VFP instructions.
llvm-svn: 156077
2012-05-03 16:38:40 +00:00
Jim Grosbach 28b0b7279e ARM: Add missing two-operand VBIC aliases.
llvm-svn: 156019
2012-05-02 21:11:56 +00:00
Richard Barton 0fc56890ba Disallow YIELD and other allocated nop hints in pre-ARMv6 architectures.
llvm-svn: 155983
2012-05-02 09:43:18 +00:00
Jim Grosbach 1d20efb837 ARM: Add a few missing add->sub aliases w/ 'w' suffix.
Aliases for adding a negative immediate when using an explicit 'w'
suffix. E.g.,
        adds.w r2, #-16
        adds.w r2, r2, #-16
        addw r2, #-16
        addw r2, #-16
        addw r2, r2, #-16

rdar://11330769

llvm-svn: 155946
2012-05-01 21:17:34 +00:00
Jim Grosbach 70bed4faaf ARM: allow vanilla expressions for movw/movt.
Expressions for movw/movt don't always have an :upper16: or :lower16:
on them and that's ok. When they don't, it's just a plain [0-65536]
immediate result, effectively the same as a :lower16: variant kind.

rdar://10550147

llvm-svn: 155941
2012-05-01 20:43:21 +00:00
Jim Grosbach 758e0cc94a MC: Unknown assembler directives are now hard errors.
Previously, an unsupported/unknown assembler directive issued a warning.
That's generally unsafe, and inconsistent with the behaviour of pretty
much every system assembler. Now that the MC assemblers are mature
enough to be the default on multiple targets, it's reasonable to
issue errors for these.

For target or platform directives that need to stay warnings, we
should add explicit handlers for them in, e.g., ELFAsmParser.cpp,
DarwinAsmParser.cpp, et. al., and issue the warning there.

rdar://9246275

llvm-svn: 155926
2012-05-01 18:38:27 +00:00
Jim Grosbach c6f32b3295 ARM: Thumb add(sp plus register) asm constraints.
Make sure when parsing the Thumb1 sp+register ADD instruction that
the source and destination operands match. In thumb2, just use the
wide encoding if they don't. In Thumb1, issue a diagnostic.

rdar://11219154

llvm-svn: 155748
2012-04-27 23:51:36 +00:00
Richard Barton 82f95ea2ad Fix ARM assembly parsing for upper case condition codes on IT instructions.
llvm-svn: 155720
2012-04-27 17:34:01 +00:00
Benjamin Kramer 6cff5ad411 Missed some register numbers.
llvm-svn: 155706
2012-04-27 12:21:46 +00:00
Benjamin Kramer b1a17c425a Update edis test for r155704.
llvm-svn: 155705
2012-04-27 12:14:03 +00:00
Evan Cheng 8a8e9d1b63 Specify cpu to unbreak tests.
llvm-svn: 155604
2012-04-26 01:38:10 +00:00
Jim Grosbach 5117ef7453 ARM: improved assembler diagnostics for missing CPU features.
When an instruction match is found, but the subtarget features it
requires are not available (missing floating point unit, or thumb vs arm
mode, for example), issue a diagnostic that identifies what the feature
mismatch is.

rdar://11257547

llvm-svn: 155499
2012-04-24 22:40:08 +00:00
Kevin Enderby 70be447e5c Add missing test cases for ARM VLD3 (single 3-element structure to all lanes)
instructions.

llvm-svn: 155453
2012-04-24 17:45:56 +00:00
Kevin Enderby c8d223e41e Add missing test cases for ARM VLD4 (single 4-element structure to all lanes)
instructions.

llvm-svn: 155444
2012-04-24 15:55:00 +00:00
Jim Grosbach f6371b5238 ARM: Add testcases for two-operand variants of VSRA/VRSRA/VSRI.
llvm-svn: 155391
2012-04-23 21:00:47 +00:00
Jim Grosbach 76cdd136bf Add ARM mode tests for the NEON vector shift-accumulate tests.
llvm-svn: 155390
2012-04-23 21:00:44 +00:00
Jim Grosbach 5c7e9e5e1b Tidy up. Reformat for ease of reading.
llvm-svn: 155389
2012-04-23 21:00:42 +00:00
Jim Grosbach 2937df45a8 ARM: Update NEON assembly two-operand aliases.
Use the new TwoOperandAliasConstraint to handle lots of the two-operand aliases
for NEON instructions. There's still more to go, but this is a good chunk of
them.

llvm-svn: 155210
2012-04-20 18:12:54 +00:00
Jim Grosbach 9cc324d31a ARM some VFP tblgen'erated two-operand aliases.
llvm-svn: 155178
2012-04-20 00:15:00 +00:00
Jim Grosbach 86afe67e10 Tidy up. Formatting.
llvm-svn: 155177
2012-04-20 00:14:57 +00:00
Silviu Baranga ca45af9a75 Added support for disassembling unpredictable swp/swpb ARM instructions.
llvm-svn: 155004
2012-04-18 14:18:57 +00:00
Silviu Baranga d5c6a63a50 Fix the bahavior of the disassembler when decoding unpredictable mrs instructions on ARM. Now the diasassembler emmits warnings instead of errors.
llvm-svn: 155002
2012-04-18 14:09:07 +00:00
Silviu Baranga 41f1fcd80e Added support for unpredictable mcrr/mcrr2/mrrc/mrrc2 ARM instruction in the disassembler. Since the upredicability conditions are complex, C++ code was added to handle them.
llvm-svn: 155001
2012-04-18 13:12:50 +00:00
Silviu Baranga a2944116dc Fixed decoding for the ARM cdp2 instruction. The restriction on the coprocessor number was removed for this instruction.
llvm-svn: 155000
2012-04-18 13:02:55 +00:00
Silviu Baranga 9da1918c84 Add suport for unpredicatble cases of the cmp, tst, teq and cmnz ARM instructions in the disassembler.
llvm-svn: 154999
2012-04-18 12:48:43 +00:00
Akira Hatanaka 71928e681b Add disassembler to MIPS.
Patch by Vladimir Medic. 

llvm-svn: 154935
2012-04-17 18:03:21 +00:00
Kevin Enderby 29ae538647 Fix ARM disassembly of VLD2 (single 2-element structure to all lanes)
instructions with writebacks. And add test a case for all opcodes handed by
DecodeVLD2DupInstruction() in ARMDisassembler.cpp .

llvm-svn: 154884
2012-04-17 00:49:27 +00:00
Jim Grosbach 2bf5f73977 ARM two-operand forms for vhadd and vhsub instructions.
rdar://11252521

llvm-svn: 154875
2012-04-16 23:00:25 +00:00
Jim Grosbach 1e1d68f1b9 MC assembly parser handling for trailing comma in macro instantiation.
A trailing comma means no argument at all (i.e., as if the comma were not
present), not an empty argument to the invokee.

rdar://11252521

llvm-svn: 154863
2012-04-16 21:18:49 +00:00
Akira Hatanaka 4c0db08880 This patch fixes 3 problems:
1. CHECKNEXT was used instead of CHECK-NEXT which caused the line to be
   ignored which in turn hid the next 2 problems:
2. ('sh_offset', 0x{{{[0-9,a-f]+}}) had one too many leading curly braces and
   failed to do it's job of accepting all hex digits and:
3. The check for the hex values for the code instructions didn't account for
   blank separators.

Patch by Jack Carter. 

llvm-svn: 154842
2012-04-16 18:20:26 +00:00
Jim Grosbach 6068d0014a ARM assembly two-operand forms for VRSHL.
rdar://11252521

llvm-svn: 154840
2012-04-16 18:03:16 +00:00
Jim Grosbach 9bfe7054af Tidy up. Test formatting.
llvm-svn: 154839
2012-04-16 18:03:14 +00:00
Akira Hatanaka 3e9d81f47c Do not add offset in applyFixup. This has already been accounted for in Value.
llvm-svn: 154838
2012-04-16 18:00:19 +00:00