Commit Graph

5697 Commits

Author SHA1 Message Date
Evan Cheng bab5988017 Livestacks really does preserve everything.
llvm-svn: 56476
2008-09-22 22:26:15 +00:00
Evan Cheng 962c2cf17a Instead of setPreservesAll, just mark them preseving machine loop info and machine dominators.
llvm-svn: 56475
2008-09-22 22:21:38 +00:00
Owen Anderson 97364655dc Significant improvements to the logic for merging live intervals. This code can't
just use LI::MergeValueAsValue, as its behavior in the presence of overlapping ranges
isn't what StrongPHIElimination wants.

llvm-svn: 56472
2008-09-22 21:58:58 +00:00
Dale Johannesen 7a74e71489 Make log, log2, log10, exp, exp2 use Expand by
default.

llvm-svn: 56471
2008-09-22 21:57:32 +00:00
Evan Cheng 168f8f3916 Mark several codegen passes as preserving all analysis.
llvm-svn: 56469
2008-09-22 20:58:04 +00:00
Dale Johannesen f1acc4d610 More refactoring. Yawn.
llvm-svn: 56468
2008-09-22 20:51:30 +00:00
Dale Johannesen 7beddb8680 Refactor FP intrinisic setup. Per review feedback.
llvm-svn: 56456
2008-09-22 19:51:58 +00:00
Evan Cheng 13beeeb128 Per review feedback: Only perform
(srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), c))
etc. when both "trunc" and "and" have single uses.

llvm-svn: 56452
2008-09-22 18:19:24 +00:00
Oscar Fuentes a229b3c9a7 Initial support for the CMake build system.
llvm-svn: 56419
2008-09-22 01:08:49 +00:00
Bill Wendling 91ef8fcd29 Add helper function to get a 32-bit floating point constant. No functionality change.
llvm-svn: 56418
2008-09-22 00:44:35 +00:00
Dan Gohman ae9d9f4d3f Factor out code into HandleVirtRegDef, for consistency with
Handle{Virt,Phys}Reg{Def,Use}. Remove a redundant check
for register zero, and redundant checks for isPhysicalRegister.

llvm-svn: 56412
2008-09-21 21:11:41 +00:00
Owen Anderson df8f1cb995 Fetch the starting index of the block when assigning intervals. This gets live-in indices
correct in the presence of things like EH labels.

llvm-svn: 56410
2008-09-21 20:43:24 +00:00
Chris Lattner 43f5449c48 don't print GlobalAddressSDNode's with an offset of zero as "foo0".
llvm-svn: 56399
2008-09-21 18:38:31 +00:00
Dale Johannesen 9af7b3daec Teach coalescer about earlyclobber bits.
Check bits for preferred register.

llvm-svn: 56384
2008-09-20 02:03:04 +00:00
Evan Cheng c042000649 Fix PR2808. When regalloc runs out of register, it spill a physical register around the live interval being allocated. Do not continue to try to spill another register, just grab the physical register and move on.
llvm-svn: 56381
2008-09-20 01:28:05 +00:00
Evan Cheng 29e4c9192d Continue after removing the current MI.
llvm-svn: 56372
2008-09-19 22:49:39 +00:00
Dan Gohman 9801ba451a Refactor X86SelectConstAddr, folding it into X86SelectAddress. This
results in better code for globals. Also, unbreak the local CSE for
GlobalValue stub loads.

llvm-svn: 56371
2008-09-19 22:16:54 +00:00
Dale Johannesen 436aae627d Make earlyclobber stuff work when virtual regs
have previously been assigned conflicting physreg.

llvm-svn: 56364
2008-09-19 18:52:31 +00:00
Evan Cheng 4c0197043c Re-materalized definition instructions may be dead. Whack them.
llvm-svn: 56352
2008-09-19 17:38:47 +00:00
Dale Johannesen e519bd4183 Remove AsmThatEarlyClobber etc. from LiveIntervalAnalysis
and redo as linked list walk.  Logic moved into RA.
Per review feedback.

llvm-svn: 56326
2008-09-19 01:02:35 +00:00
Evan Cheng 3d9416cf24 Somehow RegAllocLinearScan is keeping two pointers to MachineRegisterInfo.
llvm-svn: 56314
2008-09-18 22:38:47 +00:00
Dan Gohman f3d647e00b Don't consider instructions with implicit physical register
defs to be necessarily live.

llvm-svn: 56310
2008-09-18 18:22:32 +00:00
Dan Gohman 95be7d7b85 Add a new "fast" scheduler. This is currently basically just a
copy of the BURRList scheduler, but with several parts ripped
out, such as backtracking, online topological sort maintenance
(needed by backtracking), the priority queue, and Sethi-Ullman
number computation and maintenance (needed by the priority
queue). As a result of all this, it generates somewhat lower
quality code, but that's its tradeoff for running about 30%
faster than list-burr in -fast mode in many cases.

This is somewhat experimental. Moving forward, major pieces of
this can be refactored with pieces in common with
ScheduleDAGRRList.cpp.

llvm-svn: 56307
2008-09-18 16:26:26 +00:00
Dale Johannesen f8610ebebc Add a bit to mark operands of asm's that conflict
with an earlyclobber operand elsewhere.  Propagate
this bit and the earlyclobber bit through SDISel.
Change linear-scan RA not to allocate regs in a way 
that conflicts with an earlyclobber.  See also comments.

llvm-svn: 56290
2008-09-17 21:13:11 +00:00
Evan Cheng f3fcd7a464 Unallocatable registers do not have live intervals.
llvm-svn: 56287
2008-09-17 18:36:25 +00:00
Dan Gohman 6ab52a8018 Don't worry about clobbering physical register defs that aren't used.
llvm-svn: 56281
2008-09-17 15:25:49 +00:00
Dan Gohman c24cd015a7 Add a new MachineInstr-level DCE pass. It is very simple, and is intended to
be used with fast-isel.

llvm-svn: 56268
2008-09-17 00:43:24 +00:00
Evan Cheng a904f466e8 When converting a CopyFromReg to a copy instruction, use the register class of its uses to determine the right destination register class of the copy. This is important for targets where a physical register may belong to multiple register classes.
llvm-svn: 56258
2008-09-16 23:12:11 +00:00
Dan Gohman 64d6c6fe30 Change SelectionDAG::getConstantPool to always set the alignment of the
ConstantPoolSDNode, using the target's preferred alignment for the
constant type.

In LegalizeDAG, when performing loads from the constant pool, the
ConstantPoolSDNode's alignment is used in the calls to getLoad and
getExtLoad.

This change prevents SelectionDAG::getLoad/getExtLoad from incorrectly
choosing the ABI alignment for constant pool loads when Alignment == 0.
The incorrect alignment is only a performance issue when ABI alignment
does not equal preferred alignment (i.e., on x86 it was generating
MOVUPS instead of MOVAPS for v4f32 constant loads when the default ABI
alignment for 128bit vectors is forced to 1 byte.)

Patch by Paul Redmond!

llvm-svn: 56253
2008-09-16 22:05:41 +00:00
Bill Wendling 24c79f28b1 Reverting r56249. On further investigation, this functionality isn't needed.
Apologies for the thrashing.

llvm-svn: 56251
2008-09-16 21:48:12 +00:00
Dan Gohman ab26f20d44 Include the alignment value when displaying ConstantPoolSDNodes.
llvm-svn: 56250
2008-09-16 21:18:22 +00:00
Bill Wendling 8bc392fb1d - Change "ExternalSymbolSDNode" to "SymbolSDNode".
- Add linkage to SymbolSDNode (default to external).
- Change ISD::ExternalSymbol to ISD::Symbol.
- Change ISD::TargetExternalSymbol to ISD::TargetSymbol

These changes pave the way to allowing SymbolSDNodes with non-external linkage.

llvm-svn: 56249
2008-09-16 21:12:30 +00:00
Dan Gohman 5cf6120a7c Fix these comments to reflect current reality. Surprisingly,
MachineConstantPool::getConstantPoolIndex actually expects
a log2-encoded alignment.

llvm-svn: 56248
2008-09-16 20:45:53 +00:00
Dan Gohman 050d7835c6 Don't take the time to CheckDAGForTailCallsAndFixThem when tail calls
are not enabled. Instead just omit the tail call flag when calls are
created.

llvm-svn: 56235
2008-09-16 01:42:28 +00:00
Owen Anderson 82ab1e7280 Live intervals for live-in registers should begin at the beginning of a basic block, not at the first
instruction.  Also, their valno's should have an unknown def.  This has no effect currently, but was
causing issues when StrongPHIElimination was enabled.

llvm-svn: 56231
2008-09-15 22:00:38 +00:00
Dan Gohman 3c7b9ba547 Re-enable SelectionDAG CSE for calls. It matters in the case of
libcalls, as in this testcase on ARM.

llvm-svn: 56226
2008-09-15 19:46:03 +00:00
Evan Cheng 02acc35abd Correctly update kill infos after extending a live range and merge 2 val#'s; fix 56165 - do not mark val# copy field if the copy does not define the val#.
llvm-svn: 56199
2008-09-15 06:28:41 +00:00
Dale Johannesen c0d712d9ed adjust last patch per review feedback
llvm-svn: 56194
2008-09-14 01:44:36 +00:00
Dan Gohman 38453eebdc Remove isImm(), isReg(), and friends, in favor of
isImmediate(), isRegister(), and friends, to avoid confusion
about having two different names with the same meaning. I'm
not attached to the longer names, and would be ok with
changing to the shorter names if others prefer it.

llvm-svn: 56189
2008-09-13 17:58:21 +00:00
Dan Gohman d3fe174c53 Define CallSDNode, an SDNode subclass for use with ISD::CALL.
Currently it just holds the calling convention and flags
for isVarArgs and isTailCall.

And it has several utility methods, which eliminate magic
5+2*i and similar index computations in several places.

CallSDNodes are not CSE'd. Teach UpdateNodeOperands to handle
nodes that are not CSE'd gracefully.

llvm-svn: 56183
2008-09-13 01:54:27 +00:00
Evan Cheng 3c12fc4342 On some targets, non-move instructions can become move instructions because of coalescing. e.g.
vr2 = OR vr0, vr1
=>
vr2 = OR vr1, vr1   // after coalescing vr0 with vr1

Update the value# of the destination register with the copy instruction if that happens.

llvm-svn: 56165
2008-09-12 18:13:14 +00:00
Dan Gohman ec270fb640 Change ConstantSDNode and ConstantFPSDNode to use ConstantInt* and
ConstantFP* instead of APInt and APFloat directly.

This reduces the amount of time to create ConstantSDNode
and ConstantFPSDNode nodes when ConstantInt* and ConstantFP*
respectively are already available, as is the case in
SelectionDAGBuild.cpp. Also, it reduces the amount of time
to legalize constants into constant pools, and the amount of
time to add ConstantFP operands to MachineInstrs, due to
eliminating ConstantInt::get and ConstantFP::get calls.

It increases the amount of work needed to create new constants
in cases where the client doesn't already have a ConstantInt*
or ConstantFP*, such as legalize expanding 64-bit integer constants
to 32-bit constants. And it adds a layer of indirection for the
accessor methods. But these appear to be outweight by the benefits
in most cases.

It will also make it easier to make ConstantSDNode and
ConstantFPNode more consistent with ConstantInt and ConstantFP.

llvm-svn: 56162
2008-09-12 18:08:03 +00:00
Dale Johannesen 1f3ab86804 Pass "earlyclobber" bit through to machine
representation; coalescer and RA need to know
about it.  No functional change.

llvm-svn: 56161
2008-09-12 17:49:03 +00:00
Dan Gohman effb894453 Rename ConstantSDNode::getValue to getZExtValue, for consistency
with ConstantInt. This led to fixing a bug in TargetLowering.cpp
using getValue instead of getAPIntValue.

llvm-svn: 56159
2008-09-12 16:56:44 +00:00
Dale Johannesen baf6762e26 The sequence for ppcf128 compares was not IEEE
safe in the presence of NaNs.

llvm-svn: 56136
2008-09-12 00:30:56 +00:00
Evan Cheng 5456a37280 Fix PR2748. Avoid coalescing physical register with virtual register which would create illegal extract_subreg. e.g.
vr1024 = extract_subreg vr1025, 1
...
vr1024 = mov8rr AH
If vr1024 is coalesced with AH, the extract_subreg is now illegal since AH does not have a super-reg whose sub-register 1 is AH.

llvm-svn: 56118
2008-09-11 20:07:10 +00:00
Evan Cheng 4c9fbbb511 Fix PR2783 - coalescer bug. Missing a TargetRegisterInfo::isVirtualRegister check.
llvm-svn: 56112
2008-09-11 18:40:32 +00:00
Evan Cheng 783ed9ead1 Fix a 80 column violation.
llvm-svn: 56097
2008-09-11 05:58:06 +00:00
Evan Cheng b401449ceb Propagate subreg index when promoting a load to a copy.
llvm-svn: 56085
2008-09-11 01:02:12 +00:00
Dan Gohman 1dc9b0514f FastISel support for i1 PHI nodes.
llvm-svn: 56069
2008-09-10 21:01:31 +00:00