b352d76480
To get more thorough testing from llc-beta nightly runs, do dynamic stack
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realignment regardless of whether it's strictly necessary.
llvm-svn: 85476
2009-10-29 02:41:21 +00:00
97b9312663
Revert r85346 change to control tail merging by CodeGenOpt::Level.
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I'm going to redo this using the OptimizeForSize function attribute.
llvm-svn: 85426
2009-10-28 20:46:46 +00:00
73789b848d
Add a Thumb BRIND pattern. Change the ARM BRIND assembly to separate the
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opcode and operand with a tab. Check for these instructions in the usual
places.
llvm-svn: 85411
2009-10-28 18:26:41 +00:00
6203c6868f
fconsts and fconstd are obviously re-materializable.
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llvm-svn: 85410
2009-10-28 18:19:56 +00:00
294aea709e
Cleanup now that frame index scavenging via post-pass is working for ARM and Thumb2.
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llvm-svn: 85406
2009-10-28 17:33:28 +00:00
ec6d7c945d
Give ARMISD::EH_SJLJ_LONGJMP and EH_SJLJ_SETJMP names.
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llvm-svn: 85381
2009-10-28 06:55:03 +00:00
f64db3e1d0
X86 palignr intrinsics immediate field is in bits. ISel must transform it into bytes.
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llvm-svn: 85379
2009-10-28 06:30:34 +00:00
a91a563530
Previously, all operands to Constant were themselves constant.
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In the new world order, BlockAddress can have a BasicBlock operand.
This doesn't permute much, because if you have a ConstantExpr (or
anything more specific than Constant) we still know the operand has
to be a Constant.
llvm-svn: 85375
2009-10-28 05:14:34 +00:00
4a609f3cef
Use fconsts and fconstd to materialize small fp constants.
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llvm-svn: 85362
2009-10-28 01:44:26 +00:00
83896a59e1
Add a second ValueType argument to isFPImmLegal.
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llvm-svn: 85361
2009-10-28 01:43:28 +00:00
9c6bc1f563
Update SystemZ to use PSW following the way x86 uses EFLAGS. Besides
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eliminating a use of MVT::Flag, this is needed for an upcoming CodeGen
change.
This unfortunately requires SystemZ to switch to the list-burr
scheduler, in order to handle the physreg defs properly, however
that's what LLVM has available at this time.
llvm-svn: 85357
2009-10-28 00:55:57 +00:00
e4b80c9bee
Add an indirect branch pattern for ARM. Testcase will be coming soon.
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llvm-svn: 85355
2009-10-28 00:37:03 +00:00
d04cb6d0fa
rename indbr -> indirectbr to appease the residents of #llvm.
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llvm-svn: 85351
2009-10-28 00:19:10 +00:00
9693f9d465
Record CodeGen optimization level in the BranchFolding pass so that we can
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use it to control tail merging when there is a tradeoff between performance
and code size. When there is only 1 instruction in the common tail, we have
been merging. That can be good for code size but is a definite loss for
performance. Now we will avoid tail merging in that case when the
optimization level is "Aggressive", i.e., "-O3". Radar 7338114.
Since the IfConversion pass invokes BranchFolding, it too needs to know
the optimization level. Note that I removed the RegisterPass instantiation
for IfConversion because it required a default constructor. If someone
wants to keep that for some reason, we can add a default constructor with
a hard-wired optimization level.
llvm-svn: 85346
2009-10-27 23:49:38 +00:00
2e5198ff09
Add new note.
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llvm-svn: 85341
2009-10-27 23:30:07 +00:00
5607d2cb54
Enable virtual register based frame index scavenging by default for ARM & T2.
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llvm-svn: 85335
2009-10-27 22:52:29 +00:00
fd2730ee8c
Move and clarify note.
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llvm-svn: 85334
2009-10-27 22:48:31 +00:00
c1403a0024
Infrastructure for dynamic stack realignment on ARM. For now, this is off by
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default behind a command line option. This will enable better performance for
vectors on NEON enabled processors.
llvm-svn: 85333
2009-10-27 22:45:39 +00:00
2974f63cb5
Note corrected.
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llvm-svn: 85332
2009-10-27 22:43:24 +00:00
cd4d148040
Modify note.
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llvm-svn: 85331
2009-10-27 22:40:45 +00:00
a205402c16
Add a note.
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llvm-svn: 85329
2009-10-27 22:34:43 +00:00
e8628a0206
cppbackend support for indbr
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llvm-svn: 85312
2009-10-27 21:24:48 +00:00
42c979e8d3
CBE support for indbr.
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llvm-svn: 85311
2009-10-27 21:21:06 +00:00
cde65ec581
Similar to r85280, do not clear the "S" bit for RSBri and RSBrs.
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llvm-svn: 85299
2009-10-27 20:51:49 +00:00
4f36affe5f
Set condition code bits of BL and BLr9 to 0b1110 (ALways) to distinguish between
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BL_pred and BLr9_pred.
llvm-svn: 85297
2009-10-27 20:45:15 +00:00
16993aa30b
Do away with addLegalFPImmediate. Add a target hook isFPImmLegal which returns true if the fp immediate can be natively codegened by target.
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llvm-svn: 85281
2009-10-27 19:56:55 +00:00
b5044ce5a9
Do not clear the "S" bit for RSCri and RSCrs. They inherit from the "sI"
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instruction format that already takes care of setting this.
llvm-svn: 85280
2009-10-27 19:52:03 +00:00
df5dcdaa10
Explicitly specify 0b00, i.e, zero rotation, as the rotate filed (Inst{11-10})
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for the r/rr fragment of the multiclass AI_unary_rrot/AI_bin_rrot.
llvm-svn: 85271
2009-10-27 18:44:24 +00:00
a789f17ffc
Remove unnecessary gotos to fall-thru successors.
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llvm-svn: 85257
2009-10-27 17:40:24 +00:00
b678a56fef
Test commit. Added '.' to the comment line.
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llvm-svn: 85255
2009-10-27 17:25:15 +00:00
fb22a85baf
apparently the X86 JIT isn't fully contextized, it is still using getGlobalContext() :(
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llvm-svn: 85252
2009-10-27 17:01:03 +00:00
d90d169f9d
Correctly align double arguments in the stack.
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llvm-svn: 85235
2009-10-27 14:09:44 +00:00
538984c1c3
Now VFP instructions.
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llvm-svn: 85186
2009-10-27 00:20:49 +00:00
b02bdb4552
Change Thumb1 and Thumb2 instructions to separate opcode from operands with a tab instead of a space.
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llvm-svn: 85184
2009-10-27 00:08:59 +00:00
13edef55b6
Change ARM asm strings to separate opcode from operands with a tab instead of a space.
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llvm-svn: 85178
2009-10-26 23:45:59 +00:00
de5ad42aa1
Remove FreeInst.
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Remove LowerAllocations pass.
Update some more passes to treate free calls just like they were treating FreeInst.
llvm-svn: 85176
2009-10-26 23:43:48 +00:00
a33fa47141
Try to get ahead of Johnny Chen and pro-actively add some more ARM encoding
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bits. Johnny, please review -- I do not have a good track record of getting
these right.
llvm-svn: 85173
2009-10-26 22:59:12 +00:00
1de6a1f7d2
Fix ARM encoding typo: Opcod3 is not passed to ASuI parent class.
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Patch by Johnny Chen.
llvm-svn: 85169
2009-10-26 22:42:13 +00:00
a6aba77e0a
Add more ARM instruction encodings for 's' bit set and "rs" register encoding
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bits. Patch by Johnny Chen.
llvm-svn: 85167
2009-10-26 22:34:44 +00:00
ce8f626f82
Update CMake files.
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llvm-svn: 85161
2009-10-26 22:06:01 +00:00
0ae1b2961d
Revert r85134, it breaks mingw build
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llvm-svn: 85138
2009-10-26 18:40:24 +00:00
752aea6513
Make PIC16 overlay a loadable pass.
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llvm-svn: 85134
2009-10-26 18:22:59 +00:00
8370485db9
Break anti-dependence breaking out into its own class.
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llvm-svn: 85127
2009-10-26 16:59:04 +00:00
56869f22c4
Move DataTypes.h to include/llvm/System, update all users. This breaks the last
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direct inclusion edge from System to Support.
llvm-svn: 85086
2009-10-26 01:35:46 +00:00
5bde1cbd93
of -> or
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llvm-svn: 85065
2009-10-25 19:14:48 +00:00
5a9788b979
80-column cleanup
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llvm-svn: 85064
2009-10-25 18:55:46 +00:00
b18a46806b
Reapply 85006 with a minor fix.
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llvm-svn: 85052
2009-10-25 08:14:11 +00:00
2e7dee5f23
Add ARM getMatchingSuperRegClass to handle S / D / Q cross regclass coalescing.
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llvm-svn: 85049
2009-10-25 07:53:28 +00:00
5d1b849658
Don't forget subreg indices when folding load / store.
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llvm-svn: 85048
2009-10-25 07:52:27 +00:00
974e12b2d3
Remove includes of Support/Compiler.h that are no longer needed after the
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VISIBILITY_HIDDEN removal.
llvm-svn: 85043
2009-10-25 06:57:41 +00:00
Jim Grosbach