Commit Graph

343154 Commits

Author SHA1 Message Date
Benjamin Kramer 564a9de28e Hide implementation details. NFC> 2020-02-17 17:55:23 +01:00
Gokturk Yuksek 351ed50dcb Reland "[clang-tools-extra] fix the check for if '-latomic' is necessary""
The buildbot failures on MSVC should have been fixed by f128f442a3.
2020-02-17 16:53:29 +00:00
Matt Arsenault d9e8b2cbcc AMDGPU/GlobalISel: Skip DAG hack passes on selected functions
The way fallback to SelectionDAG works is somewhat surprising to
me. When the fallback path is enabled, the entire set of SelectionDAG
selector passes is added to the pass pipeline, and each one needs to
check if the function was selected. This results in the surprising
behavior of running SIFixSGPRCopies for example, but only if
-global-isel-abort=2 is used.

SIAddIMGInitPass is also added in addInstSelector, but I'm not sure
why we have this pass or if it should be added somewhere else for
GlobalISel.
2020-02-17 08:33:17 -08:00
Simon Pilgrim a1585aec6f [SelectionDAG] Expose the "getValidShiftAmount" helpers available. NFCI.
These are going to be useful in TargetLowering::SimplifyDemandedBits, so expose these helpers outside of SelectionDAG.cpp

Also add an getValidShiftAmountConstant early-out to getValidMinimumShiftAmountConstant/getValidMaximumShiftAmountConstant so we can use them for scalar cases as well.
2020-02-17 16:28:46 +00:00
Matt Arsenault 78d455adf0 GlobalISel: Add combine to narrow G_LSHR
Produce an unmerge to a narrower type and introduce a narrower shift
if needed. I wasn't sure if there was a better way to parameterize the
target's preferred shift type for the GICombineRule, so manually call
the combine helper.
2020-02-17 08:04:52 -08:00
Matt Arsenault 86813e2768 AMDGPU/GlobalISel: Select llvm.amdgcn.s.buffer.load
Doesn't try to fail on the dlc bit pre-gfx10 like the DAG lowering
does.
2020-02-17 08:02:40 -08:00
Haojian Wu af8b0cd58d [clang][Index] Visit the default parameter arguements in libindex.
Summary:
We are missing the default parmeter arguments when IndexFunctionLocals
is true.

Fixes https://github.com/clangd/clangd/issues/285.

Reviewers: kadircet

Subscribers: kristof.beyls, ilya-biryukov, jkorous, arphaman, usaxena95, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D74610
2020-02-17 16:45:04 +01:00
Mikhail Maltsev dd4d093762 [ARM] Add initial support for Custom Datapath Extension (CDE)
Summary:
This patch adds assembly-level support for a new Arm M-profile
architecture extension, Custom Datapath Extension (CDE).

A brief description of the extension is available at
https://developer.arm.com/architectures/instruction-sets/custom-instructions

The latest specification for CDE is currently a beta release and is
available at
https://static.docs.arm.com/ddi0607/aa/DDI0607A_a_armv8m_arm_supplement_cde.pdf

CDE allows chip vendors to add custom CPU instructions.  The CDE
instructions re-use the same encoding space as existing coprocessor
instructions (such as MRC, MCR, CDP etc.). Each coprocessor in range
cp0-cp7 can be configured as either general purpose (GCP) or custom
datapath (CDEv1).  This configuration is defined by the CPU vendor and
is provided to LLVM using 8 subtarget features: cdecp0 ... cdecp7.

The semantics of CDE instructions are implementation-defined, but the
instructions are guaranteed to be pure (that is, they are stateless,
they do not access memory or any registers except their explicit
inputs/outputs).

CDE requires the CPU to support at least Armv8.0-M mainline
architecture. CDE includes 3 sets of instructions:
* Instructions that operate on general purpose registers and NZCV
  flags
* Instructions that operate on the S or D register file (require
  either FP or MVE extension)
* Instructions that operate on the Q register file, require MVE

The user-facing names that can be specified on the command line are
the same as the 8 subtarget feature names. For example:

    $ clang -target arm-none-none-eabi -march=armv8m.main+cdecp0+cdecp3

tells the compiler that the coprocessors 0 and 3 are configured as
CDEv1 and the remaining coprocessors are configured as GCP (which is
the default).

Reviewers: simon_tatham, ostannard, dmgreen, eli.friedman

Reviewed By: simon_tatham

Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D74044
2020-02-17 15:39:16 +00:00
Matt Arsenault 5fdc9851d0 AMDGPU/GlobalISel: Run the localizer pass
While looking at the output on real sized programs, there is a lot of
extra SGPR spilling compared to the DAG path. This seems to largely be
from all constants being SGPRs in the entry block.
2020-02-17 07:38:12 -08:00
Jan Kratochvil 2178088879 Separate DIERef vs. user_id_t: m_function_scope_qualified_name_map
As discussed in https://reviews.llvm.org/D73206#1871895 there is both
`DIERef` and `user_id_t` and sometimes (for DWZ) we need to encode Main
CU into them and sometimes we cannot as it is unavailable at that point
and at the same time not even needed.

I have also noticed `DIERef` and `user_id_t` in fact contain the same
information which can be seen in SymbolFileDWARF::GetUID.

SB* API/ABI is already using `user_id_t` and it needs to encode Main CU
for DWZ. Therefore what about making `DIERef` the identifier not
containing Main CU and `user_id_t` the identifier containing Main CU?

It is sort of a revert of D63322.

I find this patch as a NFC cleanup to the codebase - to satisfy a new
premise `user_id_t` is used as little as possible and thus only for
external interfaces which must not deal with MainCU in any way.

Its larger goal is to satisfy a plan to implement DWZ support.

Differential Revision: https://reviews.llvm.org/D74637
2020-02-17 16:35:42 +01:00
Luís Marques f128f442a3 [CMake] Fix setting result of libatomic check for MSVC
We were skipping the libatomic requirement check for MSVC, but not setting
the corresponding variable, HAVE_CXX_ATOMICS_WITHOUT_LIB. D69869 seems to
have to failed to build on ARM MSVC because of that, and was reverted. This
should probably fix the issue. The plan is to check the result of the build
bots and then submit a more thoroughly refactored version for review.
2020-02-17 15:32:28 +00:00
Sander de Smalen a7a96c726e [AArch64] Implement passing SVE vectors by ref for AAPCS.
Summary:
This patch implements the part of the calling convention
where SVE Vectors are passed by reference. This means the
caller must allocate stack space for these objects and
pass the address to the callee.

Reviewers: efriedma, rovka, cameron.mcinally, c-rhodes, rengolin

Reviewed By: efriedma

Subscribers: tschuett, kristof.beyls, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D71216
2020-02-17 15:20:28 +00:00
Pierre Oechsel 0acd7e02f2 [mlir] Linalg: Extend promotion to non f32 buffers.
Summary:
Linalg's promotion pass was only supporting f32 buffers due to how the
zero value was build for the `fill` operation.

Moreover, `promoteSubViewOperands` was returning a vector with one entry
per float subview while omitting integer subviews. For a program
with only integer subviews the return vector would be of size 0.
However, `promoteSubViewsOperands` would try to access a non zero
number of entries of this vector, resulting in a sefgault.

Reviewers: nicolasvasilache, ftynse

Reviewed By: ftynse

Subscribers: mehdi_amini, rriddle, jpienaar, burmako, shauheen, antiagainst, nicolasvasilache, arpith-jacob, mgester, lucyrfox, liufengdb, Joonsoo, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D74532
2020-02-17 15:56:49 +01:00
Sjoerd Meijer dad5f00e3b [DAGCombine] Combine pattern for REV16
This adds another pattern to the combiner for a case that we were not handling
to generate the REV16 instruction for ARM/Thumb2 and a bswap+ror on X86.

Differential Revision: https://reviews.llvm.org/D74032
2020-02-17 14:54:17 +00:00
Benjamin Kramer f4c59c0f97 [wasm] Unbreak after 5fc5c7db38. NFCI. 2020-02-17 15:49:49 +01:00
Benjamin Kramer 5fc5c7db38 Strength reduce vectors into arrays. NFCI. 2020-02-17 15:37:35 +01:00
Louis Dionne 8b60ba73af [libc++] Add availability markup for std::to_chars on Apple platforms
Summary:
Otherwise, one gets link errors when trying to back-deploy to older platforms.

rdar://problem/57854364

Reviewers: lichray, EricWF

Subscribers: christof, jkorous, dexonsmith, libcxx-commits

Tags: #libc

Differential Revision: https://reviews.llvm.org/D74626
2020-02-17 09:32:46 -05:00
Matt Arsenault e5805529bf AMDGPU/GlobalISel: Select v2s32->v2s16 G_TRUNC
It would be nice if there was a way to avoid the tied operand, but as
far as I can tell there isn't a way to use or with op_sel to achieve
this
2020-02-17 09:20:13 -05:00
Matt Arsenault 361f2a7818 AMDGPU/GlobalISel: Handle sbfe/ubfe intrinsic
Try to handle arbitrary scalar BFEs by packing the operands. The DAG
gives up on non-constant arguments. We're still missing any constant
folding, so we end up with pretty ugly code most of the time. Also
handle the 64-bit scalar case, which the DAG doesn't try to do.
2020-02-17 09:20:13 -05:00
Matt Arsenault 323db5d666 GlobalISel: Add matcher for G_LSHR 2020-02-17 09:20:13 -05:00
Tim Renouf 1e926a9f9c [AMDGPU] Fix some tests that did not specify -mcpu
Summary:
This fixes some tests that did not specify -mcpu. Doing that disables
all subtarget features, which gives behavior that (a) does not
necessarily correspond to any actual target, and (b) can change as we
add new subtarget features.

Also added gfx1010 to memtime test.

Differential Revision: https://reviews.llvm.org/D74594

Change-Id: I8c0fe4fa03e9a93ef8bb722cd42d22e064526309
2020-02-17 14:02:32 +00:00
Benjamin Kramer 6704960f7c [ADT] Use inherited ctors to forward to base. NFCI. 2020-02-17 14:39:15 +01:00
Balázs Kéri d4741c44ab [ASTImporter] Added visibility check for scoped enums.
Summary:
ASTImporter makes now difference between C++11 scoped enums with same
name in different translation units if these are not visible outside.
Enum declarations are linked into decl chain correctly.

Reviewers: martong, a.sidorin, shafik, a_sidorin, teemperor

Reviewed By: shafik, a_sidorin

Subscribers: rnkovacs, dkrupp, Szelethus, gamesh411, teemperor, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D74554
2020-02-17 14:34:13 +01:00
Pavel Labath b2d64b698f [lldb] Fix build error from 07355c1c08
The error is: no matching function for call to 'transform(std::string&, std::__cxx11::basic_string<char>::iterator, <unresolved overloaded function type>)'

The fix: replace llvm::transform with an equally simple hand-rolled
loop.
2020-02-17 14:12:29 +01:00
Pavel Labath 67f63f3f7c [lldb/DWARF] Re-enable basic dwp support
Summary:
This patch removes the bitrotted SymbolFileDWARF(Dwo)Dwp classes, and
replaces them with dwp support implemented directly inside
SymbolFileDWARFDwo, in a manner mirroring the implementation in llvm.
This patch does:
- add support for the .debug_cu_index section to our DWARFContext
- adds a llvm::DWARFUnitIndex argument to the DWARFUnit constructors.
  This argument is used to look up the offsets of the debug_info and
  debug_abbrev contributions in the sections of the dwp file.
- makes sure the creation of the DebugInfo object as well as the initial
  discovery of DWARFUnits is thread-safe, as we can now call this
  concurrently when doing parallel indexing.

This patch does not:
- use the DWARFUnitIndex to search for other kinds of contributions
  (debug_loc, debug_ranges, etc.). This means that units which reference
  these sections will not work correctly. These will be handled by
  follow-up patches, but even the present level of support is sufficient
  to enable basic functionality.
- Make the llvm::DWARFContext thread-safe. Right now, it just avoids this
  problem by ensuring everything is initialized ahead of time. However,
  this is something we will run into more often as we try to use more of
  llvm, and so I plan to start looking into our options here.

Reviewers: JDevlieghere, aprantl, clayborg

Subscribers: mgorny, mgrang, lldb-commits

Tags: #lldb

Differential Revision: https://reviews.llvm.org/D73783
2020-02-17 14:10:36 +01:00
Sergej Jaskiewicz 35367e06b8 Revert "[CMake] Explicitly specify paths to libc++abi in CrossWinToARMLinux.cmake"
This reverts commit 801627ee49.
2020-02-17 16:06:30 +03:00
Pavel Labath 07355c1c08 [lldb] Delete register info definitions in the x86_64 ABI classes
Summary:
These definitions are used to "augment" information received from the remote
target with eh/debug frame and "generic" register numbers.

Besides being verbose, this information was also incomplete (new registers like
xmm16-31 were missing) and sometimes even downright wrong (ymm register
numbers).

Most of this information is available via llvm's MCRegisterInfo. This patch
creates a new class, MCBasedABI, which retrieves the eh and debug frame register
numbers this way. The tricky part here is that the llvm class uses all-caps
register names, whereas lldb register are lowercase, and sometimes called
slightly differently. Therefore this class introduces some hooks to allow a
subclass to customize the MC lookup. The subclass also needs to suply the
"generic" register numbers, as this is an lldb invention.

This patch ports the x86_64 ABI classes to use the new register info mechanism.
It also creates a new "ABIx86_64" class which can be used to house code common
to x86_64 both ABIs. Right now, this just consists of a single function, but
there are plenty of other things that could be moved here too.

Reviewers: JDevlieghere, jasonmolenda

Subscribers: mgorny, lldb-commits

Tags: #lldb

Differential Revision: https://reviews.llvm.org/D74244
2020-02-17 14:01:36 +01:00
Sergej Jaskiewicz 801627ee49 [CMake] Explicitly specify paths to libc++abi in CrossWinToARMLinux.cmake
Summary:
D69169, which was necessary for running libc++ tests on remote host, got reverted. I couldn't think of a less invasive way to achieve this behavior but specify libc++abi paths in our cache file.

Reviewers: vvereschaka, aorlov, andreil99, EricWF

Reviewed By: vvereschaka

Subscribers: mgorny, kristof.beyls, ldionne, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D74347
2020-02-17 15:24:04 +03:00
Martin Storsjö 0e1da1ef4a [LLDB] Fix GCC warnings about extra semicolons. NFC. 2020-02-17 14:16:46 +02:00
Pavel Labath d41d528648 [lldb] Add @skipIfXmlSupportMissing to TestWasm.py
These tests rely on being able to parse qXfer:libraries:read packet
(which is in xml).
2020-02-17 13:12:52 +01:00
David Green 0ac4f6b627 [ARM] MVE vector reduce MLA tests. NFC. 2020-02-17 11:54:04 +00:00
Paolo Severini c1121908aa [LLDB] Add DynamicLoaderWasmDYLD plugin for WebAssembly debugging
Add a dynamic loader plug-in class for WebAssembly modules.

Differential Revision: https://reviews.llvm.org/D72751
2020-02-17 12:42:23 +01:00
Levon Ter-Grigoryan aedc196101 [lldb/lldb-server] Add target.xml support for qXfer request.
Summary:
Synthesize target.xml in lldb-server to avoid a long chain of
qRegisterInfo packets, which can be slow over low-latency links.

Reviewers: jarin, labath

Reviewed By: labath

Subscribers: lldb-commits

Tags: #lldb

Differential Revision: https://reviews.llvm.org/D74217
2020-02-17 12:05:28 +01:00
Kerry McLaughlin 633db60f3e [AArch64][SVE] Add SVE index intrinsic
Summary:
Implements the @llvm.aarch64.sve.index intrinsic, which
takes a scalar base and step value.

This patch also adds the printSImm function to AArch64InstPrinter
to ensure that immediates of type i8 & i16 are printed correctly.

Reviewers: sdesmalen, andwar, efriedma, dancgr, cameron.mcinally, rengolin

Reviewed By: cameron.mcinally

Subscribers: tatyana-krasnukha, tschuett, kristof.beyls, hiraditya, rkruppe, arphaman, psnobl, cfe-commits, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D74550
2020-02-17 10:30:11 +00:00
Sjoerd Meijer e5043cd3c2 [AArch64] Fix small typos in the target description. NFC.
Patch by Tamas Petz.

Differential Revision: https://reviews.llvm.org/D74603
2020-02-17 10:13:47 +00:00
Simon Tatham 377b0e2b06 [TableGen] Don't elide bitconverts in PatFrag fragments.
Summary:
In the DAG pattern backend, `SimplifyTree` simplifies a pattern by
removing bitconverts between two identical types. But that function is
also run on the fragments list in instances of `PatFrags`, in which
the types haven't been specified yet. So the input and output of the
bitconvert always evaluate to the empty set of types, which makes them
compare equal. So the test always passes, and bitconverts are
unconditionally removed from the PatFrag RHS.

Fixed by spotting the empty type set and using it to inhibit the
optimization.

Reviewers: nhaehnle, hfinkel

Reviewed By: nhaehnle

Subscribers: llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D74627
2020-02-17 09:30:45 +00:00
Jan Kratochvil 516ba158b6 [lldb] [nfc] Simplify user_id_t -> size_t
As discussed in https://reviews.llvm.org/D73206#1871895> simplifying
usage of `user_id_t`.

There is even written:
  // The compile unit ID is the index of the DWARF unit.
  DWARFUnit *dwarf_cu = info->GetUnitAtIndex(comp_unit->GetID());

Differential Revision: https://reviews.llvm.org/D74670
2020-02-17 10:24:19 +01:00
Sourabh Singh Tomar 3e1090922a [NFCI][DebugInfo]: Corrected a Typo. 2020-02-17 14:50:32 +05:30
Sjoerd Meijer a02056c960 [X86] New test to check rev16 patterns, prep step for D74032. NFC. 2020-02-17 09:13:21 +00:00
Sylvestre Ledru 7ae1347fb2 clang analyzer: Fix the webpage rendering 2020-02-17 10:03:20 +01:00
Raphael Isemann cfb29e4a54 [lldb] Fix some tests failing with gmodules after change to stdlib.h
Commit 82b47b2978 changes the way the stdlib.h
header is structured which seems to cause strange lookup failures in the modules
build. This updates a few failing tests so that they pass with the new
behavior of stdlib.h.

See the discussion in https://reviews.llvm.org/rG82b47b2978405f802a33b00d046e6f18ef6a47be
2020-02-17 09:39:09 +01:00
Kang Zhang f4e920720d [NFC][PowerPC] Update the test case scalar-equal.ll
Modify the command option to add --enable-no-nans-fp-math
2020-02-17 08:34:56 +00:00
Fangrui Song dd8a2013dc [MC] Delete two unused MCCodePadder functions missed by D71106 2020-02-16 22:37:33 -08:00
QingShan Zhang 113df90388 [PowerPC] Add the missing InstrAliasing for 64-bit rotate instructions
We have the InstAlias rules for 32-bit rotate but missing the 64-bit one.
Rotate left immediate rotlwi ra,rs,n rlwinm ra,rs,n,0,31
Rotate left rotlw ra,rs,rb rlwnm ra,rs,rb,0,31

Differential Revision: https://reviews.llvm.org/D72676
2020-02-17 05:42:49 +00:00
Kang Zhang 1ae05a3c66 [NFC][PowerPC] Add a new test case scalar-equal.ll 2020-02-17 05:27:36 +00:00
Michael Liao 487fcc8d3d Fix `-Wpedantic` warning. NFC. 2020-02-17 00:18:01 -05:00
River Riddle 7a551600d1 [mlir] Address post commit feedback of D73590 for SymbolsAndSymbolTables.md 2020-02-16 21:07:20 -08:00
Craig Topper dd0b18e1ec [X86] Disable load folding for X86ISD::ADD with 128 as an immediate.
It can be turned into a sub with -128 instead as long as the
carry flag isn't used.
2020-02-16 20:52:51 -08:00
Fangrui Song c7fa409bca [CUDA][HIP][OpenMP] Add lib/Sema/UsedDeclVisitor.h after D70172 2020-02-16 20:33:07 -08:00
Craig Topper 464729cf7c [X86] Remove unnecessary check for null SDValue. NFC 2020-02-16 20:25:24 -08:00