Commit Graph

281552 Commits

Author SHA1 Message Date
Peter Collingbourne 939b16233b Fix the BinaryPredicate form of std::is_permutation to not rely on operator==
According to [1], forms 2 and 4 of std::is_permutation should use the passed in
binary predicate to compare elements. operator== should only be used for forms
1 and 3 which do not take a binary predicate.

This CL fixes forms 2 and 4 which relied on operator== for some comparisons.

[1] http://en.cppreference.com/w/cpp/algorithm/is_permutation

Patch by Thomas Anderson!

Differential Revision: https://reviews.llvm.org/D42518

llvm-svn: 323563
2018-01-26 21:23:27 +00:00
Krzysztof Parzyszek d4273abb69 [Hexagon] Make sure that offset on globals matches alignment requirements
A correctly aligned address may happen to be separated into a variable
part and a constant part, where the constant part does not match the
alignment needed in a load/store that uses this address. Such a constant
cannot be used as an immediate offset in an indexed instruction.

When lowering a global address, make sure that if there is an offset
folded into the global, the offset is valid for all uses in load/store
instructions.

llvm-svn: 323562
2018-01-26 21:20:04 +00:00
Krzysztof Parzyszek 95614acc24 [Hexagon] Replace multiple vector extracts with store-load combinations
llvm-svn: 323561
2018-01-26 21:17:14 +00:00
Wolfgang Pieb 06c0eca3c0 [DWARF] Temporarily removing a test that caused an independent failure on the mingw target.
Will recommit once that is addressed.

llvm-svn: 323560
2018-01-26 20:47:24 +00:00
Eli Friedman 29108843ff [LivePhysRegs] Preserve pristine regs in blocks with no successors.
One common source of blocks with no successors is calls to noreturn
functions; we want to preserve pristine registers in case they throw an
exception.

The whole pristine register thing is messy (we should really prefer to
explicitly model registers), but this fills a hole in the model for now.

Fixes https://bugs.llvm.org/show_bug.cgi?id=36073.

Differential Revision: https://reviews.llvm.org/D42509

llvm-svn: 323559
2018-01-26 20:23:00 +00:00
Benjamin Kramer d15b2898d3 [Support] Move PrintEscapedString into the library its declaration is in
llvm-svn: 323558
2018-01-26 20:21:02 +00:00
Benjamin Kramer a03d3198ee [X86] Unbreak the build.
X86ISelLowering.cpp:34130:5: error: return type 'llvm::SDValue' must
match previous return type 'const llvm::SDValue' when lambda expression
has unspecified explicit return type

llvm-svn: 323557
2018-01-26 20:16:43 +00:00
Alexey Bataev 7ad4e31c3b [SLP] Test for trunc vectorization, NFC.
llvm-svn: 323556
2018-01-26 20:07:55 +00:00
Craig Topper d4795b700d [X86] Allow any_extend to be combined with setcc on VLX targets.
For VLX target getSetccResultType returns vXi1 which prevents the target independent DAG combine from doing this tranform itself.

llvm-svn: 323555
2018-01-26 20:02:52 +00:00
Benjamin Kramer 4bb33349a6 Try to unbreak 32 bit builds after r323528.
llvm-svn: 323554
2018-01-26 20:01:13 +00:00
Simon Pilgrim 8e9becbd81 [X86][AVX512] Add combining support for X86ISD::VTRUNCS
Similar to the existing support for X86ISD::VTRUNCUS.

Differential Revision: https://reviews.llvm.org/D42544

llvm-svn: 323553
2018-01-26 20:01:12 +00:00
Craig Topper ace5c37c57 [X86] Add 'rdrnd' feature to silvermont to match recent gcc bug fix.
gcc recently fixed this bug https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83546

llvm-svn: 323552
2018-01-26 19:34:45 +00:00
Craig Topper 8f324bb1a4 [SelectionDAGISel] Add a debug print before call to Select. Adjust where blank lines are printed during isel process to make things more sensibly grouped.
Previously some targets printed their own message at the start of Select to indicate what they were selecting. For the targets that didn't, it means there was no print of the root node before any custom handling in the target executed. So if the target did something custom and never called SelectNodeCommon, no print would be made. For the targets that did print a message in Select, if they didn't custom handle a node SelectNodeCommon would reprint the root node before walking the isel table.

It seems better to just print the message before the call to Select so all targets behave the same. And then remove the root node printing from SelectNodeCommon and just leave a message that says we're starting the table search.

There were also some oddities in blank line behavior. Usually due to a \n after a call to SelectionDAGNode::dump which already inserted a new line.

llvm-svn: 323551
2018-01-26 19:34:20 +00:00
Craig Topper b207dd6870 [X86] Add 'rdrnd' feature to silvermont to match recent gcc bug fix.
gcc recently fixed this bug https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83546

llvm-svn: 323550
2018-01-26 19:34:14 +00:00
Argyrios Kyrtzidis 71b74ebb1e [index] Fix crash when indexing a C++14 PCH/module related to TemplateTemplateParmDecls of alias templates
TemplateTemplateParmDecls of alias templates ended-up serialized as 'file-level decls' which was causing a crash while trying to index a PCH/module file that contained them.
Commit makes sure TemplateTemplateParmDecls are not recorded as such kind of decls.

Fixes crash of rdar://36608297

Differential Revision: https://reviews.llvm.org/D42588

llvm-svn: 323549
2018-01-26 19:26:12 +00:00
Krzysztof Parzyszek 1a1edbfb04 [Hexagon] Fix an incorrect assertion in HexagonConstExtenders
llvm-svn: 323548
2018-01-26 19:20:50 +00:00
Saleem Abdulrasool f591e36b89 AST: support protocol conformances on id/class/interfaces in MS ABI
Add support for mangling ObjC protocol conformances in MS ABI as if they are
COM interfaces. By diverging from the itanium mangling of `objc_protocol`
prefixed names, this approach allows for a semi-reasonable, albeit of
questionable sanity, undecoration via existing tooling. There is also the
possibility of adding an extension and taking part of the namespace to add the
conformance via the `L` and `Z` "modifiers", but the existing tooling would not
be able to properly undecorated the symbol even though incidentally `undname`
currently produces something legible while wine's implementation is not able to
cope with the extension.

This allows for the disambiguation of overloads where the parameter differs
only in the protocol conformance of the ObjC type, e.g.

```
@protocol P;
void f(std::vector<id>);
void f(std::vector<id<P>>);
```

which clang would previously fail due to the mangling being identical as the
protocol conformance was ignored.

llvm-svn: 323547
2018-01-26 19:08:26 +00:00
Wolfgang Pieb 456b555ffe [DWARF] Generate DWARF v5 string offsets tables along with strx* index forms.
Summary: This is the producer side for DWARF v5 string offsets tables. The reader/consumer
side was committed with r321295. All compile and type units in a module share a 
contribution to the string offsets table. Indirect strings use the strx{1,2,3,4} index forms.

Reviewers: dblaikie, aprantl, JDevliegehere

Differential Revision: https://reviews.llvm.org/D42021

llvm-svn: 323546
2018-01-26 18:52:58 +00:00
Sanjay Patel b8ae262bd3 [x86] fix typo in comment; NFC
llvm-svn: 323545
2018-01-26 18:44:32 +00:00
Matt Davis b6616ae662 [NFC] Remove apostrophe to use 'it' in the possessive form.
Summary: This is  a simple change to test commit access with.

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D42586

llvm-svn: 323544
2018-01-26 18:43:57 +00:00
Craig Topper 3672f00e01 [X86] Define __IBT__ when -mibt is specified.
llvm-svn: 323543
2018-01-26 18:31:14 +00:00
Simon Pilgrim 1b14bdc0b8 [X86][AVX] LowerBUILD_VECTORAsVariablePermute - add support for VPERMILPV to v4i32/v4f32
Extension to D42431, adding support for v4i32/v4f32 as well as v2i64/v2f64 now that D42308 has landed

llvm-svn: 323542
2018-01-26 17:19:59 +00:00
Simon Pilgrim 76ede609f6 [X86][SSE] Don't colaesce v4i32 extracts
We currently coalesce v4i32 extracts from all 4 elements to 2 v2i64 extracts + shifts/sign-extends.

This seems to have been added back in the days when we tended to spill vectors and reload scalars, or ended up with repeated shuffles moving everything down to 0'th index. I don't think either of these are likely these days as we have better EXTRACT_VECTOR_ELT and VECTOR_SHUFFLE handling, and the existing code tends to make it very difficult for various vector and load combines.

Differential Revision: https://reviews.llvm.org/D42308

llvm-svn: 323541
2018-01-26 17:11:34 +00:00
Simon Pilgrim d567c27c84 [X86][SSE] Drop PMADDWD in lowerMul
As mentioned in D42258, we don't need this any more

llvm-svn: 323540
2018-01-26 16:57:36 +00:00
Nirav Dave 9896238dc9 [DAG] Teach findBaseOffset to interpret indexes of indexed memory operations
Indexed outputs are addition / subtractions and can be interpreted as such.

llvm-svn: 323539
2018-01-26 16:51:27 +00:00
Dmitry Preobrazhensky 706828157f [AMDGPU][MC] Added validation of image dst/data size (must match dmask and tfe)
See bug 36000: https://bugs.llvm.org/show_bug.cgi?id=36000

Differential Revision: https://reviews.llvm.org/D42483

Reviewers: vpykhtin, artem.tamazov, arsenm
llvm-svn: 323538
2018-01-26 16:42:51 +00:00
Pavel Labath 61e07bb481 gmodules XFAIL two more tests that only fail for android (pr36109)
llvm-svn: 323537
2018-01-26 16:05:46 +00:00
Alexander Richardson 1f9636f3ef [MIPS] Don't crash on unsized extern types with -mgpopt
Summary: This fixes an assertion when building the FreeBSD MIPS64 kernel.

Reviewers: atanasyan, sdardis, emaste

Reviewed By: sdardis

Subscribers: krytarowski, llvm-commits

Differential Revision: https://reviews.llvm.org/D42571

llvm-svn: 323536
2018-01-26 15:56:14 +00:00
Simon Pilgrim f531cf8964 [DAGCombine] reduceBuildVecToShuffle - ensure EXTRACT_VECTOR_ELT index is in range
From OSS Fuzz Test Case #5688

llvm-svn: 323535
2018-01-26 15:50:20 +00:00
Dmitry Preobrazhensky 0b4eb1ead1 [AMDGPU][MC] Added support of 64-bit image atomics
See bug 35998: https://bugs.llvm.org/show_bug.cgi?id=35998

Differential Revision: https://reviews.llvm.org/D42469

Reviewers: vpykhtin, artem.tamazov, arsenm
llvm-svn: 323534
2018-01-26 15:43:29 +00:00
Alexey Bataev 041ef2dd15 [SLP] Removed the warning about unused variable, NFC.
llvm-svn: 323533
2018-01-26 15:34:44 +00:00
Martin Probst f8e1f5c7d3 clang-format: [JS] Prevent ASI before [ and (.
Summary:
JavaScript automatic semicolon insertion can trigger before [ and (, so
avoid breaking before them if the previous token is likely to terminate
an expression.

Reviewers: djasper

Subscribers: cfe-commits, klimek

Differential Revision: https://reviews.llvm.org/D42570

llvm-svn: 323532
2018-01-26 15:07:49 +00:00
Simon Pilgrim 65ec923805 [X86][SSE] Add tests for vector truncation with PACKUS style signed saturation
PACKUS - truncates signed value, saturating to [0,unsigned_max_trunc]

llvm-svn: 323531
2018-01-26 14:58:50 +00:00
Alexey Bataev 167003df28 [SLP] Fix for PR32086: Count InsertElementInstr of the same elements as shuffle.
Summary:
If the same value is going to be vectorized several times in the same
tree entry, this entry is considered to be a gather entry and cost of
this gather is counter as cost of InsertElementInstrs for each gathered
value. But we can consider these elements as ShuffleInstr with
SK_PermuteSingle shuffle kind.

Reviewers: spatel, RKSimon, mkuper, hfinkel

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D38697

llvm-svn: 323530
2018-01-26 14:31:09 +00:00
Jonas Hahnfeld 723560d123 [OMPT] Use fuzzy return addresses in lock testcases
Use fuzzy return addresses in lock testcases so that these
testcases can also be run using the Intel Compiler.

Patch by Simon Convent!

Differential Revision: https://reviews.llvm.org/D41896

llvm-svn: 323529
2018-01-26 14:19:02 +00:00
Benjamin Kramer dfb730a032 [AST] Use bit packing to reduce sizeof(TypedefNameDecl) from 88 to 80.
We can stash the cached transparent tag bit in existing pointer padding.
Everything coming out of ASTContext is always aligned to a multiple of
8, so we have 8 spare bits.

llvm-svn: 323528
2018-01-26 14:14:11 +00:00
Dmitry Preobrazhensky 6cb42e7622 [AMDGPU][MC] Enabled disassembler for image atomic operations
See bug 35988: https://bugs.llvm.org/show_bug.cgi?id=35988

Differential Revision: https://reviews.llvm.org/D42186

Reviewers: vpykhtin, artem.tamazov, arsenm
llvm-svn: 323527
2018-01-26 14:07:38 +00:00
Simon Pilgrim 445d7c0e5c [X86] Cleanup SDLoc arguments as mentioned on D42544
llvm-svn: 323526
2018-01-26 14:00:01 +00:00
Clement Courbet 3c299e1b71 [TableGen][NFC]Remove dead variable.
llvm-svn: 323525
2018-01-26 13:21:43 +00:00
Sam McCall fdc3207dc1 [ASTImporter] avoid warnings: unused var, switch covered
llvm-svn: 323524
2018-01-26 12:06:44 +00:00
Alexey Bader d2c67a75b0 [OpenCL] Add "cles_khr_int64" extension.
Summary:
For OpenCL 1.1 embedded profile 64 bit integers i.e. long,
ulong including the appropriate vector data types and operations
on 64-bit integers are optional. The "cles_khr_int64" extension
string will be reported if the embedded profile implementation
supports 64-bit integers.

Reviewers: Anastasia, bader

Reviewed By: Anastasia, bader

Subscribers: bader, yaxunl, Anastasia, cfe-commits

Differential Revision: https://reviews.llvm.org/D42532

llvm-svn: 323522
2018-01-26 11:48:46 +00:00
Francis Visoiu Mistrih e4718e84e8 [MIR] Add support for addrspace in MIR
Add support for printing / parsing the addrspace of a MachineMemOperand.

Fixes PR35970.

Differential Revision: https://reviews.llvm.org/D42502

llvm-svn: 323521
2018-01-26 11:47:28 +00:00
Pavel Labath e8524e0ca2 Fix linux fallout from c++ gmodules enable
TestLibcxxListLoop - fails because the evil "define private public"
  trick does not work with gmodules. The purpose of the test is not to
  test debug info parsing so I just mark it as no_debug_info_testcase.
  In the long term it may be interesting to write a mock std::list which
  will allow us to test bad inputs to data formatters more easily.
TestGModules - seems to be a genuine bug. Filed pr36107 and xfailed.

llvm-svn: 323520
2018-01-26 11:40:59 +00:00
Aleksei Sidorin 8fc8510cb8 [ASTImporter] Support LambdaExprs and improve template support
Also, a number of style and bug fixes was done:

 *  ASTImporterTest: added sanity check for source node
 *  ExternalASTMerger: better lookup for template specializations
 *  ASTImporter: don't add templated declarations into DeclContext
 *  ASTImporter: introduce a helper, ImportTemplateArgumentListInfo getting SourceLocations
 *  ASTImporter: proper set ParmVarDecls for imported FunctionProtoTypeLoc

Differential Revision: https://reviews.llvm.org/D42301

llvm-svn: 323519
2018-01-26 11:36:54 +00:00
Sam McCall 24f0fa34c2 [clangd] Fix GCC build break 'declaration changes meaning'
llvm-svn: 323518
2018-01-26 11:23:33 +00:00
Eric Liu 2a27ebe670 [Tooling] Test more APIs of ToolExecutor. NFC.
llvm-svn: 323517
2018-01-26 11:10:32 +00:00
Daniil Fukalov 6e1dc68117 [AMDGPU] fix LDS f32 intrinsics
- using qualified pointer addrspace in intrinsics class to avoid .f32 mangling
- changed too common atomic mangling to ds
- added missing intrinsics to AMDGPUTTIImpl::getTgtMemIntrinsic

Reviewed by: b-sumner

Differential Revision: https://reviews.llvm.org/D42383

llvm-svn: 323516
2018-01-26 11:09:38 +00:00
Florian Hahn 212afb9fd9 [CallSiteSplitting] Fix infinite loop when recording conditions.
Fix infinite loop when recording conditions by correctly marking basic
blocks as visited.

Fixes https://bugs.llvm.org/show_bug.cgi?id=36105

llvm-svn: 323515
2018-01-26 10:36:50 +00:00
Momchil Velikov d2cc6fd90b [ARM] Accept a subset of Thumb GPR register class when emitting an SP-relative
load instruction

The function `Thumb1InstrInfo::loadRegFromStackSlot` accepts only the `tGPR`
register class. The function serves to emit a `tLDRspi` instruction and
certainly any subset of the `tGPR` register class is a valid destination of the
load.

Differential revision: https://reviews.llvm.org/D42535

llvm-svn: 323514
2018-01-26 10:20:58 +00:00
Andrei Elovikov cbc5a688f3 [X86FixupBWInsts] Prefer positive checks in the test. NFC
Reviewers: andrew.w.kaylor, craig.topper, MatzeB

Reviewed By: andrew.w.kaylor

Subscribers: aivchenk, llvm-commits

Differential Revision: https://reviews.llvm.org/D42531

llvm-svn: 323513
2018-01-26 09:50:32 +00:00