Commit Graph

391 Commits

Author SHA1 Message Date
Rui Ueyama e2efadced7 Remove Target::writeThunk.
Only MipsThunk were using the function, and the way how it wrote
thunk contents was different from ARM thunks. This patch makes
them consistent.

llvm-svn: 274997
2016-07-09 22:52:32 +00:00
Peter Smith fb05cd997c Recommit R274836 Add Thunk support framework for ARM and Mips
The TinyPtrVector of const Thunk<ELFT>* in InputSections.h can cause 
build failures on certain compiler/library combinations when Thunk<ELFT> 
is not a complete type or is an abstract class. Fixed by making Thunk<ELFT>
non Abstract.

type or is an abstract class 

llvm-svn: 274863
2016-07-08 16:10:27 +00:00
Peter Smith eeb827447e Revert R274836 Add Thunk support framework for ARM and Mips
This seems to be causing a buildbot failure on lld-x86_64-freebsd. Will
reproduce locally and fix. 

llvm-svn: 274841
2016-07-08 12:25:50 +00:00
Peter Smith de01b98a26 Add Thunk support framework for ARM and Mips
Generalise the Mips LA25 Thunk code and implement ARM and Thumb
    interworking Thunks.
    
    - Introduce a new module Thunks.cpp to store the Target Specific Thunk
      implementations.
    - DefinedRegular and Shared have a ThunkData field to record Thunk.
    - A Target can have more than one type of Thunk.
    - Support PC-relative calls to Thunks.
    - Support Thunks to PLT entries.
    - Existing Mips LA25 Thunk code integrated.
    - Support for ARMv7A interworking Thunks.
    
    Limitations:
    - Only one Thunk per SymbolBody, this is sufficient for all currently
      implemented Thunks.
    - ARM thunks assume presence of V6T2 MOVT and MOVW instructions.

    Differential revision: http://reviews.llvm.org/D21891

llvm-svn: 274836
2016-07-08 11:13:40 +00:00
Rafael Espindola 9639ec1e66 Read the implicit addend of R_386_GOT32X.
llvm-svn: 274690
2016-07-06 21:48:50 +00:00
Rafael Espindola d03e659140 Recognize R_386_GOT32X.
We don't relax it, but we at least recognize it.

llvm-svn: 274687
2016-07-06 21:41:39 +00:00
Tom Stellard 391e3a873e ELF/AMDGPU: Add support for GOT relocations
Reviewers: arsenm, rafael, tony-tye, kzhuravl, ruiu

Subscribers: llvm-commits, kzhuravl

Differential Revision: http://reviews.llvm.org/D21481

llvm-svn: 274514
2016-07-04 19:19:07 +00:00
Simon Atanasyan 002e244717 [ELF][MIPS] Support MIPS TLS relocations
The patch adds one more partition to the MIPS GOT. This time it is for
TLS related GOT entries. Such entries are located after 'local' and 'global'
ones. We cannot get a final offset for these entries at the time of
creation because we do not know size of 'local' and 'global' partitions.
So we have to adjust the offset later using `getMipsTlsOffset()` method.

All MIPS TLS relocations which need GOT entries operates MIPS style GOT
offset - 'offset from the GOT's beginning' - MipsGPOffset constant. That
is why I add new types of relocation expressions.

One more difference from othe ABIs is that the MIPS ABI does not support
any TLS relocation relaxations. I decided to make a separate function
`handleMipsTlsRelocation` and put MIPS TLS relocation handling code
there. It is similar to `handleTlsRelocation` routine and duplicates its
code. But it allows to make the code cleaner and prevent pollution of
the `handleTlsRelocation` by MIPS 'if' statements.

Differential Revision: http://reviews.llvm.org/D21606

llvm-svn: 273569
2016-06-23 15:26:31 +00:00
Rui Ueyama 39061a5220 Simplify writeThunk. NFC.
Previously, `Buf + 4` was written twice.

llvm-svn: 273337
2016-06-21 23:53:08 +00:00
Rui Ueyama 03a6cec51e Detect invalid use of R_X86_64_GOTTPOFF.
It is an ABI requirement that the relocation must be used
in MOVQ or LEAQ instructions. Previously, we ignored invalid
relocations.

llvm-svn: 273248
2016-06-21 06:03:28 +00:00
Rui Ueyama b319ae2cf1 Refactor X86TargetInfo::relaxTlsIeToLe.
`Inst` and `Op` variables are removed since they are not always
point to an instruction nor an operand. For 5-byte MOV instruction,
Op points to an instruction, which is confusing.

llvm-svn: 273246
2016-06-21 05:44:14 +00:00
Rui Ueyama 73575c4d5e Fix typo in comment.
llvm-svn: 273243
2016-06-21 05:09:39 +00:00
Rui Ueyama 3f5dd1458e Unbreak buildbots.
llvm-svn: 273242
2016-06-21 05:01:31 +00:00
Rui Ueyama 55a9def2bf Refactor X86_64TargetInfo::relaxTlsIeToLe.
This patch is to rewrite the function with a table-lookup-ish approach
so that it can read as a series of "convert this pattern to this" pattern.

llvm-svn: 273238
2016-06-21 03:42:32 +00:00
Tom Stellard 1cfb9efdf7 ELF/AMDGPU: Add support for R_AMDGPU_REL32 relocations
Reviewers: rafael, ruiu

Subscribers: kzhuravl, llvm-commits

Differential Revision: http://reviews.llvm.org/D21294

llvm-svn: 273192
2016-06-20 19:48:29 +00:00
Simon Atanasyan 4132511cdc [ELF][MIPS] Support GOT entries for non-preemptible symbols with different addends
There are two motivations for this patch. The first one is a preparation
for support MIPS TLS relocations. It might sound like a joke but for GOT
entries related to TLS relocations MIPS ABI uses almost regular approach
with creation of dynamic relocations for each GOT enty etc. But we need
to separate these 'regular' TLS related entries from MIPS specific local
and global parts of GOT. ABI declare simple solution - all TLS related
entries allocated at the end of GOT after local/global parts. The second
motivation it to support GOT relocations for non-preemptible symbols
with addends. If we have more than one GOT relocations against symbol S
with different addends we need to create GOT entries for each unique
Symbol/Addend pairs.

So we store all MIPS GOT entries in separate containers. For non-preemptible
symbols we have to maintain two data structures. The first one is MipsLocal
vector. Each entry corresponds to the GOT entry from the 'local' part
of the GOT contains the symbol's address plus addend. The second one
is MipsLocalMap. It is a map from Symbol/Addend pair to the GOT index.

Differential Revision: http://reviews.llvm.org/D21297

llvm-svn: 273127
2016-06-19 21:39:37 +00:00
Rui Ueyama c737ef5d21 Remove default values that vary depending on target.
llvm-svn: 272976
2016-06-16 23:50:25 +00:00
Rui Ueyama 2f524fb7c7 Make a switch-case a function for the sake of simplicity.
llvm-svn: 272975
2016-06-16 23:28:08 +00:00
Rui Ueyama e991a49587 Merge cases that execute the same code.
llvm-svn: 272974
2016-06-16 23:28:06 +00:00
Rui Ueyama a71ba43ed3 Early return. NFC.
llvm-svn: 272973
2016-06-16 23:28:05 +00:00
Rui Ueyama bebf4897a3 Simplify. NFC.
llvm-svn: 272972
2016-06-16 23:28:03 +00:00
Rui Ueyama 595bc5db4b Simplify *(x+y) to x[y]. NFC.
They are equivalent in C (and in C++ in this case).

llvm-svn: 272942
2016-06-16 19:48:07 +00:00
Rui Ueyama 727cd2f73f Simplify. NFC.
llvm-svn: 272924
2016-06-16 17:18:25 +00:00
Rui Ueyama e517de655b Inline a small function. NFC.
llvm-svn: 272923
2016-06-16 17:06:24 +00:00
Rui Ueyama f9d5620029 Early return. NFC.
llvm-svn: 272917
2016-06-16 16:44:52 +00:00
Rui Ueyama d089a43de4 Early return. NFC.
llvm-svn: 272915
2016-06-16 16:40:36 +00:00
Rui Ueyama 4a90f57ef2 Rename PltZero -> PltHeader.
PltZero (or PLT[0]) was an appropriate name for the little code
we have at beginning of the PLT section when we only supported x86
since the code for x86 just fits in the first PLT slot.

It's not the case anymore. The code for ARM64 occupies first two
slots, so PltZero spans PLT[0] and PLT[1], for example.
This patch renames it to avoid confusion.

llvm-svn: 272913
2016-06-16 16:28:50 +00:00
Rui Ueyama c9fee5fee6 Eliminate unnecessary call of SymbolBody::getPltVA.
For ARM and MIPS, we don't need to call this function.
This patch passes a symbol instead of a PLT entry address
so that the target handler can call it if necessary.

llvm-svn: 272910
2016-06-16 16:14:50 +00:00
Peter Smith fa4d90d5aa Add initial support for Thumb for ARMv7a
Add support for the R_ARM_THM relocations used in the objects present
    in arm-linux-gnueabihf-gcc. These are:
    R_ARM_THM_CALL
    R_ARM_THM_JUMP11
    R_ARM_THM_JUMP19
    R_ARM_THM_JUMP24
    R_ARM_THM_MOVT_ABS
    R_ARM_THM_MOVW_ABS_NC
    
    Interworking between ARM and Thumb is partially supported with BLX.
    The R_ARM_CALL relocation for ARM instructions and R_ARM_THM_CALL
    relocation for Thumb instructions will write out a BL or BLX depending
    on the state of the Target.
    
    Assumptions:
    - Availability of BLX and extended range of Thumb 4-byte Branch
      instructions.
    - In relocateOne if (Val & 0x1) == 1 target is Thumb, 0 is ARM.
      This will hold for objects that comply with the ABI for the
      ARM architecture.
    
    This is sufficient for hello world to work with a recent
    arm-linux-gnueabihf distribution.
    
    Limitations:
    No interworking for R_ARM_JUMP24, R_ARM_THM_JUMP24, R_ARM_THM_JUMP19
    and the deprecated R_ARM_PLT32 and R_ARM_PC24 instructions as these
    cannot be written out as a BLX and need a state change thunk.
    
    No range extension thunks. The R_ARM_JUMP24 and R_ARM_THM_CALL have a
    range of 16Mb

llvm-svn: 272881
2016-06-16 09:53:46 +00:00
George Rimar 2993ad2248 [ELF] - Change wording of error message.
Previously message told us that relocations could
not be used when making shared object. That was
correct because message could appear (and it is expected) 
when we linked executable.
Message should have being changed to something
that says we can't use a subset of relocations against shared
symbols.

Patch fixes the text.

llvm-svn: 272478
2016-06-11 15:59:09 +00:00
Rafael Espindola e8b8a347c7 Use errorDynRel like every other target.
llvm-svn: 272305
2016-06-09 20:42:04 +00:00
Rafael Espindola 24de767113 Rename warnDynRel.
It produces an error, so that was a bad name.

llvm-svn: 272304
2016-06-09 20:39:01 +00:00
Rafael Espindola 8dbb7e1d61 Also reject 32 bit dynamic relocs when producing executable.
They point to a shared library, so they would still overflow at runtime.

llvm-svn: 272303
2016-06-09 20:35:27 +00:00
George Rimar e6389d18dc [ELF] Replace getELFRelocationTypeName() calls with getRelName(). NFC.
That made few places in code a bit shorter.

llvm-svn: 272133
2016-06-08 12:22:26 +00:00
Rui Ueyama 3621857eac Remove break after return.
llvm-svn: 272046
2016-06-07 19:10:51 +00:00
Rui Ueyama 12ebff22cb Define a helper function to get a relocation name. NFC.
llvm-svn: 272034
2016-06-07 18:10:12 +00:00
Rui Ueyama 45a873d644 Merge duplicate code. NFC.
llvm-svn: 272032
2016-06-07 18:03:05 +00:00
Peter Smith 8646ced053 Initial support for ARM in lld.
Add support for an ARM Target and the initial set of relocations
    and PLT entries that are necessary for an ARM only hello world to
    link. This has been tested against an ARM only sysroot from the
    4.2.0 CodeSourcery Lite release.
    
    Tests have been added to test/ELF for the support that has been
    implemented.
    
    Main limitations:
    - No Thumb support
    - Relocations incomplete
    - No C++ exceptions support
    - No TLS support
    - No range extension or interworking veneer (thunk) support
    - No Build Attribute support
    - No Big-endian support
    
    The deprecated relocations R_ARM_PLT32 and R_ARM_PC24 have been
    implemented as these are used by the 4.2.0 CodeSourcery Lite release.

llvm-svn: 271993
2016-06-07 09:31:52 +00:00
Rafael Espindola e1979aed0a Implement gd to ie relaxation for aarch64.
llvm-svn: 271815
2016-06-04 23:33:31 +00:00
Rafael Espindola 69f5402b26 Use adjustRelaxExpr for tls relaxations too.
This remove some EM_386 specific code from InputSection.cpp and opens
the way for more relaxations.

llvm-svn: 271814
2016-06-04 23:22:34 +00:00
Rafael Espindola f807d47164 Rename TlsGdToLeSkip.
It will also be used for GT_TO_IE relaxations.

llvm-svn: 271813
2016-06-04 23:04:39 +00:00
Rafael Espindola 5c66b8260e Rename adjustRelaxGotExpr.
It will be used for more than just gots.

llvm-svn: 271812
2016-06-04 22:58:54 +00:00
Rafael Espindola e37d13b9ec Start adding tlsdesc support for aarch64.
This is mostly extracted from http://reviews.llvm.org/D18960.

The general idea for tlsdesc is that the two GD got entries are used
for a function pointer and its argument. The dynamic linker sets
both. In the non-dlopen case the dynamic linker sets the function to
the identity and the argument to the offset in the tls block.

All that the static linker has to do in the non-dlopen case is
relocate the code to point to the got entries and create a dynamic
relocation.

The dlopen case is more complicated, but can be implemented in another patch.

llvm-svn: 271569
2016-06-02 19:49:53 +00:00
Rafael Espindola 1c0eb972ed Simplify mask computation.
llvm-svn: 271525
2016-06-02 16:00:25 +00:00
Rafael Espindola 1016f19215 Simplify. NFC.
updateAArch64Add takes care of masking.

llvm-svn: 271524
2016-06-02 15:51:40 +00:00
Rafael Espindola 53d0a9fe40 Stort lines. NFC.
llvm-svn: 271523
2016-06-02 15:24:52 +00:00
Rafael Espindola 0f1401a8d9 Delete dead code.
AArch64 uses TLSDESC, so these are dead.

llvm-svn: 271517
2016-06-02 14:12:47 +00:00
George Rimar b720430b47 [ELF] Split too long X86_64TargetInfo::relaxGot method. NFC.
Patch adds relaxGotNoPic() method to handle no-PIC path.

llvm-svn: 271506
2016-06-02 09:22:00 +00:00
George Rimar f10c8290fa [ELF] - Implemented support for test/binop relaxations from latest ABI.
Patch implements next relaxation from latest ABI:

"Convert memory operand of test and binop into immediate operand, where binop is one of adc, add, and, cmp, or,
sbb, sub, xor instructions, when position-independent code is disabled."

It is described in System V Application Binary Interface AMD64 Architecture Processor 
Supplement Draft Version 0.99.8 (https://github.com/hjl-tools/x86-psABI/wiki/x86-64-psABI-r249.pdf, 
B.2 "B.2 Optimize GOTPCRELX Relocations").

Differential revision: http://reviews.llvm.org/D20793

llvm-svn: 271405
2016-06-01 16:45:30 +00:00
Rafael Espindola a8433c1d1b Revert "bar"
This reverts commit r271365.
Sorry, wrong branch.

llvm-svn: 271366
2016-06-01 06:15:22 +00:00