130e2c7aed
Fix a bug in x86's PreprocessForRMW logic that was exposed
...
by aggressive chain operand optimization. UpdateNodeOperands
does not modify the node in place if it would result in
a node identical to an existing node.
llvm-svn: 78297
2009-08-06 09:22:57 +00:00
82db9891fa
Missed part of recent kernel codemodel tweaks
...
llvm-svn: 78293
2009-08-06 09:11:19 +00:00
488db94e7b
Neon does not actually have VLD{234}.64 instructions.
...
These operations will have to be synthesized from other instructions.
llvm-svn: 78263
2009-08-06 00:24:27 +00:00
e148ceaf65
Add a new pre-allocation pass to assign adjacent registers for Neon instructions
...
that have that constraint. This is currently just assigning a fixed set of
registers, and it only handles VLDn for n=2,3,4 with DPR registers.
I'm going to expand it to handle more operations next; we can make it smarter
once everything is working correctly.
llvm-svn: 78256
2009-08-05 23:12:45 +00:00
741ea0d7fd
Better handle kernel code model. Also, generalize the things and fix one
...
subtle bug with small code model.
llvm-svn: 78255
2009-08-05 23:01:26 +00:00
77f33b71c7
Use GR32 for copies between GR32_NOSP and GR32_NOREX, as neither
...
is a subset of the other, but both are subsets of GR32.
llvm-svn: 78250
2009-08-05 22:18:26 +00:00
e5b5d8fbb3
When using NEON for single-precision FP, the NEON result must be placed in D0-D15 as these are the only D registers with S subregs. Introduce a new regclass to represent D0-D15 and use it in the NEON single-precision FP patterns.
...
llvm-svn: 78244
2009-08-05 21:02:22 +00:00
39fb546b9e
remove the 'DataSectionStartSuffix' and 'TextSectionStartSuffix' knobs.
...
llvm-svn: 78242
2009-08-05 20:49:52 +00:00
ef98dbe3de
Remove redundand checks: the only way to have, e.g. f32 RegVT is exactly
...
hardfloat case.
llvm-svn: 78237
2009-08-05 20:15:19 +00:00
87cc2c2dce
hasSuperClass tests for a strict superset relation, rather than
...
a superset relation. This code wants to test the regular superset
relation.
llvm-svn: 78236
2009-08-05 20:13:45 +00:00
ef42862ef5
Unbreak the stuff, this is ugly, but we cannot do better for now with 'plain' C calling conv.
...
llvm-svn: 78232
2009-08-05 19:40:16 +00:00
22ef75155e
Missed pieces for ARM HardFP ABI.
...
Patch by Sandeep Patel!
llvm-svn: 78225
2009-08-05 19:04:42 +00:00
13937d8236
Use elf Object File directly
...
llvm-svn: 78220
2009-08-05 18:13:04 +00:00
4cc1feff4f
Remove some dead code.
...
llvm-svn: 78219
2009-08-05 18:12:37 +00:00
df7ea32af7
Enable the new no-SP register classes by default. This is to address
...
PR4572. A few tests have some minor code regressions due to different
coalescing.
llvm-svn: 78217
2009-08-05 17:40:24 +00:00
9ede773c4e
Remove a redundant declaration.
...
llvm-svn: 78216
2009-08-05 17:39:44 +00:00
be47ccffef
Convert bswap test to filecheck, add more test entries & convert stuff to filecheck
...
llvm-svn: 78212
2009-08-05 16:50:53 +00:00
477fd55c9a
Fix a bug in the PIC16 backend.
...
llvm-svn: 78211
2009-08-05 16:46:43 +00:00
21788bef7c
Disable NEON single-precision FP support for Cortex-A8, for now...
...
llvm-svn: 78209
2009-08-05 16:40:57 +00:00
44c4417812
Remove dead code. MDNode and MDString are not Constant anymore.
...
llvm-svn: 78207
2009-08-05 16:40:02 +00:00
2e627cb37f
Add memory versions of some instructions.
...
Patch by Neale Ferguson!
llvm-svn: 78203
2009-08-05 16:16:11 +00:00
a307edbdd5
By default, for cortex-a8 use NEON for single-precision FP.
...
llvm-svn: 78200
2009-08-05 16:01:19 +00:00
cb781cfe81
Special constants as destinations does not work as expected - drop the patterns.
...
llvm-svn: 78191
2009-08-05 14:42:00 +00:00
ba3a342c89
Alpha: Get section directives right
...
llvm-svn: 78189
2009-08-05 13:59:57 +00:00
de8b1b2e7d
Cleanup in dbg_stoppoint handling in CBE. Patch by Sandeep Patel.
...
llvm-svn: 78182
2009-08-05 09:31:40 +00:00
68d8634871
Minor arm CBE fixes. Patch by Sandeep.
...
llvm-svn: 78181
2009-08-05 09:31:07 +00:00
fe4ce2ae7a
Emit module-level inline asm for CBE.
...
Patch by Sandeep Patel
llvm-svn: 78180
2009-08-05 09:29:56 +00:00
2b1dc9a783
- Remove custom handling of jumptables by the elf writter (this was
...
a dirty hack and isn't need anymore since the last x86 code emitter patch)
- Add a target-dependent modifier to addend calculation
- Use R_X86_64_32S relocation for X86::reloc_absolute_word_sext
- Use getELFSectionFlags whenever possible
- fix getTextSection to use TLOF and emit the right text section
- Handle global emission for static ctors, dtors and Type::PointerTyID
- Some minor fixes
llvm-svn: 78176
2009-08-05 06:57:03 +00:00
e219be7346
80 col violations.
...
llvm-svn: 78175
2009-08-05 06:41:25 +00:00
8c79569853
Teach X86FastISel how to handle CCValAssign::BCvt, which is used for
...
MMX arguments. This fixes PR4684.
llvm-svn: 78163
2009-08-05 05:33:42 +00:00
d055488c72
Clarify common linkage and the requirements on it. Enforce
...
them in the verifier.
llvm-svn: 78160
2009-08-05 05:21:07 +00:00
cbc7b26542
expose SectionKindForGlobal to curious clients, named as
...
getKindForGlobal.
llvm-svn: 78156
2009-08-05 04:25:40 +00:00
85f60cc5a8
Oops. I didn't mean to commit this piece yet.
...
llvm-svn: 78146
2009-08-05 02:47:13 +00:00
f9bbcd1afd
Major calling convention code refactoring.
...
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 01:29:28 +00:00
cbf1e16ad9
Remove an unnecessary flush in the CppBackend's output.
...
llvm-svn: 78138
2009-08-05 01:06:38 +00:00
c6b5e8a5c5
Don't flush the raw_ostream between each MachineFunction. These flush
...
calls were originally put in place because errs() at one time was
not unbuffered, and these print routines are commonly used with errs()
for debugging. However, errs() is now properly unbuffered, so the
flush calls are no longer needed. This significantly reduces the
number of write(2) calls for regular asm printing when there are many
small functions.
llvm-svn: 78137
2009-08-05 00:49:25 +00:00
20f79e321e
Change DAG nodes for Neon VLD2/3/4 operations to return multiple results.
...
Get rid of yesterday's code to fix the register usage during isel.
Select the new DAG nodes to machine instructions. The new pre-alloc pass
to choose adjacent registers for these results is not done, so the
results of this will generally not assemble yet.
llvm-svn: 78136
2009-08-05 00:49:09 +00:00
1b02ceeb41
1) Proper emit displacements for x86, using absolute relocations where necessary
...
for ELF to work.
2) RIP addressing: Use SIB bytes for absolute relocations where RegBase=0,
IndexReg=0.
3) The JIT can get the real address of cstpools and jmptables during
code emission, fix that for object code emission
llvm-svn: 78129
2009-08-05 00:11:21 +00:00
7cc6aca1e6
Fix part 1 of pr4682. PICADD is a 16-bit instruction even in thumb2 mode.
...
llvm-svn: 78126
2009-08-04 23:47:55 +00:00
a8720101b5
Replace dregsingle operand modifier with explicit escaped curly brackets.
...
For other VLDn and VSTn operations, we need to list the multiple registers
explicitly anyway, so there's no point in special-casing this one usage.
llvm-svn: 78109
2009-08-04 21:39:33 +00:00
f2dbd2e205
Restlyize to match other targets, fixes cmake build to boot.
...
llvm-svn: 78105
2009-08-04 21:27:06 +00:00
783b65b546
Enable load / store multiple pass for Thumb2. It's not using ldrd / strd yet.
...
llvm-svn: 78104
2009-08-04 21:12:13 +00:00
cd450bbbe5
remove a random reference to subtarget. Even without this, we
...
still get "intel syntax" instructions from llc with
-x86-asm-syntax=intel
llvm-svn: 78103
2009-08-04 21:12:08 +00:00
30bf625ac2
Add NEON single-precision FP support for fabs and fneg.
...
llvm-svn: 78101
2009-08-04 20:39:05 +00:00
16dc0cd8a2
rip out SectionEndDirectiveSuffix support, only uses by
...
the masm backend. If anyone cares about masm in the future,
we'll have semantic sections it can hang off of.
llvm-svn: 78096
2009-08-04 20:09:41 +00:00
d302ab9961
Most flags are reserved registers on Blackfin.
...
The only exception is CC.
llvm-svn: 78089
2009-08-04 19:16:55 +00:00
a3abe2a7ce
In thumb mode, r7 is used as frame register. This fixes pr4681.
...
llvm-svn: 78086
2009-08-04 18:46:17 +00:00
a3839bc6c0
Match common pattern for FNMAC. Add NEON SP support.
...
llvm-svn: 78085
2009-08-04 18:44:29 +00:00
b4c28d23e1
Legalize i64 store operations generated by inst-combine.
...
llvm-svn: 78082
2009-08-04 17:59:16 +00:00
3b9c52c5c1
Initial support for single-precision FP using NEON. Added "neonfp" attribute to enable. Added patterns for some binary FP operations.
...
llvm-svn: 78081
2009-08-04 17:53:06 +00:00
ed65bf420d
Avoid compiler warning (in -Asserts mode)
...
llvm-svn: 78070
2009-08-04 16:46:12 +00:00
f222054df7
enhance codegen to put 16-bit character strings into the
...
__TEXT,__ustring section on darwin.
llvm-svn: 78068
2009-08-04 16:27:13 +00:00
eee9df0e97
fix a fixme: don't create an explicit "CStringSection" for ELF,
...
it is just being used as a prefix, so forward substitute it directly.
llvm-svn: 78067
2009-08-04 16:19:50 +00:00
81bbf443fe
Add support emiting for 2/4 byte mergable strings to the ".rodata.str*"
...
section on ELF targets.
llvm-svn: 78066
2009-08-04 16:13:09 +00:00
d0a53d380a
Ooops, I was too fast to commit the wrong fix :(
...
llvm-svn: 78060
2009-08-04 11:18:31 +00:00
3c5b68e2a7
Fix a typo - this unbreaks llvm-gcc build on arm
...
llvm-svn: 78059
2009-08-04 11:12:51 +00:00
3870fbb561
Thumb2 does not have ib (increment before) and da (decrement after) forms of ldm / stm.
...
llvm-svn: 78057
2009-08-04 08:34:18 +00:00
b58dc1c667
make MergeableCString be a SectionKind "abstract class", and
...
add new concrete versions for 1/2/4-byte mergable strings.
These are not actually created yet.
llvm-svn: 78055
2009-08-04 05:35:56 +00:00
ad9a6c4855
No really, it's unused.
...
llvm-svn: 78047
2009-08-04 04:08:40 +00:00
09c1d0002b
Remove now unused Module argument to createTargetMachine.
...
llvm-svn: 78043
2009-08-04 04:02:45 +00:00
f43cf709cb
Remove ARM specific getInlineAsmLength. We'll rely on the simpler (and faster) generic algorithm for now. If more accurate computation is needed, we'll rely on the disassembler.
...
llvm-svn: 78032
2009-08-04 01:56:09 +00:00
71756e789b
Load / store multiple pass fixes for Thumb2. Not enabled yet.
...
llvm-svn: 78031
2009-08-04 01:43:45 +00:00
03eb0e3c33
Emit sub r, #c instead of transforming it to add r, #-c if c fits in 8-bit. This is a bit of pre-mature optimization. 8-bit variant makes it likely it will be narrowed to a 16-bit instruction.
...
llvm-svn: 78030
2009-08-04 01:41:15 +00:00
f45dee3ad2
Lower Neon VLD* intrinsics to custom DAG nodes, and manually allocate the
...
results to fixed registers.
llvm-svn: 78025
2009-08-04 00:36:16 +00:00
17f8878114
Minor cleanup. No functional changes intended.
...
llvm-svn: 78024
2009-08-04 00:25:01 +00:00
3ddfff98a0
Update CMake files.
...
llvm-svn: 78020
2009-08-03 23:44:01 +00:00
d033a62ff7
remove an unneeded section switch.
...
llvm-svn: 78014
2009-08-03 23:02:45 +00:00
661710c51d
switch ppc to using SwitchToSection instead of textual section stuff.
...
llvm-svn: 78013
2009-08-03 22:52:21 +00:00
09441faba9
use TLOF to compute the section for a function instead of
...
replicating the logic manually.
llvm-svn: 78011
2009-08-03 22:32:50 +00:00
73ebe435ca
convert macho stub emission to use SwitchToSection instead of
...
textual sections.
llvm-svn: 78007
2009-08-03 22:18:15 +00:00
e7a932d145
hoist some common code out of a switch
...
llvm-svn: 78006
2009-08-03 22:16:57 +00:00
feb01a100b
this really shouldn't switch sections without telling the asmprinter, but
...
hey it uses .previous, so it should work :)
llvm-svn: 78004
2009-08-03 21:57:00 +00:00
d2c179c8f6
Eliminate textual section switching from the x86 backend, one
...
more step towards "semantics sections"
llvm-svn: 78002
2009-08-03 21:53:27 +00:00
f307e0bd6d
Lower CONCAT_VECTOR during legalization instead of matching it during isel.
...
Add a testcase.
llvm-svn: 77992
2009-08-03 20:36:38 +00:00
a73416bd1c
Minor stylistic cleanups in the Blackfin target.
...
Thanks Chris.
llvm-svn: 77987
2009-08-03 19:32:30 +00:00
87a2ebd77d
remove a dead switch directive, replace it with some
...
code that I will be using shortly.
llvm-svn: 77983
2009-08-03 19:10:44 +00:00
3aa1e77572
Remove neverHasSideEffects on MMX_MOVD64rrv164 since it has a matching pattern.
...
llvm-svn: 77978
2009-08-03 18:07:19 +00:00
21f54a7572
eliminate textual section switching from intel asm printer.
...
This will cause it to enter the ".text" section instead of "_text"
but masm is already broken.
llvm-svn: 77977
2009-08-03 18:06:07 +00:00
1b7868ec54
Change C, CBE, MSIL to not provide target data via getTargetData().
...
- The theory is these should never actually be called, since these boil down to
passes which can access the target data via the standard mechanism.
llvm-svn: 77975
2009-08-03 17:40:25 +00:00
c28b306423
llvm_report_error already prints "LLVM ERROR:". So stop reporting errors like "LLVM ERROR: llvm: error:" or "LLVM ERROR: ERROR:".
...
llvm-svn: 77971
2009-08-03 13:33:33 +00:00
f48daf5823
Unbreak win64 compilation callback.
...
Since we're generating stubs by hands we don't follow the ABI and don't
create a register spill area.
Don't use this area in compilation callback!
llvm-svn: 77968
2009-08-03 08:43:36 +00:00
03056efe01
Create proper frame index for FP
...
llvm-svn: 77966
2009-08-03 08:14:30 +00:00
7d80ab1593
Perform bitconvert to proper type
...
llvm-svn: 77965
2009-08-03 08:14:14 +00:00
442beabbf7
Add 'Indirect' LocInfo class and use to pass __m128 on win64. Also minore fixes here and there (mostly __m64).
...
llvm-svn: 77964
2009-08-03 08:13:56 +00:00
72bc3846bc
Cleanup Darwin MMX calling conv stuff - make the stuff more generic. This also fixes a subtle bug, when 6th v1i64 argument passed wrongly.
...
llvm-svn: 77963
2009-08-03 08:13:24 +00:00
71386e08fe
Unbreak Win64 CC. Step one: honour register save area, fix some alignment and provide a different set of call-clobberred registers.
...
llvm-svn: 77962
2009-08-03 08:12:53 +00:00
70e9816624
Use movd instead of movq
...
llvm-svn: 77956
2009-08-03 05:21:05 +00:00
719d235520
Remove now unused arguments from TargetRegistry::lookupTarget.
...
llvm-svn: 77950
2009-08-03 04:20:57 +00:00
97f7dfb862
These are done.
...
llvm-svn: 77949
2009-08-03 04:08:36 +00:00
0f16ea5c30
Pass target triple string in to TargetMachine constructor.
...
This is not just a matter of passing in the target triple from the module;
currently backends are making decisions based on the build and host
architecture. The goal is to migrate to making these decisions based off of the
triple (in conjunction with the feature string). Thus most clients pass in the
target triple, or the host triple if that is empty.
This has one important change in the way behavior of the JIT and llc.
For the JIT, it was previously selecting the Target based on the host
(naturally), but it was setting the target machine features based on the triple
from the module. Now it is setting the target machine features based on the
triple of the host.
For LLC, -march was previously only used to select the target, the target
machine features were initialized from the module's triple (which may have been
empty). Now the target triple is taken from the module, or the host's triple is
used if that is empty. Then the triple is adjusted to match -march.
The take away is that -march for llc is now used in conjunction with the host
triple to initialize the subtarget. If users want more deterministic behavior
from llc, they should use -mtriple, or set the triple in the input module.
llvm-svn: 77946
2009-08-03 04:03:51 +00:00
7bdf4c2cec
Fix the instruction encoding.
...
llvm-svn: 77944
2009-08-03 03:27:05 +00:00
854d34a9fb
Remove a bitcast that was a no-op.
...
Thanks to Eli Friedman for noticing it.
llvm-svn: 77942
2009-08-03 03:00:05 +00:00
18ba271a79
Use movq to move 64 bits in and out of mmx registers.
...
Fixes PR4669
llvm-svn: 77940
2009-08-03 02:45:34 +00:00
8b9deebba3
Use the i12 variant of load / store opcodes if offset is zero. Now we pass all of multisource as well.
...
llvm-svn: 77939
2009-08-03 02:38:06 +00:00
57c11da8df
Remove -disable-mips-abicall and -enable-mips-absolute-call command-line
...
options, which don't appear to be useful. -enable-mips-absolute-call is
completely unused (and unless I'm mistaken, is supposed to have the
same effect that -relocation-model=dynamic-no-pic should have),
and -disable-mips-abicall appears to be effectively a
synonym for -relocation-model=static. Adjust the few users of hasABICall
to checks which seem more appropriate. Update MipsSubtarget,
MipsTargetMachine, and MipselTargetMachine to synchronize with recent
changes.
llvm-svn: 77938
2009-08-03 02:22:28 +00:00
6eecd56efc
- s/DOUT/DEBUG(errs()/g
...
- Tidy up some headers.
llvm-svn: 77929
2009-08-03 00:11:34 +00:00
c3719c36e6
Move most targets TargetMachine constructor to only taking a target triple.
...
- The C, C++, MSIL, and Mips backends still need the module.
llvm-svn: 77927
2009-08-02 23:37:13 +00:00
bbb772ace9
Add extra SEXT pattern.
...
llvm-svn: 77920
2009-08-02 22:45:24 +00:00
d35fbe4595
The x86 jit doesn't generate a def_cfa_offset unwind instruction after the
...
pushes in the function prolog if the function doesn't have any stack space,
i.e. for a prolog like:
0x40011870: push %r15
0x40011872: push %r14
0x40011874: push %rbx
Patch by Zoltan!
llvm-svn: 77919
2009-08-02 22:25:37 +00:00
31b44e8f6c
Normalize Subtarget constructors to take a target triple string instead of
...
Module*.
Also, dropped uses of TargetMachine where unnecessary. The only target which
still takes a TargetMachine& is Mips, I would appreciate it if someone would
normalize this to match other targets.
llvm-svn: 77918
2009-08-02 22:11:08 +00:00
7dc3b72685
Remove unneeded intrinsics from Blackfin backend.
...
__builtin_bfin_ones does the same as ctpop, so it can be implemented in the front-end.
__builtin_bfin_loadbytes loads from an unaligned pointer with the disalignexcpt instruction. It does the same as loading from a pointer with the low bits masked. It is better if the front-end creates a masked load. We can always instruction select the masked to disalignexcpt+load.
We keep csync/ssync/idle. These intrinsics represent instructions that need workarounds for some silicon revisions. We may even want to convert inline assembler to intrinsics to enable the workarounds.
llvm-svn: 77917
2009-08-02 21:49:05 +00:00
2a21149b20
Add some basic blackfin intrinsics.
...
llvm-svn: 77903
2009-08-02 18:28:11 +00:00
ddddf2d549
Add support for CPU features (i.e., bugs) and workarounds.
...
This is just the framework to identify the needed workarounds. They are not actually implemented.
llvm-svn: 77902
2009-08-02 18:27:36 +00:00
b052972a58
Inline assembly support for Blackfin.
...
We use the same constraints as GCC, including those that are slightly insane for inline assembler.
llvm-svn: 77899
2009-08-02 17:39:17 +00:00
552d8d6618
Analog Devices Blackfin back-end.
...
Generate code for the Blackfin family of DSPs from Analog Devices:
http://www.analog.com/en/embedded-processing-dsp/blackfin/processors/index.html
We aim to be compatible with the exsisting GNU toolchain found at:
http://blackfin.uclinux.org/gf/project/toolchain
The back-end is experimental.
llvm-svn: 77897
2009-08-02 17:32:10 +00:00
757eee8a27
Fix indentation.
...
llvm-svn: 77895
2009-08-02 16:10:52 +00:00
73efcaf6e1
Add a comment.
...
llvm-svn: 77894
2009-08-02 16:10:01 +00:00
1ccfa8bdc1
Resync lea32addr and lea64addr.
...
llvm-svn: 77893
2009-08-02 16:09:17 +00:00
1472cf5b3f
move dwarf debug info section selection stuff from TAI to
...
TLOF, unifying all the dwarf targets at the same time.
llvm-svn: 77889
2009-08-02 07:24:22 +00:00
c784feba8e
convert EHFrameSection to be managed by TLOF instead of TAI.
...
llvm-svn: 77888
2009-08-02 06:52:36 +00:00
bdde99bd42
I need Triple information, 10.6 shouldn't set this, it bloats
...
object files.
llvm-svn: 77887
2009-08-02 06:51:58 +00:00
8a0db7516e
ARM TAI no longer needs a TM, but createTargetAsmInfo() still does.
...
llvm-svn: 77878
2009-08-02 05:23:52 +00:00
e98a3c3ca3
Move the getInlineAsmLength virtual method from TAI to TII, where
...
the only real caller (GetFunctionSizeInBytes) uses it.
The custom ARM implementation of this is basically reimplementing
an assembler poorly for negligible gain. It should be removed
IMNSHO, but I'll leave that to ARMish folks to decide.
llvm-svn: 77877
2009-08-02 05:20:37 +00:00
0161419259
move a virtual method body to its .cpp file to avoid a #include
...
in a header.
llvm-svn: 77874
2009-08-02 04:58:19 +00:00
1fe76c385b
turn some templated inline functions into static functions.
...
llvm-svn: 77873
2009-08-02 04:52:00 +00:00
df672c2bb2
alpha TAI doesn't need TM.
...
llvm-svn: 77872
2009-08-02 04:46:05 +00:00
d4c8fd44ee
MSP430 TAI doesn't need TM.
...
llvm-svn: 77871
2009-08-02 04:45:22 +00:00
d45a7860ec
simplify SPULinuxTargetAsmInfo, remove use of TM.
...
llvm-svn: 77869
2009-08-02 04:44:33 +00:00
2be66ce420
xcore TAI doesn't need TM.
...
llvm-svn: 77868
2009-08-02 04:42:09 +00:00
3ea23cff65
PIC16 TAI doesn't need TM
...
llvm-svn: 77867
2009-08-02 04:41:14 +00:00
fb53861ee0
remove the dead ELFTargetAsmInfo.h/cpp file. TargetAsmInfo
...
defaults to being ELF.
llvm-svn: 77866
2009-08-02 04:33:09 +00:00
7ee0246f51
eliminate the TM argument to the TAI class, remove comment about supporting
...
solaris :)
llvm-svn: 77865
2009-08-02 04:32:07 +00:00
d39874e6ec
eliminate TargetMAchine argument to sparc TAI
...
llvm-svn: 77864
2009-08-02 04:30:59 +00:00
b25afe081c
remove TargetAsmInfo::TM, which is now dead. The basic TAI class now
...
no longer depends on TM!
llvm-svn: 77863
2009-08-02 04:27:24 +00:00
cecdb9e772
remove the x86/ppc impls of getEHGlobalPrefix, which is already dead.
...
llvm-svn: 77861
2009-08-02 04:13:22 +00:00
f526fb7e9a
clean up #includes of TargetAsmInfo.cpp
...
llvm-svn: 77858
2009-08-02 04:09:22 +00:00
29c6c43cd0
remove the dead PreferredEHDataFormat TAI hook: its now dead
...
even considering #if 0 code.
llvm-svn: 77856
2009-08-02 04:02:52 +00:00
c16c75ea9b
move getDwarfExceptionSection from TAI to TLOF and rename it to
...
getLSDASection() to be more specific. This makes it pretty obvious
that the ELF LSDA section is being specified wrong in PIC mode. We're
probably getting a lot of startup-time relocations to a readonly page,
which is expensive and bad.
Someone who cares about ELF C++ should investigate this.
llvm-svn: 77847
2009-08-02 01:34:32 +00:00
cc5e54e986
Fix a possible crash on delete of an uninitialized variable.
...
llvm-svn: 77846
2009-08-02 01:25:15 +00:00
321dc97adf
Don't call SectionForGlobal for hasAvailableExternallyLinkage()
...
variables either.
llvm-svn: 77844
2009-08-02 01:18:44 +00:00
a17d2e5c21
don't call SectionForGlobal on declarations, you can't tell the section a
...
declaration will end up in.
llvm-svn: 77843
2009-08-02 01:02:43 +00:00
4e7dfafc03
convert ctors/dtors section to be in TLOF instead of
...
TAI.
llvm-svn: 77842
2009-08-02 00:34:36 +00:00
9836976567
don't override the default of this, the only difference is \t instead of ' '.
...
llvm-svn: 77838
2009-08-02 00:12:20 +00:00
b2aebed2dc
Change MCOperand to use Create style instead of Make style for constructing
...
operands.
llvm-svn: 77837
2009-08-02 00:09:22 +00:00
73d577c933
Make SectionKind::get() private.
...
llvm-svn: 77835
2009-08-02 00:02:44 +00:00
f8d9710b6f
(re)introduce new simpler apis for creation sectionkinds.
...
llvm-svn: 77834
2009-08-01 23:57:16 +00:00
0c40266b5a
Remove "JumpTableDataSection" from TAI, instead, have AsmPrinter
...
compute it based on what it knows. As part of this, rename getSectionForMergeableConstant
to getSectionForConstant because it works for non-mergable constants also.
The only functionality change from this is that Xcore will start dropping
its jump tables into readonly section instead of data section in -static mode.
This should be fine as the linker resolves the relocations. If this is a
problem, let me know and we'll come up with another solution.
llvm-svn: 77833
2009-08-01 23:46:12 +00:00
cc71620c86
give alpha its readonly section. This optimizes alpha, and prevents a
...
testsuite regression with a coming patch.
llvm-svn: 77832
2009-08-01 23:44:04 +00:00
84b453aca4
.rdata == .rodata on mips.
...
llvm-svn: 77827
2009-08-01 23:07:29 +00:00
b1a3309a18
no need to override the default with the default.
...
llvm-svn: 77826
2009-08-01 23:05:25 +00:00
b2bbb61f33
REmove dead fields of TAI.
...
llvm-svn: 77820
2009-08-01 22:40:22 +00:00
5aa4952625
update for rename
...
llvm-svn: 77817
2009-08-01 22:06:53 +00:00
d5c01136ef
fix a fixme by sinking various target-specific directives down into
...
the appropriate subclasses.
llvm-svn: 77815
2009-08-01 21:56:13 +00:00
286326ed24
coff also doesn't have a ReadOnlySection yet, (!)
...
llvm-svn: 77814
2009-08-01 21:49:24 +00:00
bc3d5f5db0
coff doesn't set a .bss seciton, so this is dead.
...
llvm-svn: 77813
2009-08-01 21:48:25 +00:00
26fb277f92
it turns out that isWeak() was basically dead anyway. Kill off SectionInfo :-/
...
llvm-svn: 77812
2009-08-01 21:46:23 +00:00
72c3e7746f
don't use isWeak anymore.
...
llvm-svn: 77810
2009-08-01 21:42:58 +00:00
9139b02cda
Fix typos in comments.
...
llvm-svn: 77806
2009-08-01 21:25:00 +00:00
c9c277ba0f
Change SectionKind to be a property that is true of a *section*, it
...
should have no state that is specific to particular globals in the
section. In this case, it means the removal of the "isWeak" and
"ExplicitSection" bits. MCSection uses the new form of SectionKind.
To handle isWeak, I introduced a new SectionInfo class, which is
SectionKind + isWeak, and it is used by the part of the code generator
that does classification of a specific global.
The ExplicitSection disappears. It is moved onto MCSection as a new
"IsDirective" bit. Since the Name of a section is either a section
or directive, it makes sense to keep this bit in MCSection. Ultimately
the creator of MCSection should canonicalize (e.g.) .text to whatever
the actual section is.
llvm-svn: 77803
2009-08-01 21:11:14 +00:00
c278621694
Minor code cleanups.
...
llvm-svn: 77795
2009-08-01 19:14:37 +00:00
04e3a30a21
Add newline at end of file to remove gcc warning.
...
llvm-svn: 77791
2009-08-01 19:09:44 +00:00
95bad379a9
All MCSections are now required to have a SectionKind.
...
llvm-svn: 77787
2009-08-01 18:25:49 +00:00
e64f48ba8b
Workaround a couple of Darwin assembler bugs.
...
llvm-svn: 77781
2009-08-01 06:13:52 +00:00
edfad17d9b
Minor code simplifications.
...
llvm-svn: 77768
2009-08-01 03:42:59 +00:00
e6e8289d72
Split t2MOVCCs since some assemblers do not recognize mov shifted register alias with predicate.
...
llvm-svn: 77764
2009-08-01 01:43:45 +00:00
d0984565de
The X86 maximal stack alignment calculator preserves the CFG. Also,
...
be more careful about the return value of runOnMachineFunction.
llvm-svn: 77758
2009-08-01 00:31:02 +00:00
6735e10fb0
X86 floating-point passes don't modify the CFG.
...
llvm-svn: 77757
2009-08-01 00:26:16 +00:00
6ab54fdb0a
Fix Thumb2 function call isel. Thumb1 and Thumb2 should share the same
...
instructions for calls since BL and BLX are always 32-bit long and BX is always
16-bit long.
Also, we should be using BLX to call external function stubs.
llvm-svn: 77756
2009-08-01 00:16:10 +00:00
82e72324dd
Use setPreservesAll in X86CodeEmitter.
...
llvm-svn: 77755
2009-07-31 23:44:16 +00:00
a4fc8d94ce
llvm-mc: A few more parsing / match tweaks.
...
- Operands which are just a label should be parsed as immediates, not memory
operands (from the assembler perspective).
- Match a few more flavors of immediates.
- Distinguish match functions for memory operands which don't take a segment
register.
- We match the .s for "hello world" now!
llvm-svn: 77745
2009-07-31 22:22:54 +00:00
95d6325859
t2BR_JT is mov pc, it's 2 byte long, not 4.
...
llvm-svn: 77744
2009-07-31 22:22:22 +00:00
9eb3f88048
Thumb2 movcc need .w suffix.
...
llvm-svn: 77743
2009-07-31 22:21:55 +00:00
63779b8d57
PreferredEHDataFormat is always call with data and global, but this whole
...
thing is #if0'd out anyway. Just simplify the code by reducing the interface.
Not deleting this is essential for Bill's continuing happiness.
llvm-svn: 77736
2009-07-31 21:39:55 +00:00
3ebf848b47
llvm-mc/X86: Sketch match functions for immediates and memory operands.
...
Also, change scale value to always be 1 when unspecified to machine MachineInst
encoding.
llvm-svn: 77728
2009-07-31 20:53:16 +00:00
d25701c114
move emitUsedDirectiveFor to TargetLoweringObjectFile and rename it to
...
indicate that it is a predicate, not an emitter. This eliminates TAI
dependencies on Mangler and GlobalValue.
llvm-svn: 77726
2009-07-31 20:52:39 +00:00
740749b470
remove the PPCLinuxTargetAsmInfo implementation of PreferredEHDataFormat,
...
because it just calls the default impl.
Remove the PPCDarwinTargetAsmInfo version of PreferredEHDataFormat because
it just returns DW_EH_PE_absptr unless on 10.6. However, 10.6 doesn't support
PPC, so the default impl is just fine.
llvm-svn: 77724
2009-07-31 20:43:26 +00:00
5ebf64e075
remove a pointless override.
...
llvm-svn: 77723
2009-07-31 20:36:15 +00:00
5a1acd9912
Move a few more APIs back to 2.5 forms. The only remaining ones left to change back are
...
metadata related, which I'm waiting on to avoid conflicting with Devang.
llvm-svn: 77721
2009-07-31 20:28:14 +00:00
45d7185117
Whitespace and 80-col cleanup.
...
llvm-svn: 77718
2009-07-31 20:07:27 +00:00
4d2c0f9008
switch off of 'Section' onto MCSection. We're not properly using
...
MCSection subclasses yet, but this is a step in the right direction.
llvm-svn: 77708
2009-07-31 18:48:30 +00:00
be8422e8e0
Until we have a "ALIGN" pseudo instruction, have asm printer emitted a .align
...
to ensure the instruction that follows a TBB (when the number of table entries
is odd) is 2-byte aligned.
Patch by Sandeep Patel.
llvm-svn: 77705
2009-07-31 18:35:56 +00:00
f6d0fa3d33
- Teach TBB / TBH offset limits are 510 and 131070 respectively since the offset
...
is scaled by two.
- Teach GetInstSizeInBytes about TBB and TBH.
llvm-svn: 77701
2009-07-31 18:28:05 +00:00
ca8135379e
Normalize target registration code.
...
llvm-svn: 77692
2009-07-31 18:16:53 +00:00
5ea74d55ce
Reapply r77654 with a fix: MachineFunctionPass's getAnalysisUsage
...
shouldn't do AU.setPreservesCFG(), because even though CodeGen passes
don't modify the LLVM IR CFG, they may modify the MachineFunction CFG,
and passes like MachineLoop are registered with isCFGOnly set to true.
llvm-svn: 77691
2009-07-31 18:16:33 +00:00
51d5b43cda
refactor section construction in TLOF to be through an explicit
...
initialize method, which can be called when an MCContext is available.
llvm-svn: 77687
2009-07-31 17:42:42 +00:00
fc0264a38e
fix PR4650: we only track sizes for certain objects, so only put something
...
into the mergable section if it is one of our special cases. This could
obviously be improved, but this is the minimal fix and restores us to the
previous behavior.
llvm-svn: 77679
2009-07-31 16:17:13 +00:00
b60210ebab
Fix a struct/class mismatch, to silence a MSVC warning.
...
llvm-svn: 77673
2009-07-31 11:35:26 +00:00
7de154708a
define target names for std libcalls.
...
llvm-svn: 77667
2009-07-31 07:35:57 +00:00
5434756585
Revert r77654, it appears to be causing llvm-gcc bootstrap failures, and many
...
failures when building assorted projects with clang.
--- Reverse-merging r77654 into '.':
U include/llvm/CodeGen/Passes.h
U include/llvm/CodeGen/MachineFunctionPass.h
U include/llvm/CodeGen/MachineFunction.h
U include/llvm/CodeGen/LazyLiveness.h
U include/llvm/CodeGen/SelectionDAGISel.h
D include/llvm/CodeGen/MachineFunctionAnalysis.h
U include/llvm/Function.h
U lib/Target/CellSPU/SPUISelDAGToDAG.cpp
U lib/Target/PowerPC/PPCISelDAGToDAG.cpp
U lib/CodeGen/LLVMTargetMachine.cpp
U lib/CodeGen/MachineVerifier.cpp
U lib/CodeGen/MachineFunction.cpp
U lib/CodeGen/PrologEpilogInserter.cpp
U lib/CodeGen/MachineLoopInfo.cpp
U lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
D lib/CodeGen/MachineFunctionAnalysis.cpp
D lib/CodeGen/MachineFunctionPass.cpp
U lib/CodeGen/LiveVariables.cpp
llvm-svn: 77661
2009-07-31 03:02:41 +00:00
b6d6aa2d22
llvm-mc: Match a few X86 instructions.
...
- This is "experimental" code, I am feeling my way around and working out the
best way to do things (and learning tblgen in the process). Comments welcome,
but keep in mind this stuff will change radically.
- This is enough to match "subb" and friends, but not much else. The next step is to
automatically generate the matchers for individual operands.
llvm-svn: 77657
2009-07-31 02:32:59 +00:00
bcb44baa57
Manage MachineFunctions with an analysis Pass instead of the Annotable
...
mechanism. To support this, make MachineFunctionPass a little more
complete.
llvm-svn: 77654
2009-07-31 01:52:50 +00:00
5811ab5cf3
When fp is not eliminated, instructions with T2_i12 modes will be changed to T2_i8 ones. Take that into consideration when determining stack size limit for reserving register scavenging slot.
...
llvm-svn: 77642
2009-07-30 23:29:25 +00:00
5aae45fb6f
Remove redundant match for frame index from imm8 addrmode, it is handled by the imm12 addrmode.
...
llvm-svn: 77632
2009-07-30 22:45:52 +00:00
0bfc8312c2
Darwin assembler now recognizes "orn", so remove workaround.
...
llvm-svn: 77627
2009-07-30 21:51:41 +00:00
ce774e2383
Darwin assembler now supports "rrx", so remove workaround.
...
llvm-svn: 77625
2009-07-30 21:38:40 +00:00
79c079b478
Cleanup and include code selection for some frame index cases.
...
llvm-svn: 77622
2009-07-30 18:56:48 +00:00
cab137d294
Add missing D* register clobbers for Thumb-2 call.
...
llvm-svn: 77611
2009-07-30 18:01:09 +00:00
703edcc553
Minor whitespace tidiness.
...
llvm-svn: 77602
2009-07-30 17:04:07 +00:00
013f007762
Rename GRAD to GR32_AD, to follow the naming convention of other
...
classes. And define its SubRegClassList.
llvm-svn: 77601
2009-07-30 17:02:08 +00:00
c667b60b93
add a random codegen deficiency.
...
llvm-svn: 77598
2009-07-30 16:08:58 +00:00
92df9c3323
Add a note.
...
llvm-svn: 77584
2009-07-30 08:56:19 +00:00
e62288fdd4
Optimize some common usage patterns of atomic built-ins __sync_add_and_fetch() and __sync_sub_and_fetch.
...
When the return value is not used (i.e. only care about the value in the memory), x86 does not have to use add to implement these. Instead, it can use add, sub, inc, dec instructions with the "lock" prefix.
This is currently implemented using a bit of instruction selection trick. The issue is the target independent pattern produces one output and a chain and we want to map it into one that just output a chain. The current trick is to select it into a merge_values with the first definition being an implicit_def. The proper solution is to add new ISD opcodes for the no-output variant. DAG combiner can then transform the node before it gets to target node selection.
Problem #2 is we are adding a whole bunch of x86 atomic instructions when in fact these instructions are identical to the non-lock versions. We need a way to add target specific information to target nodes and have this information carried over to machine instructions. Asm printer (or JIT) can use this information to add the "lock" prefix.
llvm-svn: 77582
2009-07-30 08:33:02 +00:00
6afdc5e694
Switch obvious clients to Twine instead of utostr (when they were already using
...
a Twine, e.g., for names).
- I am a little ambivalent about this; we don't want the string conversion of
utostr, but using overload '+' mixed with string and integer arguments is
sketchy. On the other hand, this particular usage is something of an idiom.
llvm-svn: 77579
2009-07-30 04:20:37 +00:00
8787861004
Keep track of references to mem(cpy,move,set) and then print only one extern
...
declaration for them.
llvm-svn: 77578
2009-07-30 04:15:15 +00:00
49a6f16b7c
Add a new register class to describe operands that can't be SP,
...
due to x86 encoding restrictions. This is currently off by default
because it may cause code quality regressions. This is for PR4572.
llvm-svn: 77565
2009-07-30 01:56:29 +00:00
652529ec9c
Eliminate a bunch of redundant tables.
...
llvm-svn: 77558
2009-07-30 00:40:42 +00:00
0dbdec8042
Lower a 128-bit BUILD_VECTOR with 2 elements to a pair of INSERT_VECTOR_ELTs.
...
llvm-svn: 77557
2009-07-30 00:31:25 +00:00
da9ba9ec2c
Use array_endof instead of doing it manually.
...
llvm-svn: 77553
2009-07-30 00:10:18 +00:00
e3493a91cc
tbb / tbh instructions only branch forward, not backwards.
...
llvm-svn: 77522
2009-07-29 23:20:20 +00:00
1f58eed638
Add VFP3 D registers to the DPR register class.
...
llvm-svn: 77521
2009-07-29 23:03:41 +00:00
4056ca9568
Move types back to the 2.5 API.
...
llvm-svn: 77516
2009-07-29 22:17:13 +00:00
7667332899
inline the global 'getInstrOperandRegClass' function into its callers
...
now that TargetOperandInfo does the heavy lifting.
llvm-svn: 77508
2009-07-29 21:36:49 +00:00
175bd14967
Make sure Thumb2 uses the right call instructions.
...
llvm-svn: 77507
2009-07-29 21:26:42 +00:00
f3239532cc
1. Introduce a new TargetOperandInfo::getRegClass() helper method
...
and convert code to using it, instead of having lots of things
poke the isLookupPtrRegClass() method directly.
2. Make PointerLikeRegClass contain a 'kind' int, and store it in
the existing regclass field of TargetOperandInfo when the
isLookupPtrRegClass() predicate is set. Make getRegClass pass
this into TargetRegisterInfo::getPointerRegClass(), allowing
targets to have multiple ptr_rc things.
llvm-svn: 77504
2009-07-29 21:10:12 +00:00
ee68a483ec
Give getPointerRegClass() a "kind" value so that targets can
...
support multiple different pointer register classes.
llvm-svn: 77501
2009-07-29 20:31:52 +00:00
0d98d8b8b3
- Fix an obvious copy and paste error.
...
- Darwin Thumb2 call clobbers r9.
llvm-svn: 77500
2009-07-29 20:10:36 +00:00
77268a56ff
Add llvm_unreachable for ... unreachable code!
...
llvm-svn: 77480
2009-07-29 18:14:04 +00:00
cf19885a32
Change Neon VLDn intrinsics to return multiple values instead of really
...
wide vectors. Likewise, change VSTn intrinsics to take separate arguments
for each vector in a multi-vector struct. Adjust tests accordingly.
llvm-svn: 77468
2009-07-29 16:39:22 +00:00
4eb9df073d
more syntactic cleanups.
...
llvm-svn: 77442
2009-07-29 06:33:53 +00:00
5e6e022770
minor smallvector cleanups
...
llvm-svn: 77441
2009-07-29 06:29:53 +00:00
6b6dbb3bd8
whitespace cleanup.
...
llvm-svn: 77438
2009-07-29 05:48:09 +00:00
e033e6da08
mingw uses .data and .text, not _data and _text.
...
llvm-svn: 77435
2009-07-29 05:25:42 +00:00
c5397abb52
fix PR4584 with a trivial patch now that the pieces are in place.
...
llvm-svn: 77434
2009-07-29 05:20:33 +00:00
5034329f8d
pass the mangler down into the various SectionForGlobal methods.
...
No functionality change.
llvm-svn: 77432
2009-07-29 05:09:30 +00:00
8f35574c06
constant prop a utostr.
...
llvm-svn: 77430
2009-07-29 04:55:08 +00:00
7610c57d4b
remove some completely wrong code. 1 is never < 16. It turns out that GCC appears to put strings of any length into the ELF cstring equivalent, so just rip out the code.
...
llvm-svn: 77429
2009-07-29 04:54:38 +00:00
c6d70ae063
Optimize Thumb2 jumptable to use tbb / tbh when all the offsets fit in byte / halfword.
...
llvm-svn: 77422
2009-07-29 02:18:14 +00:00
99f5534296
Fix comment.
...
llvm-svn: 77415
2009-07-29 01:01:19 +00:00
bef0437d61
Change the "PreferredEHDataFormat" from "absptr" if we're on a Darwin system >
...
Leopard.
llvm-svn: 77414
2009-07-29 00:59:34 +00:00
f7802a33ce
Add support for gcc __builtin_ia32_ptest{z,c,nzc} intrinsics. Lower
...
to ptest instruction plus setcc. Revamp ptest instruction. Add test.
llvm-svn: 77407
2009-07-29 00:28:05 +00:00
0033199c50
Match X86 register names to number.
...
llvm-svn: 77404
2009-07-29 00:02:19 +00:00
0830980141
Thumb-2: fix typo that caused incorrect stack elimination for VFP operations and very large stack frames.
...
llvm-svn: 77401
2009-07-28 23:52:33 +00:00
e1fdb0e8ce
Move X86 instruction parsing into X86/AsmParser.
...
llvm-svn: 77384
2009-07-28 22:40:46 +00:00
26cf1e3baf
Output the correct format for Darwin.
...
llvm-svn: 77376
2009-07-28 22:03:50 +00:00
403990ad58
Darwin outputs (DW_EH_PE_pcrel | DW_EH_PE_indirect | DW_EH_PE_sdata4) when we're
...
dealing with Data.
llvm-svn: 77372
2009-07-28 21:53:17 +00:00
a4f43fb5dd
Rename MDNode.h header. It defines MDnode and other metadata classes.
...
New name is Metadata.h.
llvm-svn: 77370
2009-07-28 21:49:47 +00:00
4aa3295a65
Return ConstantVector to 2.5 API.
...
llvm-svn: 77366
2009-07-28 21:19:26 +00:00
c8bed03349
In thumb2 mode, add pc is unpredictable. Use add + mov pc instead (that is until more optimization goes in).
...
llvm-svn: 77364
2009-07-28 20:53:24 +00:00
68bb69d6e3
Remove support for ORN to workaround <rdar://problem/7096522>.
...
llvm-svn: 77363
2009-07-28 20:51:25 +00:00
f59ee96a16
Provide generic MCAsmParser when constructing target specific parsers.
...
llvm-svn: 77362
2009-07-28 20:47:52 +00:00
d6b4b29706
more simplifications and cleanup. :)
...
llvm-svn: 77350
2009-07-28 18:48:43 +00:00
c2c7932c64
Change ConstantArray to 2.5 API.
...
llvm-svn: 77347
2009-07-28 18:32:17 +00:00
865c6298d7
Add workaround for <rdar://problem/7098328>.
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llvm-svn: 77340
2009-07-28 18:15:38 +00:00
513a36b63d
Fix PR4639, a ELF-TLS regression from some of my refactoring.
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llvm-svn: 77336
2009-07-28 17:57:51 +00:00
a3242e93b7
the apple "ld_classic" linker doesn't support .literal16 in 32-bit
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mode, and "ld64" (the default linker) falls back to it in -static
mode.
llvm-svn: 77334
2009-07-28 17:50:28 +00:00
e82862e24e
Add Thumb-2 patterns for ARMsrl_flag and ARMsra_flag.
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llvm-svn: 77329
2009-07-28 17:06:49 +00:00
795b63fb65
fix unused variable warning
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llvm-svn: 77326
2009-07-28 16:49:19 +00:00
12da273f90
tADDrSPI doesn't have a predicate operand, but tADDhirr and tADDi3 have.
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llvm-svn: 77305
2009-07-28 07:38:35 +00:00
73a5119675
Code clean up. No functionality changes.
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llvm-svn: 77301
2009-07-28 06:24:12 +00:00
780748d565
- More refactoring. This gets rid of all of the getOpcode calls.
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- This change also makes it possible to switch between ARM / Thumb on a
per-function basis.
- Fixed thumb2 routine which expand reg + arbitrary immediate. It was using
using ARM so_imm logic.
- Use movw and movt to do reg + imm when profitable.
- Other code clean ups and minor optimizations.
llvm-svn: 77300
2009-07-28 05:48:47 +00:00
e1a70c964f
fix a casting problem on the llvm-x86_64-linux tester
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llvm-svn: 77295
2009-07-28 03:20:34 +00:00
5e693ed07b
Rip all of the global variable lowering logic out of TargetAsmInfo. Since
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it is highly specific to the object file that will be generated in the end,
this introduces a new TargetLoweringObjectFile interface that is implemented
for each of ELF/MachO/COFF/Alpha/PIC16 and XCore.
Though still is still a brutal and ugly refactoring, this is a major step
towards goodness.
This patch also:
1. fixes a bunch of dangling pointer problems in the PIC16 backend.
2. disables the TargetLowering copy ctor which PIC16 was accidentally using.
3. gets us closer to xcore having its own crazy target section flags and
pic16 not having to shadow sections with its own objects.
4. fixes wierdness where ELF targets would set CStringSection but not
CStringSection_. Factor the code better.
5. fixes some bugs in string lowering on ELF targets.
llvm-svn: 77294
2009-07-28 03:13:23 +00:00
697150ec0c
don't copy TargetLowering.
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llvm-svn: 77293
2009-07-28 03:05:40 +00:00
57b51d9f82
ORN does not require (and can not have) the ".w" suffix. "Orthogonality" is a dirty word at ARM.
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llvm-svn: 77275
2009-07-27 23:34:12 +00:00
52d03b252e
llvm-mc: Move AsmLexer::getCurStrVal to StringRef based API.
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- My DFS traversal of LLVM is, at least for now, nearly complete! :)
llvm-svn: 77258
2009-07-27 21:49:56 +00:00
9d0e762c81
hoist MCContext/MCStreamer up to AsmPrinter since we're going to start creating
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MCSections soon instead of Section for all targets, and we need something to
own them.
llvm-svn: 77252
2009-07-27 21:28:04 +00:00
69c464dec4
Move ConstantFP construction back to the 2.5-ish API.
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llvm-svn: 77247
2009-07-27 20:59:43 +00:00
e5b969f6a6
Remove TPat. No patterns depend on just isThumb(). Must use either T1Pat (isThumb1Only()) or T2Pat (is Thumb2).
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llvm-svn: 77242
2009-07-27 19:59:26 +00:00
e7cb8f7987
Sink getSectionPrefixForUniqueGlobal down into the TAI
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implementations that need it, rearrange ELFTAI.
llvm-svn: 77236
2009-07-27 19:14:14 +00:00
375a01c34a
remove dead code.
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llvm-svn: 77233
2009-07-27 19:00:33 +00:00
38b7eee164
More DCE.
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llvm-svn: 77231
2009-07-27 18:48:45 +00:00
0e075e2429
convertToThreeAddress can't handle Thumb2 instructions (which don't have same address mode as ARM instructions).
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llvm-svn: 77230
2009-07-27 18:44:00 +00:00
18688f431d
Get rid of more dead code.
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llvm-svn: 77227
2009-07-27 18:38:54 +00:00
239ed4b343
Cosmetic change.
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llvm-svn: 77222
2009-07-27 18:31:40 +00:00
8f2ed1bc5a
Clean up.
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llvm-svn: 77221
2009-07-27 18:25:24 +00:00
056c669e93
Get rid of some more getOpcode calls.
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This also fixes potential problems in ARMBaseInstrInfo routines not recognizing thumb1 instructions when 32-bit and 16-bit instructions mix.
llvm-svn: 77218
2009-07-27 18:20:05 +00:00
447a8f29ef
Fix build.
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llvm-svn: 77217
2009-07-27 18:18:30 +00:00
96b3d4a2f9
Remove duplicate entries while printing decls for external symbols.
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Some libcall names are same, so they were getting printed twice.
llvm-svn: 77215
2009-07-27 18:04:34 +00:00
e48c85fa8b
add an explanatory comment about why we drop these in readonly and
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not in mergable
llvm-svn: 77210
2009-07-27 17:39:40 +00:00
1814e81e17
make COFF work like ELF and macho, by splitting out into its own
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header even though there is only one COFF target.
llvm-svn: 77204
2009-07-27 16:45:59 +00:00
ff1f401f9b
don't create default text/data sections for all targets.
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llvm-svn: 77203
2009-07-27 16:44:04 +00:00
e25817a138
Apparently alpha doesn't use ElfTargetAsmInfo (?)
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llvm-svn: 77202
2009-07-27 16:42:14 +00:00
007031d1b4
Thumb-2 does not have RSC.
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llvm-svn: 77201
2009-07-27 16:39:05 +00:00
782f242fd7
Add ".w" suffix for wide thumb-2 instructions.
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llvm-svn: 77199
2009-07-27 16:31:55 +00:00
543c83e8f2
inline a method.
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llvm-svn: 77198
2009-07-27 16:27:32 +00:00
3679ad5a77
apparently we have "windows" and "coff", which are different(?)
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llvm-svn: 77197
2009-07-27 16:22:39 +00:00
c51f3394f3
sink text/data section creation down into the target-specific places that
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should know about them. PECoff doesn't share these, and I want all sections
to be created by object-file-specific code.
llvm-svn: 77196
2009-07-27 16:20:58 +00:00
469ae8ac54
32-bit darwin targets support .literal16 too.
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llvm-svn: 77191
2009-07-27 15:44:04 +00:00
86b7255776
Eliminate getNamed/getUnnamedSection, adding a new and unified getOrCreateSection
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instead.
llvm-svn: 77186
2009-07-27 06:17:14 +00:00
149465ea06
Eliminate SectionFlags, just embed a SectionKind into Section
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instead and drive things based off of that.
llvm-svn: 77184
2009-07-27 05:32:16 +00:00
371ec9e810
If CPSR is modified but the def is dead, then it's ok to fold the load / store.
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llvm-svn: 77182
2009-07-27 04:18:04 +00:00
c47e109335
Use t2LDRi12 and t2STRi12 to load / store to / from stack frames. Eliminate more getOpcode calls.
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llvm-svn: 77181
2009-07-27 03:14:20 +00:00
c8885129d8
Generate a libcall for i8 multiply.
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llvm-svn: 77179
2009-07-27 02:44:46 +00:00
e334b34bfd
fixed incorrect lowering of ISD::SUB node. SUB has only one result value.
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It wasn't caught during tests because we never got a sub generated, (i8 was always getting promoted to int, which in turn was broken into subc/sube). Though the optimizer leaves an i8 sub now.
llvm-svn: 77178
2009-07-27 02:26:06 +00:00
186332f898
Use the right instructions to copy between GPR and the more strictive tGPR classes. t2MOV does not match the RC requirements.
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llvm-svn: 77175
2009-07-27 00:33:08 +00:00
0e5b149930
Merge isLoadFromStackSlot into one since it behaves the same regardless of sub-target.
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llvm-svn: 77174
2009-07-27 00:24:36 +00:00
26b51b15ed
Just use a single isMoveInstr to catch all the cases.
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llvm-svn: 77173
2009-07-27 00:05:15 +00:00
faede73a32
Rename tMOVhi2lor to tMOVgpr2tgpr. It's not moving from a high register to a low register. It's moving from a GPR register class to a more restrictive tGPR class. Also change tMOVlor2hir, and tMOVhir2hir.
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llvm-svn: 77172
2009-07-26 23:59:01 +00:00
602d44fa70
untangle a TargetAsmInfo hack where ELFTargetAsmInfo would create a
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'unnamed' bss section, but some impls would want a named one. Since
they don't have consistent behavior, just make each target do their
own thing, instead of doing something "sortof common" then having
targets change immutable objects later.
llvm-svn: 77165
2009-07-26 19:23:28 +00:00
8953720f23
Refactor. Get rid of a few more getOpcode() calls.
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llvm-svn: 77164
2009-07-26 18:55:14 +00:00
06ad4948f5
reduce indentation
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llvm-svn: 77161
2009-07-26 18:08:15 +00:00
fc4d4994ee
Fix the breakage caused by 76950.
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PIC16 has special naming conventions for variables having section names specified via section attribute.
llvm-svn: 77153
2009-07-26 10:25:01 +00:00
ec7ec7c1ac
Move MSILModule and MSILWriter into the 'llvm' namespace, instead of the 'MSIL'
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namespace which could very well conflict with non-LLVM code.
Also clean up some spacing, remove an extra header.
llvm-svn: 77146
2009-07-26 08:16:51 +00:00
9813b0b025
Eliminate some uses of DOUT, cerr, and getNameStart().
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llvm-svn: 77145
2009-07-26 07:49:05 +00:00
1db210322a
remove a densemap from TargetAsmInfo that was uniquing the targetflags strings,
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just use a smallstring instead.
llvm-svn: 77144
2009-07-26 07:33:58 +00:00
d2e0220cb4
simplify SectionFlagsForGlobal, even though I want to kill it.
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llvm-svn: 77143
2009-07-26 07:17:39 +00:00
9db3a9286d
make SectionKind keep track of whether a global had an explicit
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section specified for it or not.
llvm-svn: 77142
2009-07-26 07:14:28 +00:00
d9951203f0
simplify this code now that SectionKind knows if a global is weak or not.
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llvm-svn: 77141
2009-07-26 07:07:01 +00:00
e45ff5cc2b
make SectionKind know whether a symbol is weak or not in addition
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to its classification.
llvm-svn: 77140
2009-07-26 07:00:12 +00:00
29151b0218
rename Mergable -> Mergeable and Writable -> Writeable
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llvm-svn: 77138
2009-07-26 06:48:26 +00:00
2d7270d577
remove a bunch of helper functions, just use SectionKind::get instead.
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llvm-svn: 77135
2009-07-26 06:34:33 +00:00
fb6867c7db
simplify getSectionForMergableConstant to take a SectionKind.
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llvm-svn: 77134
2009-07-26 06:26:55 +00:00
aae21f4915
precreate 4/8/16 byte mergable sections to simplify code.
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llvm-svn: 77133
2009-07-26 06:16:11 +00:00
911e2b8649
introduce specialized mergable const sectionkinds for elements of size 4/8/16 to
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simplify targets.
llvm-svn: 77132
2009-07-26 06:11:33 +00:00
6194637d66
improve the default impl of getSectionForMergableConstant by
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putting readonly constants in the readonly section if we have one.
llvm-svn: 77131
2009-07-26 05:57:07 +00:00
1e76db06b9
make elf targets correctly handle constant pool entries that require relocations.
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llvm-svn: 77130
2009-07-26 05:55:20 +00:00
1d68bd7f97
Rearrange all the SectionKinds and structure them into a hierarchical
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group instead of a bunch of random unrelated ideas. Provide predicates
to categorize a SectionKind into a group, and use them instead of
getKind() throughout the code.
This also renames a ton of SectionKinds to be more consistent and
evocative, and adds a huge number of comments on the enums so that
I will hopefully be able to remember how this stuff works long from
now.
llvm-svn: 77129
2009-07-26 05:44:20 +00:00
ee01b242e8
Factor commonality in triple match routines into helper template for registering
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classes, and migrate existing targets over.
llvm-svn: 77126
2009-07-26 05:03:33 +00:00
8e58bc9ed4
put normal data into .data instead of .data.rel on elf systems.
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llvm-svn: 77116
2009-07-26 03:06:11 +00:00
bc981d8efa
Kill Target specific ModuleMatchQuality stuff.
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- This was overkill and inconsistently implemented.
llvm-svn: 77114
2009-07-26 02:22:58 +00:00
Dan Gohman