b80734bb15
Fix bug in NEON convert for single-precision FP. This also fixes the tblgen warnings.
...
llvm-svn: 78629
2009-08-11 01:07:38 +00:00
9382d5ac05
Add stdlib.h
...
llvm-svn: 78627
2009-08-11 00:20:00 +00:00
693e36a3e8
SjLj based exception handling unwinding support. This patch is nasty, brutish
...
and short. Well, it's kinda short. Definitely nasty and brutish.
The front-end generates the register/unregister calls into the SjLj runtime,
call-site indices and landing pad dispatch. The back end fills in the LSDA
with the call-site information provided by the front end. Catch blocks are
not yet implemented.
Built on Darwin and verified no llvm-core "make check" regressions.
llvm-svn: 78625
2009-08-11 00:09:57 +00:00
475f8a4fa2
Enable Thumb2 instruction shrinking (32-bit to 16-bit) pass. Convert a bunch of thumb2 tests to FileCheck.
...
llvm-svn: 78622
2009-08-10 23:56:04 +00:00
733a64db57
Fix a bug where DAGCombine was producing an illegal ConstantFP
...
node after legalize, and remove the workaround code from the
ARM backend.
llvm-svn: 78615
2009-08-10 23:15:10 +00:00
53aa7a960c
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type.
...
llvm-svn: 78610
2009-08-10 22:56:29 +00:00
d91dceea0f
Whitespace, 80-column, and isTwoAddress -> Constraints = "" changes.
...
No functional change.
llvm-svn: 78608
2009-08-10 22:37:37 +00:00
85b5b027f7
Use NEON for single-precision int<->FP conversions.
...
llvm-svn: 78604
2009-08-10 22:17:39 +00:00
148e9f0d3f
Do not rely on magic "llvm.dbg.*" global variable name to find debug info.
...
PIC16 developers, please verify.
llvm-svn: 78603
2009-08-10 22:11:20 +00:00
458c91732c
Fix up whitespace, remove commented out code.
...
llvm-svn: 78600
2009-08-10 21:48:58 +00:00
e4f79d140d
llvm-mc/AsmParser: Disambiguate i64i8imm.
...
llvm-svn: 78598
2009-08-10 21:06:41 +00:00
aeb1feb67a
llvm-mc/AsmParser: Allow .td users to redefine the names of the methods to call
...
on target specific operands for testing class membership and converting to
MCInst operands.
llvm-svn: 78597
2009-08-10 21:00:45 +00:00
3e77df2bcd
SimpleValueType-ify a few more methods on TargetLowering.
...
llvm-svn: 78595
2009-08-10 20:46:15 +00:00
f72c13bdf5
Handle the constantfp created during post-legalization dag combiner phase.
...
llvm-svn: 78594
2009-08-10 20:25:59 +00:00
246617857f
Continue the SimpleValueType-ification.
...
llvm-svn: 78593
2009-08-10 20:18:46 +00:00
0afe2cc097
llvm-mc/AsmMatcher: Fix thinko, Mem isn't a subclass of Imm.
...
llvm-svn: 78587
2009-08-10 19:08:02 +00:00
c30530d105
Start moving TargetLowering away from using full MVTs and towards SimpleValueType, which will simplify the privatization of IntegerType in the future.
...
llvm-svn: 78584
2009-08-10 18:56:59 +00:00
17410a4b92
llvm-mc/AsmMatcher: Change assembler parser match classes to their own record
...
structure.
llvm-svn: 78581
2009-08-10 18:41:10 +00:00
6c20391d38
split MachO section handling stuff out to its out .h/.cpp file.
...
llvm-svn: 78576
2009-08-10 18:15:01 +00:00
fbcafd4c6c
arm only needs to emit one .align directive for hidden nlp's, not one
...
per pointer.
llvm-svn: 78574
2009-08-10 18:02:16 +00:00
292472d3d3
make sure that arm nonlazypointers are aligned properly
...
llvm-svn: 78573
2009-08-10 18:01:34 +00:00
ec64b73712
Fix a weird ppc64-specific link error during an llvm-gcc build:
...
ld: bad offset (0x00000091) for lo14 instruction pic-base fix-up in ___popcountdi2 from libgcc/./_popcountsi2_s.o
The problem is that the non lazy symbol pointers need to be 8 byte aligned
on ppc64 and .section doesn't have an implicit alignment like ".non_lazy_symbol_pointer"
does.
llvm-svn: 78572
2009-08-10 17:58:51 +00:00
7b01bf6125
fix some warnings for the MSVC build, by Yonggang Luo!
...
llvm-svn: 78571
2009-08-10 17:35:42 +00:00
62e053b790
Checkpoint scheduling itinerary changes.
...
llvm-svn: 78564
2009-08-10 15:56:13 +00:00
5bb93ce769
Watch out for empty BB.
...
llvm-svn: 78562
2009-08-10 08:10:13 +00:00
8a640ae504
rev, rev16, and revsh do not set CPSR.
...
llvm-svn: 78561
2009-08-10 07:58:45 +00:00
f16a1d5b79
Duh. Most 16-bit Thumb rr instructions are two-address. Fix table.
...
llvm-svn: 78560
2009-08-10 07:20:37 +00:00
1f5bee14a1
CPSR can be livein; transfer predicate operands correctly; tMUL is two-address.
...
llvm-svn: 78559
2009-08-10 06:57:42 +00:00
092b701a2c
Add support for folding loads / stores into 16-bit moves used by Thumb2.
...
llvm-svn: 78558
2009-08-10 06:32:05 +00:00
55c014a9f3
80 col violation.
...
llvm-svn: 78557
2009-08-10 05:51:48 +00:00
f5b73869f2
Use tMOVgpr2gpr instead of t2MOVr.
...
llvm-svn: 78556
2009-08-10 05:49:43 +00:00
51cbd2d6c4
Add support to reduce most of 32-bit Thumb2 arithmetic instructions.
...
llvm-svn: 78550
2009-08-10 02:37:24 +00:00
5b4c308f0c
Always use the 16-bit tMOVgpr2gpr instead of the 32-bit t2MOVr.
...
llvm-svn: 78549
2009-08-10 02:06:53 +00:00
cb307a27bf
Make the big switch: Change MCSectionMachO to represent a section *semantically*
...
instead of syntactically as a string. This means that it keeps track of the
segment, section, flags, etc directly and asmprints them in the right format.
This also includes parsing and validation support for llvm-mc and
"attribute(section)", so we should now start getting errors about invalid
section attributes from the compiler instead of the assembler on darwin.
Still todo:
1) Uniquing of darwin mcsections
2) Move all the Darwin stuff out to MCSectionMachO.[cpp|h]
3) there are a few FIXMEs, for example what is the syntax to get the
S_GB_ZEROFILL segment type?
llvm-svn: 78547
2009-08-10 01:39:42 +00:00
6e046f4291
Use abs64 instead abs; some platforms don't have a 64-bit abs overload. Noticed by Yonggang Luo!
...
llvm-svn: 78543
2009-08-09 22:37:07 +00:00
d461c1c559
Add support to convert 32-bit instructions to 16-bit non-two-address ones.
...
llvm-svn: 78540
2009-08-09 19:17:19 +00:00
8e33cb2de1
llvm-mc/AsmParser: Implement user defined super classes.
...
- We can now discriminate SUB32ri8 from SUB32ri, for example.
llvm-svn: 78530
2009-08-09 07:20:21 +00:00
447c4ab91d
Extend comment on ParserMatchClass .td field, and add some missing
...
classes for X86.
llvm-svn: 78524
2009-08-09 06:00:04 +00:00
c32aa060bd
llvm-mc/AsmParser: Define match classes in the .td file.
...
-2 FIXMEs.
llvm-svn: 78523
2009-08-09 05:18:30 +00:00
591105c540
sink the 'name' and 'isdirective' state out of MCSection into its derived classes.
...
This totally optimizes PIC16 sections by not having an 'isdirective' bit anymore!! ;-)
llvm-svn: 78517
2009-08-08 23:39:42 +00:00
cfed3005e5
Use subclassing to print lane-like immediates (w/o hash) eliminating
...
'no_hash' modifier. Hopefully this will make Daniel happy :)
llvm-svn: 78514
2009-08-08 23:10:41 +00:00
3219d85f16
add a note about dead zero extends.
...
llvm-svn: 78511
2009-08-08 22:46:59 +00:00
1cb9396f4f
1. Make MCSection an abstract class.
...
2. Move section switch printing to MCSection virtual method which takes a
TAI. This eliminates textual formatting stuff from TLOF.
3. Eliminate SwitchToSectionDirective, getSectionFlagsAsString, and
TLOFELF::AtIsCommentChar.
llvm-svn: 78510
2009-08-08 22:41:53 +00:00
7dfa9f2e56
Add crc32 instruction and intrinsics. Add a new class of prefix
...
bytes for F2 0F 38 and propagate. Add a FIXME for a set
of possibilities which correspond to intrinsics already used.
New test.
llvm-svn: 78508
2009-08-08 21:55:08 +00:00
e2dc8a46e9
Add support for READCYCLECOUNTER in Blackfin back-end.
...
llvm-svn: 78506
2009-08-08 21:42:22 +00:00
26cc5b78d0
add new PIC16Section class, this time hopefully not breaking the build :)
...
llvm-svn: 78505
2009-08-08 21:37:01 +00:00
66f4f54e8a
llvm-mc/AsmMatcher: Switch token matching to use the new string matcher.
...
Also, redefined MatchRegisterName to just return the register value or a
sentinel, to simplify the generated code.
llvm-svn: 78504
2009-08-08 21:22:41 +00:00
59410aaea6
Revert r78501, it doesn't build.
...
--- Reverse-merging r78501 into '.':
U lib/Target/PIC16/PIC16TargetObjectFile.cpp
D lib/Target/PIC16/PIC16Section.h
llvm-svn: 78503
2009-08-08 21:12:40 +00:00
4a4e4487fc
make PIC16 create its own custom MCSection.
...
llvm-svn: 78501
2009-08-08 20:55:25 +00:00
245fdfb9c3
make target-specific TLOF impls (except PIC16) create target-specific
...
MCSection instances.
llvm-svn: 78500
2009-08-08 20:52:13 +00:00
c9ea8fddb2
eliminate TargetLoweringObjectFileSparc in favor of a TAI hook.
...
A TAI hook is appropriate in this case because this is just an
asm syntax issue, not a semantic difference. TLOF should model
the semantics of the section.
llvm-svn: 78498
2009-08-08 20:43:12 +00:00
36d04ec972
give pic16 a target-specific section creation name too
...
llvm-svn: 78496
2009-08-08 20:23:47 +00:00
ce7d14032b
now that getOrCreateSection is all object-file specific,
...
give the impls an object-file-specific name. In the future
they can take different arguments etc.
llvm-svn: 78495
2009-08-08 20:22:20 +00:00
302041d5c9
sink getOrCreateSection down into all the object file implementations,
...
now that they create *all* the sections.
llvm-svn: 78494
2009-08-08 20:14:13 +00:00
f6448f57e6
Use reloc_absolute_word_sext relocation for X86::MOV64(ri/mi)32 instructions,
...
since they are in 64 bit mode with i64immSExt32 imms. JIT is not affected since
it handles both word absolute relocations in the same way
llvm-svn: 78479
2009-08-08 17:47:41 +00:00
028f6dc4c2
Update CMake
...
llvm-svn: 78475
2009-08-08 17:03:13 +00:00
7167f33872
Add insert_elt / extract_elt patterns for v4f32 stuff.
...
Did anyone tests v4f32 ever?
llvm-svn: 78470
2009-08-08 14:06:07 +00:00
4218516f5d
Lane number should be printed w/o hash
...
llvm-svn: 78469
2009-08-08 14:05:53 +00:00
887d05ce9b
Use VLDM / VSTM to spill/reload 128-bit Neon registers
...
llvm-svn: 78468
2009-08-08 13:35:48 +00:00
e372826523
move this fp select into a pattern
...
llvm-svn: 78464
2009-08-08 12:49:07 +00:00
541efcc5c4
llvm-mc/AsmMatcher: Improve match code.
...
- This doesn't actually improve the algorithm (its still linear), but the
generated (match) code is now fairly compact and table driven. Still need a
generic string matcher.
- The table still needs to be compressed, this is quite simple to do and should
shrink it to under 16k.
- This also simplifies and restructures the code to make the match classes more
explicit, in anticipation of resolving ambiguities.
llvm-svn: 78461
2009-08-08 07:50:56 +00:00
e2231070ff
Implement Neon VZIP and VUZP instructions. These are very similar to VTRN,
...
so I generalized the class for VTRN in the .td file to handle all 3 of them.
llvm-svn: 78460
2009-08-08 06:13:25 +00:00
db46af0461
Implement Neon VTRN instructions. For now, anyway, these are selected
...
directly from the intrinsics produced by the frontend. If it is more
convenient to have a custom DAG node for using these to implement shuffles,
we can add that later.
llvm-svn: 78459
2009-08-08 05:53:00 +00:00
1be453b462
Add a skeleton Thumb2 instruction size reduction pass.
...
llvm-svn: 78456
2009-08-08 03:21:23 +00:00
2aa91cc2be
Code refactoring. No functionality change.
...
llvm-svn: 78455
2009-08-08 03:20:32 +00:00
274fcbe43e
tADDhirr should target GPR, not tGPR.
...
llvm-svn: 78454
2009-08-08 03:19:44 +00:00
4dc201eb64
I can type.
...
llvm-svn: 78453
2009-08-08 02:54:37 +00:00
b94284b5e2
make printInstruction return void since its result is omitted. Make the
...
error condition get trapped with an assert.
llvm-svn: 78449
2009-08-08 01:32:19 +00:00
b1692dc267
don't check the result of printInstruction anymore.
...
llvm-svn: 78444
2009-08-08 00:05:42 +00:00
674ffc1e59
Do not generate 32-bit call on win64 when imm does not fit
...
llvm-svn: 78443
2009-08-07 23:59:21 +00:00
742db6a6d4
Make NEON single-precision FP support the default for cortex-a8 (again).
...
llvm-svn: 78430
2009-08-07 23:32:33 +00:00
e35472e3a9
remove a bunch of now-dead crud from the asmprinter and TAI interfaces.
...
llvm-svn: 78428
2009-08-07 23:16:27 +00:00
d28a26dfab
Unbreak the stuff
...
llvm-svn: 78425
2009-08-07 22:51:13 +00:00
a190c169bf
avoid this libcall with long inline expansion
...
llvm-svn: 78420
2009-08-07 22:37:20 +00:00
23b28cb824
2 more vdup.32 cases
...
llvm-svn: 78419
2009-08-07 22:36:50 +00:00
fb93be2b6f
A big oops. Thumb1 default CC is a def of CPSR, not a use of CPSR.
...
llvm-svn: 78418
2009-08-07 22:36:37 +00:00
fe3bdb4b6f
Reformatting of lines. Put multiple DEBUG statements under one DEBUG statement.
...
llvm-svn: 78411
2009-08-07 21:33:25 +00:00
6e130db3b7
Thumb2 32-bit ldm / stm needs .w suffix if submode is ia.
...
llvm-svn: 78410
2009-08-07 21:19:10 +00:00
15b8037034
llvm-mc/AsmMatcher: Tweaks in response to feedback.
...
llvm-svn: 78404
2009-08-07 20:33:39 +00:00
b64ec07ea6
This is done.
...
llvm-svn: 78399
2009-08-07 19:34:52 +00:00
f0237b1aa6
Use 16-bit tMOVgpr2gpr instead of tMOVr to copy GPR registers in Thumb2 mode.
...
llvm-svn: 78398
2009-08-07 19:34:35 +00:00
4c3b1ca5a0
Fix support to use NEON for single precision fp math.
...
llvm-svn: 78397
2009-08-07 19:30:41 +00:00
54c847cd6c
Minor fixes to avoid using invalid debugloc.
...
llvm-svn: 78383
2009-08-07 11:00:02 +00:00
24ee4d0aa4
Simplify code and avoid allocations.
...
llvm-svn: 78382
2009-08-07 10:42:28 +00:00
cf18d6befb
Improve disabling of X86 AsmMatcher.
...
llvm-svn: 78381
2009-08-07 09:06:38 +00:00
32d0bb4c4e
Disable X86 AsmMatcher for now, it is causing gcc-4.0 to run out of memory on
...
i386-apple-darwin9. This presumably will get fixed once the generated code
improves.
llvm-svn: 78379
2009-08-07 08:45:03 +00:00
e10787e710
llvm-mc/AsmMatcher: Move to a slightly more sane matching design.
...
- Still not very sane, but a least its not 60k lines on X86. :)
- In terms of correctness, currently some things are hard wired for X86, and we
still don't properly resolve ambiguities (this is ignoring the instructions
we don't even match due to funny .td stuff or other corner cases).
The high level changes:
1. Represent tokens which are significant for matching explicitly as separate
operands. This uniformly handles not only the instruction mnemonic, but
also 'signficiant' syntax like the '*' in "call * ...".
2. Separate the matching of operands to an instruction from the construction of
the MCInst. In theory this can be done during matching, but since the number
of variations is small I think it makes sense to decompose the problems.
3. Improved a few of the mechanisms to at least successfully flatten / tokenize
the assembly strings for PowerPC and ARM.
4. The comment at the top of AsmMatcherEmitter.cpp explains the approach I'm
moving towards for handling ambiguous instructions. The high-bit is to infer
a partial ordering of the operand classes (and force the user to specify one
if we can't) and use that to resolve ambiguities.
llvm-svn: 78378
2009-08-07 08:26:05 +00:00
82ff022ed2
Error out, rather than infinite looping, if constant island pass can't converge.
...
llvm-svn: 78377
2009-08-07 07:35:21 +00:00
317bd7aab2
tBfar is bl, which clobbers LR.
...
llvm-svn: 78370
2009-08-07 05:45:07 +00:00
003dc1fa5b
Run memsel inserter just before emit assembly to avoid tinkering by other passes.
...
llvm-svn: 78369
2009-08-07 05:44:27 +00:00
a3a3453acf
These should be expanded
...
llvm-svn: 78365
2009-08-07 02:17:44 +00:00
a6d0afcb74
Fix a bunch of namespace pollution.
...
llvm-svn: 78363
2009-08-07 01:32:21 +00:00
b972e5633f
It turns out most of the thumb2 instructions are not allowed to touch SP. The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing.
...
This patch takes pain to ensure all the PEI lowering code does the right thing when lowering frame indices, insert code to manipulate stack pointers, etc. It's also custom lowering dynamic stack alloc into pseudo instructions so we can insert the right instructions at scheduling time.
This fixes PR4659 and PR4682.
llvm-svn: 78361
2009-08-07 00:34:42 +00:00
edfdd07a79
Output the new StructType constructor, which takes the context of the
...
module as first argument.
llvm-svn: 78340
2009-08-06 21:31:35 +00:00
cd4688905f
Use DebugInfoFinder
...
llvm-svn: 78334
2009-08-06 20:53:24 +00:00
0127031c20
Implement Neon VST[234] operations.
...
llvm-svn: 78330
2009-08-06 18:47:44 +00:00
b062c236c5
Add parameter to pattern classes to enable an itinerary to be specified for instructions. For now just use the existing itineraries or NoItinerary.
...
llvm-svn: 78321
2009-08-06 16:52:47 +00:00
1ff90134a4
Fix several fixmes and clean up code by sinking *all* section
...
creation activity into the target-specific subclasses of TLOF.
Before this, globals with explicit sections could be created by
the base class.
1. make getOrCreateSection protected, add a new getExplicitSectionGlobal
pure virtual method to assign sections to globals with a specified
section.
2. eliminate getSpecialCasedSectionGlobals, which is now PIC specific.
3. eliminate the getKindForNamedSection virtual method, which is
now just a static method for ELF.
4. Add implementions of getExplicitSectionGlobal for ELF/PECOFF/Darwin/PIC16.
They are now all detangled and understandable, woo! :)
llvm-svn: 78319
2009-08-06 16:39:58 +00:00
b29996eb23
go through PIC16TargetObjectFile to make sections instead of
...
creating them directly in the pic16 asmprinter.
llvm-svn: 78317
2009-08-06 16:27:28 +00:00
d0439d0638
We need to sext global addresses in kernel code model, not zext
...
llvm-svn: 78299
2009-08-06 11:23:24 +00:00
130e2c7aed
Fix a bug in x86's PreprocessForRMW logic that was exposed
...
by aggressive chain operand optimization. UpdateNodeOperands
does not modify the node in place if it would result in
a node identical to an existing node.
llvm-svn: 78297
2009-08-06 09:22:57 +00:00
82db9891fa
Missed part of recent kernel codemodel tweaks
...
llvm-svn: 78293
2009-08-06 09:11:19 +00:00
488db94e7b
Neon does not actually have VLD{234}.64 instructions.
...
These operations will have to be synthesized from other instructions.
llvm-svn: 78263
2009-08-06 00:24:27 +00:00
e148ceaf65
Add a new pre-allocation pass to assign adjacent registers for Neon instructions
...
that have that constraint. This is currently just assigning a fixed set of
registers, and it only handles VLDn for n=2,3,4 with DPR registers.
I'm going to expand it to handle more operations next; we can make it smarter
once everything is working correctly.
llvm-svn: 78256
2009-08-05 23:12:45 +00:00
741ea0d7fd
Better handle kernel code model. Also, generalize the things and fix one
...
subtle bug with small code model.
llvm-svn: 78255
2009-08-05 23:01:26 +00:00
77f33b71c7
Use GR32 for copies between GR32_NOSP and GR32_NOREX, as neither
...
is a subset of the other, but both are subsets of GR32.
llvm-svn: 78250
2009-08-05 22:18:26 +00:00
e5b5d8fbb3
When using NEON for single-precision FP, the NEON result must be placed in D0-D15 as these are the only D registers with S subregs. Introduce a new regclass to represent D0-D15 and use it in the NEON single-precision FP patterns.
...
llvm-svn: 78244
2009-08-05 21:02:22 +00:00
39fb546b9e
remove the 'DataSectionStartSuffix' and 'TextSectionStartSuffix' knobs.
...
llvm-svn: 78242
2009-08-05 20:49:52 +00:00
ef98dbe3de
Remove redundand checks: the only way to have, e.g. f32 RegVT is exactly
...
hardfloat case.
llvm-svn: 78237
2009-08-05 20:15:19 +00:00
87cc2c2dce
hasSuperClass tests for a strict superset relation, rather than
...
a superset relation. This code wants to test the regular superset
relation.
llvm-svn: 78236
2009-08-05 20:13:45 +00:00
ef42862ef5
Unbreak the stuff, this is ugly, but we cannot do better for now with 'plain' C calling conv.
...
llvm-svn: 78232
2009-08-05 19:40:16 +00:00
22ef75155e
Missed pieces for ARM HardFP ABI.
...
Patch by Sandeep Patel!
llvm-svn: 78225
2009-08-05 19:04:42 +00:00
13937d8236
Use elf Object File directly
...
llvm-svn: 78220
2009-08-05 18:13:04 +00:00
4cc1feff4f
Remove some dead code.
...
llvm-svn: 78219
2009-08-05 18:12:37 +00:00
df7ea32af7
Enable the new no-SP register classes by default. This is to address
...
PR4572. A few tests have some minor code regressions due to different
coalescing.
llvm-svn: 78217
2009-08-05 17:40:24 +00:00
9ede773c4e
Remove a redundant declaration.
...
llvm-svn: 78216
2009-08-05 17:39:44 +00:00
be47ccffef
Convert bswap test to filecheck, add more test entries & convert stuff to filecheck
...
llvm-svn: 78212
2009-08-05 16:50:53 +00:00
477fd55c9a
Fix a bug in the PIC16 backend.
...
llvm-svn: 78211
2009-08-05 16:46:43 +00:00
21788bef7c
Disable NEON single-precision FP support for Cortex-A8, for now...
...
llvm-svn: 78209
2009-08-05 16:40:57 +00:00
44c4417812
Remove dead code. MDNode and MDString are not Constant anymore.
...
llvm-svn: 78207
2009-08-05 16:40:02 +00:00
2e627cb37f
Add memory versions of some instructions.
...
Patch by Neale Ferguson!
llvm-svn: 78203
2009-08-05 16:16:11 +00:00
a307edbdd5
By default, for cortex-a8 use NEON for single-precision FP.
...
llvm-svn: 78200
2009-08-05 16:01:19 +00:00
cb781cfe81
Special constants as destinations does not work as expected - drop the patterns.
...
llvm-svn: 78191
2009-08-05 14:42:00 +00:00
ba3a342c89
Alpha: Get section directives right
...
llvm-svn: 78189
2009-08-05 13:59:57 +00:00
de8b1b2e7d
Cleanup in dbg_stoppoint handling in CBE. Patch by Sandeep Patel.
...
llvm-svn: 78182
2009-08-05 09:31:40 +00:00
68d8634871
Minor arm CBE fixes. Patch by Sandeep.
...
llvm-svn: 78181
2009-08-05 09:31:07 +00:00
fe4ce2ae7a
Emit module-level inline asm for CBE.
...
Patch by Sandeep Patel
llvm-svn: 78180
2009-08-05 09:29:56 +00:00
2b1dc9a783
- Remove custom handling of jumptables by the elf writter (this was
...
a dirty hack and isn't need anymore since the last x86 code emitter patch)
- Add a target-dependent modifier to addend calculation
- Use R_X86_64_32S relocation for X86::reloc_absolute_word_sext
- Use getELFSectionFlags whenever possible
- fix getTextSection to use TLOF and emit the right text section
- Handle global emission for static ctors, dtors and Type::PointerTyID
- Some minor fixes
llvm-svn: 78176
2009-08-05 06:57:03 +00:00
e219be7346
80 col violations.
...
llvm-svn: 78175
2009-08-05 06:41:25 +00:00
8c79569853
Teach X86FastISel how to handle CCValAssign::BCvt, which is used for
...
MMX arguments. This fixes PR4684.
llvm-svn: 78163
2009-08-05 05:33:42 +00:00
d055488c72
Clarify common linkage and the requirements on it. Enforce
...
them in the verifier.
llvm-svn: 78160
2009-08-05 05:21:07 +00:00
cbc7b26542
expose SectionKindForGlobal to curious clients, named as
...
getKindForGlobal.
llvm-svn: 78156
2009-08-05 04:25:40 +00:00
85f60cc5a8
Oops. I didn't mean to commit this piece yet.
...
llvm-svn: 78146
2009-08-05 02:47:13 +00:00
f9bbcd1afd
Major calling convention code refactoring.
...
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 01:29:28 +00:00
cbf1e16ad9
Remove an unnecessary flush in the CppBackend's output.
...
llvm-svn: 78138
2009-08-05 01:06:38 +00:00
c6b5e8a5c5
Don't flush the raw_ostream between each MachineFunction. These flush
...
calls were originally put in place because errs() at one time was
not unbuffered, and these print routines are commonly used with errs()
for debugging. However, errs() is now properly unbuffered, so the
flush calls are no longer needed. This significantly reduces the
number of write(2) calls for regular asm printing when there are many
small functions.
llvm-svn: 78137
2009-08-05 00:49:25 +00:00
20f79e321e
Change DAG nodes for Neon VLD2/3/4 operations to return multiple results.
...
Get rid of yesterday's code to fix the register usage during isel.
Select the new DAG nodes to machine instructions. The new pre-alloc pass
to choose adjacent registers for these results is not done, so the
results of this will generally not assemble yet.
llvm-svn: 78136
2009-08-05 00:49:09 +00:00
1b02ceeb41
1) Proper emit displacements for x86, using absolute relocations where necessary
...
for ELF to work.
2) RIP addressing: Use SIB bytes for absolute relocations where RegBase=0,
IndexReg=0.
3) The JIT can get the real address of cstpools and jmptables during
code emission, fix that for object code emission
llvm-svn: 78129
2009-08-05 00:11:21 +00:00
7cc6aca1e6
Fix part 1 of pr4682. PICADD is a 16-bit instruction even in thumb2 mode.
...
llvm-svn: 78126
2009-08-04 23:47:55 +00:00
a8720101b5
Replace dregsingle operand modifier with explicit escaped curly brackets.
...
For other VLDn and VSTn operations, we need to list the multiple registers
explicitly anyway, so there's no point in special-casing this one usage.
llvm-svn: 78109
2009-08-04 21:39:33 +00:00
f2dbd2e205
Restlyize to match other targets, fixes cmake build to boot.
...
llvm-svn: 78105
2009-08-04 21:27:06 +00:00
783b65b546
Enable load / store multiple pass for Thumb2. It's not using ldrd / strd yet.
...
llvm-svn: 78104
2009-08-04 21:12:13 +00:00
cd450bbbe5
remove a random reference to subtarget. Even without this, we
...
still get "intel syntax" instructions from llc with
-x86-asm-syntax=intel
llvm-svn: 78103
2009-08-04 21:12:08 +00:00
30bf625ac2
Add NEON single-precision FP support for fabs and fneg.
...
llvm-svn: 78101
2009-08-04 20:39:05 +00:00
16dc0cd8a2
rip out SectionEndDirectiveSuffix support, only uses by
...
the masm backend. If anyone cares about masm in the future,
we'll have semantic sections it can hang off of.
llvm-svn: 78096
2009-08-04 20:09:41 +00:00
d302ab9961
Most flags are reserved registers on Blackfin.
...
The only exception is CC.
llvm-svn: 78089
2009-08-04 19:16:55 +00:00
a3abe2a7ce
In thumb mode, r7 is used as frame register. This fixes pr4681.
...
llvm-svn: 78086
2009-08-04 18:46:17 +00:00
a3839bc6c0
Match common pattern for FNMAC. Add NEON SP support.
...
llvm-svn: 78085
2009-08-04 18:44:29 +00:00
b4c28d23e1
Legalize i64 store operations generated by inst-combine.
...
llvm-svn: 78082
2009-08-04 17:59:16 +00:00
3b9c52c5c1
Initial support for single-precision FP using NEON. Added "neonfp" attribute to enable. Added patterns for some binary FP operations.
...
llvm-svn: 78081
2009-08-04 17:53:06 +00:00
ed65bf420d
Avoid compiler warning (in -Asserts mode)
...
llvm-svn: 78070
2009-08-04 16:46:12 +00:00
f222054df7
enhance codegen to put 16-bit character strings into the
...
__TEXT,__ustring section on darwin.
llvm-svn: 78068
2009-08-04 16:27:13 +00:00
eee9df0e97
fix a fixme: don't create an explicit "CStringSection" for ELF,
...
it is just being used as a prefix, so forward substitute it directly.
llvm-svn: 78067
2009-08-04 16:19:50 +00:00
81bbf443fe
Add support emiting for 2/4 byte mergable strings to the ".rodata.str*"
...
section on ELF targets.
llvm-svn: 78066
2009-08-04 16:13:09 +00:00
d0a53d380a
Ooops, I was too fast to commit the wrong fix :(
...
llvm-svn: 78060
2009-08-04 11:18:31 +00:00
3c5b68e2a7
Fix a typo - this unbreaks llvm-gcc build on arm
...
llvm-svn: 78059
2009-08-04 11:12:51 +00:00
3870fbb561
Thumb2 does not have ib (increment before) and da (decrement after) forms of ldm / stm.
...
llvm-svn: 78057
2009-08-04 08:34:18 +00:00
b58dc1c667
make MergeableCString be a SectionKind "abstract class", and
...
add new concrete versions for 1/2/4-byte mergable strings.
These are not actually created yet.
llvm-svn: 78055
2009-08-04 05:35:56 +00:00
ad9a6c4855
No really, it's unused.
...
llvm-svn: 78047
2009-08-04 04:08:40 +00:00
09c1d0002b
Remove now unused Module argument to createTargetMachine.
...
llvm-svn: 78043
2009-08-04 04:02:45 +00:00
f43cf709cb
Remove ARM specific getInlineAsmLength. We'll rely on the simpler (and faster) generic algorithm for now. If more accurate computation is needed, we'll rely on the disassembler.
...
llvm-svn: 78032
2009-08-04 01:56:09 +00:00
71756e789b
Load / store multiple pass fixes for Thumb2. Not enabled yet.
...
llvm-svn: 78031
2009-08-04 01:43:45 +00:00
03eb0e3c33
Emit sub r, #c instead of transforming it to add r, #-c if c fits in 8-bit. This is a bit of pre-mature optimization. 8-bit variant makes it likely it will be narrowed to a 16-bit instruction.
...
llvm-svn: 78030
2009-08-04 01:41:15 +00:00
f45dee3ad2
Lower Neon VLD* intrinsics to custom DAG nodes, and manually allocate the
...
results to fixed registers.
llvm-svn: 78025
2009-08-04 00:36:16 +00:00
17f8878114
Minor cleanup. No functional changes intended.
...
llvm-svn: 78024
2009-08-04 00:25:01 +00:00
3ddfff98a0
Update CMake files.
...
llvm-svn: 78020
2009-08-03 23:44:01 +00:00
d033a62ff7
remove an unneeded section switch.
...
llvm-svn: 78014
2009-08-03 23:02:45 +00:00
661710c51d
switch ppc to using SwitchToSection instead of textual section stuff.
...
llvm-svn: 78013
2009-08-03 22:52:21 +00:00
09441faba9
use TLOF to compute the section for a function instead of
...
replicating the logic manually.
llvm-svn: 78011
2009-08-03 22:32:50 +00:00
73ebe435ca
convert macho stub emission to use SwitchToSection instead of
...
textual sections.
llvm-svn: 78007
2009-08-03 22:18:15 +00:00
e7a932d145
hoist some common code out of a switch
...
llvm-svn: 78006
2009-08-03 22:16:57 +00:00
feb01a100b
this really shouldn't switch sections without telling the asmprinter, but
...
hey it uses .previous, so it should work :)
llvm-svn: 78004
2009-08-03 21:57:00 +00:00
d2c179c8f6
Eliminate textual section switching from the x86 backend, one
...
more step towards "semantics sections"
llvm-svn: 78002
2009-08-03 21:53:27 +00:00
f307e0bd6d
Lower CONCAT_VECTOR during legalization instead of matching it during isel.
...
Add a testcase.
llvm-svn: 77992
2009-08-03 20:36:38 +00:00
a73416bd1c
Minor stylistic cleanups in the Blackfin target.
...
Thanks Chris.
llvm-svn: 77987
2009-08-03 19:32:30 +00:00
87a2ebd77d
remove a dead switch directive, replace it with some
...
code that I will be using shortly.
llvm-svn: 77983
2009-08-03 19:10:44 +00:00
3aa1e77572
Remove neverHasSideEffects on MMX_MOVD64rrv164 since it has a matching pattern.
...
llvm-svn: 77978
2009-08-03 18:07:19 +00:00
21f54a7572
eliminate textual section switching from intel asm printer.
...
This will cause it to enter the ".text" section instead of "_text"
but masm is already broken.
llvm-svn: 77977
2009-08-03 18:06:07 +00:00
1b7868ec54
Change C, CBE, MSIL to not provide target data via getTargetData().
...
- The theory is these should never actually be called, since these boil down to
passes which can access the target data via the standard mechanism.
llvm-svn: 77975
2009-08-03 17:40:25 +00:00
c28b306423
llvm_report_error already prints "LLVM ERROR:". So stop reporting errors like "LLVM ERROR: llvm: error:" or "LLVM ERROR: ERROR:".
...
llvm-svn: 77971
2009-08-03 13:33:33 +00:00
f48daf5823
Unbreak win64 compilation callback.
...
Since we're generating stubs by hands we don't follow the ABI and don't
create a register spill area.
Don't use this area in compilation callback!
llvm-svn: 77968
2009-08-03 08:43:36 +00:00
03056efe01
Create proper frame index for FP
...
llvm-svn: 77966
2009-08-03 08:14:30 +00:00
7d80ab1593
Perform bitconvert to proper type
...
llvm-svn: 77965
2009-08-03 08:14:14 +00:00
442beabbf7
Add 'Indirect' LocInfo class and use to pass __m128 on win64. Also minore fixes here and there (mostly __m64).
...
llvm-svn: 77964
2009-08-03 08:13:56 +00:00
72bc3846bc
Cleanup Darwin MMX calling conv stuff - make the stuff more generic. This also fixes a subtle bug, when 6th v1i64 argument passed wrongly.
...
llvm-svn: 77963
2009-08-03 08:13:24 +00:00
71386e08fe
Unbreak Win64 CC. Step one: honour register save area, fix some alignment and provide a different set of call-clobberred registers.
...
llvm-svn: 77962
2009-08-03 08:12:53 +00:00
70e9816624
Use movd instead of movq
...
llvm-svn: 77956
2009-08-03 05:21:05 +00:00
719d235520
Remove now unused arguments from TargetRegistry::lookupTarget.
...
llvm-svn: 77950
2009-08-03 04:20:57 +00:00
97f7dfb862
These are done.
...
llvm-svn: 77949
2009-08-03 04:08:36 +00:00
0f16ea5c30
Pass target triple string in to TargetMachine constructor.
...
This is not just a matter of passing in the target triple from the module;
currently backends are making decisions based on the build and host
architecture. The goal is to migrate to making these decisions based off of the
triple (in conjunction with the feature string). Thus most clients pass in the
target triple, or the host triple if that is empty.
This has one important change in the way behavior of the JIT and llc.
For the JIT, it was previously selecting the Target based on the host
(naturally), but it was setting the target machine features based on the triple
from the module. Now it is setting the target machine features based on the
triple of the host.
For LLC, -march was previously only used to select the target, the target
machine features were initialized from the module's triple (which may have been
empty). Now the target triple is taken from the module, or the host's triple is
used if that is empty. Then the triple is adjusted to match -march.
The take away is that -march for llc is now used in conjunction with the host
triple to initialize the subtarget. If users want more deterministic behavior
from llc, they should use -mtriple, or set the triple in the input module.
llvm-svn: 77946
2009-08-03 04:03:51 +00:00
7bdf4c2cec
Fix the instruction encoding.
...
llvm-svn: 77944
2009-08-03 03:27:05 +00:00
854d34a9fb
Remove a bitcast that was a no-op.
...
Thanks to Eli Friedman for noticing it.
llvm-svn: 77942
2009-08-03 03:00:05 +00:00
18ba271a79
Use movq to move 64 bits in and out of mmx registers.
...
Fixes PR4669
llvm-svn: 77940
2009-08-03 02:45:34 +00:00
8b9deebba3
Use the i12 variant of load / store opcodes if offset is zero. Now we pass all of multisource as well.
...
llvm-svn: 77939
2009-08-03 02:38:06 +00:00
57c11da8df
Remove -disable-mips-abicall and -enable-mips-absolute-call command-line
...
options, which don't appear to be useful. -enable-mips-absolute-call is
completely unused (and unless I'm mistaken, is supposed to have the
same effect that -relocation-model=dynamic-no-pic should have),
and -disable-mips-abicall appears to be effectively a
synonym for -relocation-model=static. Adjust the few users of hasABICall
to checks which seem more appropriate. Update MipsSubtarget,
MipsTargetMachine, and MipselTargetMachine to synchronize with recent
changes.
llvm-svn: 77938
2009-08-03 02:22:28 +00:00
6eecd56efc
- s/DOUT/DEBUG(errs()/g
...
- Tidy up some headers.
llvm-svn: 77929
2009-08-03 00:11:34 +00:00
c3719c36e6
Move most targets TargetMachine constructor to only taking a target triple.
...
- The C, C++, MSIL, and Mips backends still need the module.
llvm-svn: 77927
2009-08-02 23:37:13 +00:00
bbb772ace9
Add extra SEXT pattern.
...
llvm-svn: 77920
2009-08-02 22:45:24 +00:00
d35fbe4595
The x86 jit doesn't generate a def_cfa_offset unwind instruction after the
...
pushes in the function prolog if the function doesn't have any stack space,
i.e. for a prolog like:
0x40011870: push %r15
0x40011872: push %r14
0x40011874: push %rbx
Patch by Zoltan!
llvm-svn: 77919
2009-08-02 22:25:37 +00:00
31b44e8f6c
Normalize Subtarget constructors to take a target triple string instead of
...
Module*.
Also, dropped uses of TargetMachine where unnecessary. The only target which
still takes a TargetMachine& is Mips, I would appreciate it if someone would
normalize this to match other targets.
llvm-svn: 77918
2009-08-02 22:11:08 +00:00
David Goodwin