11fc6f8765
Update the block cloner which fixes bugpoint on code using unwind_to (phew!)
...
and also update the cloning interface's major user, the loop optimizations.
llvm-svn: 48088
2008-03-09 05:24:34 +00:00
5ce9b521d7
Update the inliner and simplifycfg to handle unwind_to.
...
llvm-svn: 48086
2008-03-09 05:10:13 +00:00
cc24104703
Two things. Preserve the unwind_to when splitting a BB.
...
Add the ability to remove just one instance of a BB from a phi node. This fixes
the compile error in the tree now.
llvm-svn: 48085
2008-03-09 05:04:48 +00:00
4d0ed842b1
Prune the unwind_to labels on BBs that don't need them. Another step in the
...
removal of invoke, PR1269.
llvm-svn: 48084
2008-03-09 04:55:16 +00:00
93930dc28c
add a note
...
llvm-svn: 48064
2008-03-09 01:08:22 +00:00
eef374c197
Implement a readme entry, compiling
...
#include <xmmintrin.h>
__m128i doload64(short x) {return _mm_set_epi16(0,0,0,0,0,0,0,1);}
into:
movl $1, %eax
movd %eax, %xmm0
ret
instead of a constant pool load.
llvm-svn: 48063
2008-03-09 01:05:04 +00:00
322c826c9d
Fix two problems in SelectionDAGLegalize::ExpandBUILD_VECTOR's handling
...
of BUILD_VECTORS that only have two unique elements:
1. The previous code was nondeterminstic, because it walked a map in
SDOperand order, which isn't determinstic.
2. The previous code didn't handle the case when one element was undef
very well. Now we ensure that the generated shuffle mask has the
undef vector on the RHS (instead of potentially being on the LHS)
and that any elements that refer to it are themselves undef. This
allows us to compile CodeGen/X86/vec_set-9.ll into:
_test3:
movd %rdi, %xmm0
punpcklqdq %xmm0, %xmm0
ret
instead of:
_test3:
movd %rdi, %xmm1
#IMPLICIT_DEF %xmm0
punpcklqdq %xmm1, %xmm0
ret
... saving a register.
llvm-svn: 48060
2008-03-09 00:29:42 +00:00
a1f25b0020
Teach SD some vector identities, allowing us to compile vec_set-9 into:
...
_test3:
movd %rdi, %xmm1
#IMPLICIT_DEF %xmm0
punpcklqdq %xmm1, %xmm0
ret
instead of:
_test3:
#IMPLICIT_DEF %rax
movd %rax, %xmm0
movd %rdi, %xmm1
punpcklqdq %xmm1, %xmm0
ret
This is still not ideal. There is no reason to two xmm regs.
llvm-svn: 48058
2008-03-08 23:43:36 +00:00
ad58828354
1) Improve comments.
...
2) Don't try to insert an i64 value into the low part of a
vector with movq on an x86-32 target. This allows us to
compile:
__m128i doload64(short x) {return _mm_set_epi16(0,0,0,0,0,0,0,1);}
into:
_doload64:
movaps LCPI1_0, %xmm0
ret
instead of:
_doload64:
subl $28, %esp
movl $0, 4(%esp)
movl $1, (%esp)
movq (%esp), %xmm0
addl $28, %esp
ret
llvm-svn: 48057
2008-03-08 22:59:52 +00:00
8a6ebd23a8
minor simplifications to this code, don't create a dead
...
SCALAR_TO_VECTOR on paths that end up not using it.
llvm-svn: 48056
2008-03-08 22:48:29 +00:00
35adf46967
This one looks easy, add a note.
...
llvm-svn: 48055
2008-03-08 22:32:39 +00:00
a76e23a935
move these to the appropriate file
...
llvm-svn: 48054
2008-03-08 22:28:45 +00:00
35e92c7bea
Not all users of a BB are Instructions any more.
...
llvm-svn: 48047
2008-03-08 07:48:41 +00:00
a53414fd79
Load the symbols first so that the interpreter constructor can find them when
...
it tries to initialize them.
llvm-svn: 48046
2008-03-08 02:49:45 +00:00
39b0ac4e59
Remove unused runPass methods.
...
llvm-svn: 48044
2008-03-08 01:43:56 +00:00
21a8f144a6
More ppc32 byval handling (bug fixes). Things
...
are looking pretty good now.
llvm-svn: 48043
2008-03-08 01:41:42 +00:00
95cf661534
Implement x86 support for @llvm.prefetch. It corresponds to prefetcht{0|1|2} and prefetchnta instructions.
...
llvm-svn: 48042
2008-03-08 00:58:38 +00:00
d2ab5fd713
Add support for calls with i128 return values on ppc64.
...
llvm-svn: 48041
2008-03-08 00:19:12 +00:00
d6951455e4
Something that kills a super-register also
...
kills the sub-register.
llvm-svn: 48038
2008-03-07 23:45:15 +00:00
4e97e94809
Fix a typo. It's causing consumer-typeset to miscompile. Perhaps more.
...
llvm-svn: 48035
2008-03-07 22:39:49 +00:00
968f32ce3d
PPC64 passes arguments of integral type in i64 registers, not i32. Reflect this
...
by promoting smaller integral values (i32 at this point) to i64, then truncating
to get the wanted size.
llvm-svn: 48030
2008-03-07 20:49:02 +00:00
8d2ead2e34
Add support for lowering 128-bit shifts on ppc64.
...
llvm-svn: 48029
2008-03-07 20:36:53 +00:00
bfa252d402
Next bits of PPC byval handling. Basically functional
...
but there are bugs.
llvm-svn: 48028
2008-03-07 20:27:40 +00:00
20b5a2b037
Add support for ppc64 shifts with 7-bit (oversized) shift amount (e.g. PPCshl).
...
llvm-svn: 48027
2008-03-07 20:18:24 +00:00
25ff7e217d
Replace SDT_PPCShiftOp in favor of SDTIntBinOps. This allows it to work
...
with 32 or 64-bit operands/results.
llvm-svn: 48026
2008-03-07 20:13:51 +00:00
39a3221e27
Fixed a register scavenger bug. If a def is re-defining part of a super register, there must be an implicit def of the super-register on the MI.
...
llvm-svn: 48024
2008-03-07 20:12:54 +00:00
780b3ca64b
Update inliner to handle functions that return multiple values.
...
llvm-svn: 48020
2008-03-07 20:06:16 +00:00
c1969de3e9
fix 80 col violations
...
llvm-svn: 48019
2008-03-07 20:05:43 +00:00
3f13b6630a
add a pass that can extract all kinds of global values, not just functions. Update llvm-extract to use it and optionally extract a global variable if you want it too
...
llvm-svn: 48015
2008-03-07 19:51:57 +00:00
e8a3e74b6c
Clarify some important bits
...
llvm-svn: 48010
2008-03-07 18:34:50 +00:00
0074ea3ae7
Small cleanup: propagate thread-localness via generic routine.
...
No functionality change.
llvm-svn: 48009
2008-03-07 18:32:18 +00:00
d4defb00df
mark frem as expand for all legal fp types on x86, regardless of whether
...
we're using SSE or not. This fixes PR2122.
llvm-svn: 48006
2008-03-07 06:36:32 +00:00
55bfd8c3f7
When setting the "unused" info, take into account something like this:
...
%r3<def> = OR %x3<kill>, %x3
We don't want to mark the %r3 as unused even though it's a sub-register of %x3.
llvm-svn: 48003
2008-03-06 23:22:43 +00:00
34173f0a43
80 col violation.
...
llvm-svn: 47998
2008-03-06 17:42:34 +00:00
636ab19205
some more spelling changes
...
llvm-svn: 47996
2008-03-06 10:51:21 +00:00
ad19df0687
fix typos
...
llvm-svn: 47994
2008-03-06 10:36:00 +00:00
a3cb090446
Constant fold SIGN_EXTEND_INREG with ashr not lshr.
...
llvm-svn: 47992
2008-03-06 08:20:51 +00:00
d0b62a1552
Don't try to simplify urem and srem using arithmetic rules that don't work
...
under modulo (overflow). Fixes PR1933.
llvm-svn: 47987
2008-03-06 06:48:30 +00:00
e9b690b7f1
Refine Cell's i64 constant generation code to cover more constants where the
...
upper and lower 32-bits are the same (in addition to 0 and -1 previously.)
llvm-svn: 47985
2008-03-06 04:02:54 +00:00
dcabdb1b38
gcc likes things spelled correctly
...
llvm-svn: 47981
2008-03-05 23:41:37 +00:00
26cabc447c
Skip, for now, callsites where use of sret argument is not dominated by callsite.
...
llvm-svn: 47980
2008-03-05 23:39:23 +00:00
0d235052d1
Next bit of PPC ByVal handling; call-site code seems
...
correct now.
llvm-svn: 47978
2008-03-05 23:31:27 +00:00
2609888f29
Missed patch from my last commit
...
llvm-svn: 47977
2008-03-05 23:21:39 +00:00
e43711d392
Resolve aliases to aliasees, where possible
...
llvm-svn: 47975
2008-03-05 23:08:47 +00:00
24f65c3ab7
Handle functions as targets during linking of aliases as well
...
llvm-svn: 47974
2008-03-05 23:08:16 +00:00
42f56b4838
- Fix support for "special" i64 immediates that can be loaded
...
using IL, ILA, et. al. v2i64 and i64 are now supported by
the select bits (SELB) instruction.
- Add missing comparison operations (testcase forthcoming)
- More multiclass refactoring.
llvm-svn: 47973
2008-03-05 23:02:02 +00:00
dac5fa94ef
Try hard to link aliases. Checks can be too strict by now.
...
llvm-svn: 47968
2008-03-05 22:22:46 +00:00
29b502e0e0
Fix a coalescer bug wrt how dead copy interval is shortened.
...
llvm-svn: 47966
2008-03-05 22:09:42 +00:00
3b1c95f885
Handle 'ret' with multiple values.
...
llvm-svn: 47965
2008-03-05 21:50:24 +00:00
c3d98074a9
Add Hybrid Cycle Detection to Andersen's analysis.
...
Patch by Curtis Dunham.
llvm-svn: 47959
2008-03-05 19:31:47 +00:00
8ee39c61f2
Clarify that CALLSEQ_START..END may not be nested,
...
and add some protection against creating such.
llvm-svn: 47957
2008-03-05 19:14:03 +00:00
7c08a01698
evan implemented this.
...
llvm-svn: 47948
2008-03-05 17:11:51 +00:00
2e13597f9d
Remember the source->dest mapping when copying aliases. This fixes PR2054
...
llvm-svn: 47945
2008-03-05 15:27:21 +00:00
12cee7195f
Clarify the state-of-the-art
...
llvm-svn: 47944
2008-03-05 15:11:00 +00:00
3ea44e4ee9
isTwoAddress = 1 -> Constraints.
...
llvm-svn: 47941
2008-03-05 08:19:16 +00:00
6ec7dc6bea
PSLLWri etc. are two-address instructions.
...
llvm-svn: 47940
2008-03-05 08:11:27 +00:00
2acd0c25f6
add a note
...
llvm-svn: 47939
2008-03-05 07:22:39 +00:00
78e9cab229
Generalize FP constant shrinking optimization to apply to any vt
...
except ppc long double. This allows us to shrink constant pool
entries for x86 long double constants, which in turn allows us to
use flds/fldl instead of fldt.
llvm-svn: 47938
2008-03-05 06:48:13 +00:00
3dc3899007
Improve comment, pass in the original VT so that we can shrink a long double constant
...
all the way to float, not stopping at double.
llvm-svn: 47937
2008-03-05 06:46:58 +00:00
3bd59641ac
Ignore debugging related instructions if they get this far.
...
llvm-svn: 47934
2008-03-05 02:34:36 +00:00
801bfb2cf7
Rather than asserting. Dump out the MI that we are not able to encode and abort.
...
llvm-svn: 47933
2008-03-05 02:08:03 +00:00
da7897c4e1
Codegen support for i128 UINT_TO_FP. This just fixes a
...
bug in r47928 (Int64Ty is the correct type for the constant
pool entry here) and removes the asserts, now that the code
is capable of handling i128.
llvm-svn: 47932
2008-03-05 02:07:31 +00:00
0a62cb44ce
Add a target lowering hook to control whether it's worthwhile to compress fp constant.
...
For x86, if sse2 is available, it's not a good idea since cvtss2sd is slower than a movsd load and it prevents load folding. On x87, it's important to shrink fp constant since fldt is very expensive.
llvm-svn: 47931
2008-03-05 01:30:59 +00:00
357061a74d
64bit CAS on 32bit x86.
...
llvm-svn: 47929
2008-03-05 01:15:49 +00:00
d9d874b0cd
Codegen support for i128 SINT_TO_FP.
...
llvm-svn: 47928
2008-03-05 01:08:17 +00:00
6325446666
Refactor code. Remove duplicated functions that basically do the same thing as
...
findRegisterUseOperandIdx, findRegisterDefOperandIndx. Fix some naming inconsistencies.
llvm-svn: 47927
2008-03-05 00:59:57 +00:00
e516aa1127
Skip functions that return multiple values.
...
llvm-svn: 47924
2008-03-05 00:36:59 +00:00
b3ca38c1d5
Check struct return type first.
...
llvm-svn: 47922
2008-03-05 00:27:05 +00:00
3fcd946c26
Removed spurious EnablePPCRS check.
...
llvm-svn: 47918
2008-03-04 23:27:33 +00:00
85d41a1c44
Move PPC lowering functions into PPCTargetLowering
...
class (cosmetic). First piece of byval implementation;
this doesn't work yet. No functional change.
llvm-svn: 47917
2008-03-04 23:17:14 +00:00
1af20ad336
Use a command-line option to turn register scavenging on/off for PPC.
...
llvm-svn: 47915
2008-03-04 23:13:51 +00:00
ce556d908b
Print types for all ret operands.
...
llvm-svn: 47911
2008-03-04 22:05:14 +00:00
4566d885dd
Use while loop.
...
llvm-svn: 47909
2008-03-04 21:59:49 +00:00
b2fae1d13f
Revert SmallVector ctor variants.
...
llvm-svn: 47908
2008-03-04 21:54:56 +00:00
941ab37ea8
Use cast instead of dyn_cast.
...
Update test to use multiple return value directly, instead of relying on -sretpromotion.
llvm-svn: 47907
2008-03-04 21:45:28 +00:00
ea4cb89d34
Filter nested structs
...
llvm-svn: 47906
2008-03-04 21:32:09 +00:00
841322b32a
Handle multiple return values.
...
llvm-svn: 47904
2008-03-04 21:15:15 +00:00
4fee9f35b5
x86-64 atomics
...
llvm-svn: 47903
2008-03-04 21:13:33 +00:00
28179f764c
Properly populate lists of defined/undefined symbols in presence of aliases
...
llvm-svn: 47900
2008-03-04 20:16:11 +00:00
d72ade3b3b
Add alias with non-external aliasee to the list of exported symbols of the library.
...
llvm-svn: 47899
2008-03-04 20:15:35 +00:00
297ea0de75
Use appropriate index to get the result value.
...
llvm-svn: 47897
2008-03-04 19:22:54 +00:00
748c77f530
Skip sret attribute while preparing attribute list for
...
new function and new call sites.
llvm-svn: 47896
2008-03-04 19:12:58 +00:00
5dc63480db
Add FunctionType ctor variant that takes SmallVector params.
...
llvm-svn: 47895
2008-03-04 18:57:05 +00:00
ed6e4b0b7d
Increment counter that keeps track of total number of sret promoted.
...
llvm-svn: 47892
2008-03-04 17:48:11 +00:00
6bb36e686d
Skip declarations.
...
llvm-svn: 47890
2008-03-04 17:47:06 +00:00
5b69f3fa33
Process externally visible functions also. Later on code generator will do the right thing.
...
llvm-svn: 47889
2008-03-04 17:46:26 +00:00
ecce5af83d
Collect statistics.
...
llvm-svn: 47888
2008-03-04 17:44:37 +00:00
c62c2bb4d0
Some improvements related to the computation of heights, depths of SUnits.
...
The basic idea is that all these algorithms are computing the longest paths from the root node or to the exit node. Therefore the existing implementation that uses and iterative and potentially
exponential algorithm was changed to a well-known graph algorithm based on dynamic programming. It has a linear run-time.
llvm-svn: 47884
2008-03-04 11:19:43 +00:00
38caf77419
Refactor ExpandConstantFP so it can optimize load from constpool of types larger than f64 into extload from smaller types.
...
llvm-svn: 47883
2008-03-04 08:05:30 +00:00
59d58ab8c4
80 column violations.
...
llvm-svn: 47878
2008-03-04 03:20:06 +00:00
2ae707888b
Did I say 'e = getNumOperands()'? I meant --e, of course.
...
llvm-svn: 47875
2008-03-04 00:48:15 +00:00
567d2e5b57
Rename isOperand() to isOperandOf() (and other similar methods). It always confuses me.
...
llvm-svn: 47872
2008-03-04 00:41:45 +00:00
33ff36321e
Remove -always-fold-and-in-test.
...
llvm-svn: 47871
2008-03-04 00:40:35 +00:00
0e541ea730
Miscellaneous clean-ups based on Evan's feedback:
...
- Cleaned up how the prologue-epilogue inserter loops over the instructions.
- Instead of restarting the processing of an instruction if we remove an
implicit kill, just update the end iterator and make sure that the iterator
isn't incremented.
llvm-svn: 47870
2008-03-03 23:57:28 +00:00
e1c4f99549
Misc. APInt-ification in the DAGCombiner.
...
llvm-svn: 47869
2008-03-03 23:51:38 +00:00
10f34077f1
More APInt-ification.
...
llvm-svn: 47868
2008-03-03 23:35:36 +00:00
0e238dc813
Yet more APInt-ification.
...
llvm-svn: 47867
2008-03-03 22:37:52 +00:00
2fa65b7997
More APInt-ification.
...
llvm-svn: 47866
2008-03-03 22:22:56 +00:00
a986eea82f
Add support for lowering i64 SRA_PARTS and friends on x86-64.
...
llvm-svn: 47865
2008-03-03 22:22:09 +00:00
f2bbfa3ba0
More APInt-ification.
...
llvm-svn: 47864
2008-03-03 22:20:46 +00:00
632ea65072
This is the initial check-in for adding register scavenging to PPC. (Currently,
...
PPC-64 doesn't work.) This also lowers the spilling of the CR registers so that
it uses a register other than the default R0 register (the scavenger scrounges
for one). A significant part of this patch fixes how kill information is
handled.
llvm-svn: 47863
2008-03-03 22:19:16 +00:00
7921ad0d67
Go through the machine instruction's operands to make sure that we're not
...
marking both a super- and sub-register as "killed". This removes implicit uses
that are marked as "killed".
llvm-svn: 47862
2008-03-03 22:14:33 +00:00
528083bc28
Make the register scavenger update the bookkeeping values for sub/super
...
registers.
llvm-svn: 47861
2008-03-03 22:12:25 +00:00
4836d58f89
Multiple instructions can be inserted when eliminating frame indexes. We need
...
the register scavenger to process all of those new instructions instead of just
the last one inserted.
llvm-svn: 47860
2008-03-03 22:11:16 +00:00
9d91785987
s/isReturnStruct()/hasStructRetAttr()/g
...
llvm-svn: 47857
2008-03-03 21:46:28 +00:00
83558f9f46
regenerate.
...
llvm-svn: 47849
2008-03-03 18:58:47 +00:00
c6b56c79aa
If a function uses multive values in ret instruction then it
...
is returning a struct value.
llvm-svn: 47848
2008-03-03 18:58:16 +00:00
b0faf89133
Preserve paramater attributes.
...
llvm-svn: 47847
2008-03-03 18:36:03 +00:00
e209be4985
Stub out a Path::GetMainExecutable call to find the path to the
...
main executable of a program. This needs to be implemented on windows.
llvm-svn: 47835
2008-03-03 02:55:43 +00:00
d51372aa96
another random note
...
llvm-svn: 47831
2008-03-02 19:29:42 +00:00
6b0a189225
add a note
...
llvm-svn: 47830
2008-03-02 19:27:34 +00:00
a70df9e2ee
Evan implemented these.
...
llvm-svn: 47828
2008-03-02 18:05:14 +00:00
bd0bb3f07f
Evan implemented this.
...
llvm-svn: 47827
2008-03-02 17:56:29 +00:00
c93b48caeb
add support for lvsl, fixing PR1481
...
llvm-svn: 47825
2008-03-02 08:54:27 +00:00
8fb4c98284
add support for the sse.cmp.* intrinsics, which fixes sse.isamax with the CBE.
...
llvm-svn: 47824
2008-03-02 08:47:13 +00:00
9044719798
refactor intrinsic handling code out into its own method.
...
llvm-svn: 47823
2008-03-02 08:29:41 +00:00
2541f1dac6
fix printing of undef vectors, this fixes "simple" and "build" in UnitTests/Vector.
...
Now they all pass.
llvm-svn: 47820
2008-03-02 08:14:45 +00:00
4c058b39e4
insertelement got the wrong operands.
...
llvm-svn: 47819
2008-03-02 08:10:16 +00:00
051709436e
Several changes:
...
* Simplify handling of byval, making it easier to understand and more
consistent. This fixes PR2065.
* Clean up and simplify handling of GEPs. I can actually understand it now!
* Implement support for GEP'ing into vectors, this fixes
SingleSource/UnitTests/Vector/build2 among others.
llvm-svn: 47818
2008-03-02 08:07:24 +00:00
9140fba6ad
Fix a bug I introduced in constant array and constant vector handling.
...
llvm-svn: 47816
2008-03-02 05:46:57 +00:00
7295bc15a0
implement shufflevector.
...
llvm-svn: 47815
2008-03-02 05:41:07 +00:00
f724e34ddc
Add a new ShuffleVectorInst::getMaskValue method.
...
llvm-svn: 47813
2008-03-02 05:28:33 +00:00
689d830b6d
implement extractelement.
...
llvm-svn: 47812
2008-03-02 03:57:08 +00:00
d9cc003b0d
implement insertelement.
...
llvm-svn: 47811
2008-03-02 03:52:39 +00:00
92d929c21d
respect isSigned for vector types, fixing sdiv of vectors etc.
...
llvm-svn: 47810
2008-03-02 03:41:23 +00:00
fe1083be61
print the attribute in the right place, this fixes function returning vectors.
...
llvm-svn: 47809
2008-03-02 03:39:43 +00:00
d861066d15
vector types are simple types. This fixes div/rem of vectors.
...
llvm-svn: 47807
2008-03-02 03:33:31 +00:00
b104be599a
Print vector types appropriately. This gets basic vector code working
...
(PR1126)
llvm-svn: 47806
2008-03-02 03:29:50 +00:00
c8d974a323
rename PT -> VT for VectorTypes.
...
llvm-svn: 47805
2008-03-02 03:18:46 +00:00
895aef4720
Print i32/i64 integer constants as 1u instead of ((unsigned int)1).
...
Use dyn_cast better.
llvm-svn: 47804
2008-03-02 03:16:38 +00:00
647c6642e7
Move pr717 to here.
...
llvm-svn: 47803
2008-03-02 02:51:40 +00:00
3cc9be0b59
Add an unwind_to field to basic blocks, making them Users instead of Values.
...
This is the first checkin for PR1269, the new EH infrastructure.
llvm-svn: 47802
2008-03-02 02:48:09 +00:00
20bcdba9ca
good catch anton
...
llvm-svn: 47800
2008-03-01 23:18:21 +00:00
f5c90ec12c
make CAS work
...
llvm-svn: 47799
2008-03-01 22:27:48 +00:00
d032c33300
all but CAS working on x86
...
llvm-svn: 47798
2008-03-01 21:52:34 +00:00
7f6e95a973
Print the name, not a pointer.
...
llvm-svn: 47796
2008-03-01 17:20:55 +00:00
0070dd1de3
Add lock prefix support to x86. Also add the instructions necessary for the atomic ops. They are still marked pseudo, since I cannot figure out what format to use, but they are the correct opcode.
...
llvm-svn: 47795
2008-03-01 13:37:02 +00:00
ffe0da0eb2
Fix PR2113 by verifying allocations.
...
llvm-svn: 47792
2008-03-01 09:01:57 +00:00
a683edb2d8
allow specified inline threshold to be negative, as the value is
...
itself sometimes negative.
llvm-svn: 47786
2008-03-01 08:09:51 +00:00
208cc8f1b9
Add MVT::is128BitVector and is64BitVector. Shrink
...
unaligned load/store code using them. Per review
of unaligned load/store vector patch.
llvm-svn: 47782
2008-03-01 03:40:57 +00:00
73bdf043a1
Refactor / clean up code; remove td list scheduler special tie breaker (no real benefit).
...
llvm-svn: 47779
2008-03-01 00:39:47 +00:00
e8ddaba169
Fix cut-n-pasto.
...
llvm-svn: 47777
2008-02-29 23:41:13 +00:00
4eedfd2421
Add pass to promote sret.
...
This pass transforms
%struct._Point = type { i32, i32, i32, i32, i32, i32 }
define internal void @foo(%struct._Point* sret %agg.result)
into
%struct._Point = type { i32, i32, i32, i32, i32, i32 }
define internal %struct._Point @foo()
This pass updates foo() clients appropriately to use
getresult instruction to extract return values.
This pass is not yet ready for prime time.
llvm-svn: 47776
2008-02-29 23:34:08 +00:00
0e8b146152
Use enumeration for preffered EH dwarf encoding reason
...
llvm-svn: 47770
2008-02-29 22:09:08 +00:00
26edb59d97
Don't fill eh frames even though these are text sections.
...
llvm-svn: 47765
2008-02-29 19:36:59 +00:00
811153a551
If we reload a virtual register that's already been assigned, we want to mark
...
that instruction as its "last use". This fixes PR1925.
llvm-svn: 47758
2008-02-29 18:52:01 +00:00
2e26dc8051
Fix PR2112: don't run loop aligner if target doesn't have a TargetLowering object.
...
llvm-svn: 47755
2008-02-29 17:52:15 +00:00
c966cebe93
fix a bug Anders ran into where scalarrepl would crash when promoting
...
a union containing a vector and an array whose elements were smaller than
the vector elements. this means we need to compile the load of the
array elements into an extract element plus a truncate.
llvm-svn: 47752
2008-02-29 07:12:06 +00:00
77205def10
Refactor some code out of ConvertUsesToScalar into their own methods, no
...
functionality change.
llvm-svn: 47751
2008-02-29 07:03:13 +00:00
c612571555
Folding or(fcmp,fcmp) only works if the operands of the fcmps are the same fp type.
...
llvm-svn: 47750
2008-02-29 06:09:11 +00:00
ca7c61e79a
No need for coalescer to update kills. Only copies are coalesced and those instructions will be deleted. Doh.
...
llvm-svn: 47749
2008-02-29 02:50:03 +00:00
88f839944d
Remove redundant #include.
...
llvm-svn: 47748
2008-02-29 02:49:15 +00:00
bd2fa566e4
More APInt-ification.
...
llvm-svn: 47746
2008-02-29 01:47:35 +00:00
837a6dccd7
Use the new convertFromAPInt instead of convertFromZeroExtendedInteger,
...
which allows more of the surrounding arithmetic to be done with APInt
instead of uint64_t.
llvm-svn: 47745
2008-02-29 01:44:25 +00:00
06c45d516d
Use the new convertFromAPInt instead of convertFromZeroExtendedInteger.
...
llvm-svn: 47744
2008-02-29 01:42:52 +00:00
ec6be4a782
Use the new APInt-enabled form of getConstant instead of converting
...
an APInt into a uint64_t to call getConstant.
llvm-svn: 47742
2008-02-29 01:41:59 +00:00
105c1d4106
Add support to APInt for shift and rotate operations with APInt
...
instead of uint32_t for the shift/rotate count operand type.
llvm-svn: 47741
2008-02-29 01:40:47 +00:00
17df4cd397
Use the correct instruction encodings for the 64-bit MMX movd.
...
llvm-svn: 47740
2008-02-29 01:35:12 +00:00
ca24fd9096
Simplify code using convertFromZeroExtendedInteger with an APInt
...
by using the new convertFromAPInt directly.
llvm-svn: 47739
2008-02-29 01:27:13 +00:00
35723eb4f6
Add a method to APFloat to convert directly from APInt.
...
llvm-svn: 47738
2008-02-29 01:26:11 +00:00
95a7be473c
Added option -align-loops=<true/false> to disable loop aligner pass.
...
llvm-svn: 47736
2008-02-28 23:29:57 +00:00
cbde4c2206
Interface of getByValTypeAlignment differed between
...
generic & x86 versions; change generic to follow x86
and improve comments. Add PPC version (not right
for non-Darwin.)
llvm-svn: 47734
2008-02-28 22:31:51 +00:00
09b64a4ed1
Make llvm-ar behave like ar, if you create an empty archive, ar creates an empty archive. llvm-ar would not generate an output file in this case
...
llvm-svn: 47733
2008-02-28 22:24:48 +00:00
714eeb2d55
Initialize TextAlignFillValue. Fix revision 47703.
...
llvm-svn: 47732
2008-02-28 22:14:09 +00:00
9781aee03c
Avoid collisions in value names.
...
llvm-svn: 47725
2008-02-28 20:26:04 +00:00
c4c3de2b52
Fix an assertion message.
...
llvm-svn: 47722
2008-02-28 18:36:51 +00:00
643dce1146
add a note
...
llvm-svn: 47720
2008-02-28 17:21:27 +00:00
f77e6977a0
Fix http://llvm.org/bugs/show_bug.cgi?id=2104 by ordering lexicographically what gets printed. Be const-correct in PrintResults and uninline it too
...
llvm-svn: 47712
2008-02-28 08:38:45 +00:00
507713de08
Set to default: x86 no longer fold and into test if it has more than one use.
...
llvm-svn: 47711
2008-02-28 07:46:38 +00:00
a465bfb87c
Keep track how many commutes are performed by the scheduler.
...
llvm-svn: 47710
2008-02-28 07:40:24 +00:00
e2f55f9fc5
Sparc backend doesn't support debug info yet, mark the nodes as expand. This fixes a crash on
...
test/DebugInfo/funccall.ll
llvm-svn: 47709
2008-02-28 05:54:25 +00:00
9824ffef0c
implement expand for ISD::DECLARE by just deleting it.
...
llvm-svn: 47708
2008-02-28 05:53:40 +00:00
f1444c35e8
Fix CodeGen/Generic/storetrunc-fp.ll on sparc, PR2105
...
llvm-svn: 47707
2008-02-28 05:48:04 +00:00
beb6a5ba4f
fix CodeGen/Generic/2008-01-25-dag-combine-mul.ll on sparc, PR2105
...
llvm-svn: 47706
2008-02-28 05:44:20 +00:00
765be8874d
target-indep codegen memcpy lowering issue.
...
llvm-svn: 47705
2008-02-28 05:34:27 +00:00
83e80cd368
Add a random not very important note
...
llvm-svn: 47704
2008-02-28 04:52:59 +00:00
c799065cc3
Add a quick and dirty "loop aligner pass". x86 uses it to align its loops to 16-byte boundaries.
...
llvm-svn: 47703
2008-02-28 00:43:03 +00:00
93e8b679a3
A few more small things I've run into.
...
llvm-svn: 47702
2008-02-28 00:21:43 +00:00
d73396bef9
EHPreferredDataFormat hook for PPC targets. Looks like Darwin
...
uses the same encoding everywhere. Linux FIXME'ed.
llvm-svn: 47701
2008-02-27 23:49:15 +00:00
a1a6882519
Remove dead code.
...
llvm-svn: 47700
2008-02-27 23:33:51 +00:00
ae24cca0e4
Preparation step for some cleanup/generalization in EH information emission:
...
provide TAI hook for selection of EH data emission format. Currently unused.
llvm-svn: 47699
2008-02-27 23:33:50 +00:00
bf76a08e7c
Handle load/store of misaligned vectors that are the
...
same size as an int type by doing a bitconvert of
load/store of the int type (same algorithm as floating point).
This makes them work for ppc Altivec. There was some
code that purported to handle loads of (some) vectors
by splitting them into two smaller vectors, but getExtLoad
rejects subvector loads, so this could never have worked;
the patch removes it.
llvm-svn: 47696
2008-02-27 22:36:00 +00:00
26854f242e
Don't hard-code the mask size to be 32, which is incorrect on ppc64
...
and was causing aborts with the new APInt changes. This may also be
fixing an obscure ppc64 bug.
llvm-svn: 47692
2008-02-27 21:12:32 +00:00
3d17e4c427
This is done.
...
llvm-svn: 47688
2008-02-27 20:26:32 +00:00
fdc732ab9a
Fix a bug in dead spill slot elimination.
...
llvm-svn: 47687
2008-02-27 19:57:11 +00:00
e5e32ec8f7
Remove the `else', at Evan's insistence.
...
llvm-svn: 47686
2008-02-27 19:44:57 +00:00
ef40c5b204
Add a FIXME about the VECTOR_SHUFFLE evil hack.
...
llvm-svn: 47676
2008-02-27 17:39:13 +00:00
14241b29b2
Emit an error when a library is not found. It is the GNU ld behavior and it is expected by the configure scripts.
...
llvm-svn: 47674
2008-02-27 17:20:32 +00:00
e158a82f26
LegalizeTypes support for EXTRACT_VECTOR_ELT. The
...
approach taken is different to that in LegalizeDAG
when it is a question of expanding or promoting the
result type: for example, if extracting an i64 from
a <2 x i64>, when i64 needs expanding, it bitcasts
the vector to <4 x i32>, extracts the appropriate
two i32's, and uses those for the Lo and Hi parts.
Likewise, when extracting an i16 from a <4 x i16>,
and i16 needs promoting, it bitcasts the vector to
<2 x i32>, extracts the appropriate i32, twiddles
the bits if necessary, and uses that as the promoted
value. This puts more pressure on bitcast legalization,
and I've added the appropriate cases. They needed to
be added anyway since users can generate such bitcasts
too if they want to. Also, when considering various
cases (Legal, Promote, Expand, Scalarize, Split) it is
a pain that expand can correspond to Expand, Scalarize
or Split, so I've changed the LegalizeTypes enum so it
lists those different cases - now Expand only means
splitting a scalar in two.
The code produced is the same as by LegalizeDAG for
all relevant testcases, except for
2007-10-31-extractelement-i64.ll, where the code seems
to have improved (see below; can an expert please tell
me if it is better or not).
Before < vs after >.
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 28(%esp)
< movl (%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 28(%esp)
< movl 8(%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 16(%esp), %eax
< movl %eax, 48(%esp)
< movl 20(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 60(%esp)
< movl (%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 24(%esp), %eax
< movl %eax, 48(%esp)
< movl 28(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 60(%esp)
< movl 8(%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
llvm-svn: 47672
2008-02-27 13:34:40 +00:00
2111bd2e37
LegalizeTypes support for legalizing the mask
...
operand of a VECTOR_SHUFFLE. The mask is a
vector of constant integers. The code in
LegalizeDAG doesn't bother to legalize the
mask, since it's basically just storage for
a bunch of constants, however LegalizeTypes
is more picky. The problem is that there may
not exist any legal vector-of-integers type
with a legal element type, so it is impossible
to create a legal mask! Unless of course you
cheat by creating a BUILD_VECTOR where the
operands have a different type to the element
type of the vector being built... This is
pretty ugly but works - all relevant tests in
the testsuite pass, and produce the same
assembler with and without LegalizeTypes.
llvm-svn: 47670
2008-02-27 13:03:44 +00:00
5d5bc484d0
LegalizeTypes support for INSERT_VECTOR_ELT.
...
llvm-svn: 47669
2008-02-27 10:18:23 +00:00
8ae8e2d50b
Don't track max alignment during stack object allocations since they can be deleted later. Let PEI compute it.
...
llvm-svn: 47668
2008-02-27 10:04:56 +00:00
96658d0189
Support for legalizing MEMBARRIER.
...
llvm-svn: 47667
2008-02-27 08:53:44 +00:00
97925ec704
Final de-tabification.
...
llvm-svn: 47663
2008-02-27 06:33:05 +00:00
6fca938971
Add path separator support, patch by Sam Bishop.
...
llvm-svn: 47662
2008-02-27 06:17:10 +00:00
83263b8cfb
Make X86TargetLowering::LowerSINT_TO_FP return without creating a dead
...
stack slot and store if the SINT_TO_FP is actually legal. This allows
us to compile:
double a(double b) {return (unsigned)b;}
to:
_a:
cvttsd2siq %xmm0, %rax
movl %eax, %eax
cvtsi2sdq %rax, %xmm0
ret
instead of:
_a:
subq $8, %rsp
cvttsd2siq %xmm0, %rax
movl %eax, %eax
cvtsi2sdq %rax, %xmm0
addq $8, %rsp
ret
crazy.
llvm-svn: 47660
2008-02-27 05:57:41 +00:00
5fe95a04f5
this code is correct but strange looking ;-)
...
llvm-svn: 47659
2008-02-27 05:48:44 +00:00
3c7d3d5700
Compile x86-64-and-mask.ll into:
...
_test:
movl %edi, %eax
ret
instead of:
_test:
movl $4294967295, %ecx
movq %rdi, %rax
andq %rcx, %rax
ret
It would be great to write this as a Pat pattern that used subregs
instead of a 'pseudo' instruction, but I don't know how to do that
in td files.
llvm-svn: 47658
2008-02-27 05:47:54 +00:00
6d56368caf
Spiller now remove unused spill slots.
...
llvm-svn: 47657
2008-02-27 03:04:06 +00:00
66272a545b
Teach Legalize how to expand an EXTRACT_ELEMENT.
...
llvm-svn: 47656
2008-02-27 01:52:30 +00:00
f19609abe8
Convert the last remaining users of the non-APInt form of
...
ComputeMaskedBits to use the APInt form, and remove the
non-APInt form.
llvm-svn: 47654
2008-02-27 01:23:58 +00:00
5bc621c680
Add comment.
...
llvm-svn: 47653
2008-02-27 01:20:54 +00:00
3f86109fd1
add a note
...
llvm-svn: 47652
2008-02-27 01:17:20 +00:00
ae2b6fbb8e
Convert SimplifyDemandedMask and ShrinkDemandedConstant to use APInt.
...
Change several cases in SimplifyDemandedMask that don't ever do any
simplifying to reuse the logic in ComputeMaskedBits instead of
duplicating it.
llvm-svn: 47648
2008-02-27 00:25:32 +00:00
0362de154e
regenerate.
...
llvm-svn: 47642
2008-02-26 23:19:08 +00:00
4db58fce82
Add assert.
...
llvm-svn: 47641
2008-02-26 23:17:50 +00:00
d29ed0b122
Fix an issue where GVN had the sizes of the two memcpy's reverse, resulting
...
in an invalid transformation.
llvm-svn: 47639
2008-02-26 23:06:17 +00:00
f287e7dcc6
Add assert to check return type.
...
llvm-svn: 47637
2008-02-26 22:55:21 +00:00
3bfca3e942
Refactor according to Evan's and Anton's suggestions.
...
llvm-svn: 47635
2008-02-26 22:21:54 +00:00
8490c6935b
regenerate
...
llvm-svn: 47634
2008-02-26 22:17:48 +00:00
a58b1c9b6b
Remove unncessary ReturnInst constructors.
...
llvm-svn: 47633
2008-02-26 22:12:58 +00:00
d6bd311506
Use a smallvector for inactiveCounts and initialize it lazily
...
instead of init'ing it maximally to zeros on entry. getFreePhysReg
is pretty hot and only a few elements are typically used. This speeds
up linscan by 5% on 176.gcc.
llvm-svn: 47631
2008-02-26 22:08:41 +00:00
d7a258d325
Rename PrintableName to Name.
...
llvm-svn: 47629
2008-02-26 21:47:57 +00:00
c24ea4fb41
Change "Name" to "AsmName" in the target register info. Gee, a refactoring tool
...
would have been a Godsend here!
llvm-svn: 47625
2008-02-26 21:11:01 +00:00
fa6b366892
Enable -coalescer-commute-instrs by default.
...
llvm-svn: 47623
2008-02-26 20:40:22 +00:00
a736c001b6
Use SmallVector while constructing ReturnInst.
...
llvm-svn: 47619
2008-02-26 19:38:17 +00:00
060e79c729
Avoid const_casts
...
llvm-svn: 47616
2008-02-26 19:15:26 +00:00
aa2617206f
fix http://llvm.org/bugs/show_bug.cgi?id=2097
...
llvm-svn: 47615
2008-02-26 19:13:21 +00:00
85e38bfb2e
Remove unnecessary getOperand/setOperand overriders.
...
Simplify getReturnValue()
llvm-svn: 47614
2008-02-26 19:08:13 +00:00
9db0aa86d9
Avoid aborting on invalid shift counts.
...
llvm-svn: 47612
2008-02-26 18:50:50 +00:00
c38eb52787
Unify to ReturnInst::init() member functions.
...
llvm-svn: 47611
2008-02-26 18:49:29 +00:00
666bbe34f4
Fix for pr2093: direct operands aren't necessarily addresses, so don't
...
try to simplify them.
llvm-svn: 47610
2008-02-26 18:37:49 +00:00
ae682fb940
Optimize most common case by using single RetVal in ReturnInst.
...
llvm-svn: 47607
2008-02-26 17:56:20 +00:00
1f17bf6171
Correct function comments.
...
llvm-svn: 47606
2008-02-26 17:50:59 +00:00
07c83cc86e
Fix PR2096, a regression introduced with my patch last night. This
...
also fixes cfrac, flops, and 175.vpr
llvm-svn: 47605
2008-02-26 17:09:59 +00:00
7cdbbfd067
Fix a nasty bug in LegalizeTypes (spotted in
...
CodeGen/PowerPC/illegal-element-type.ll): suppose
a node X is processed, and processing maps it to
a node Y. Then X continues to exist in the DAG,
but with no users. While processing some other
node, a new node may be created that happens to
be equal to X, and thus X will be reused rather
than a truly new node. This can cause X to
"magically reappear", and since it is in the
Processed state in will not be reprocessed, so
at the end of type legalization the illegal node
X can still be present. The solution is to replace
X with Y whenever X gets resurrected like this.
llvm-svn: 47601
2008-02-26 11:21:42 +00:00
80d6b87934
De-tabify
...
llvm-svn: 47600
2008-02-26 10:57:23 +00:00
d188e03715
De-tabify.
...
llvm-svn: 47599
2008-02-26 10:53:30 +00:00
7bb51dfbb1
De-tabify.
...
llvm-svn: 47598
2008-02-26 10:51:52 +00:00
69a10f4112
Add support for intermodule tail calls on x86/32bit with
...
GOT-style position independent code. Before only tail calls to
protected/hidden functions within the same module were optimized.
Now all function calls are tail call optimized.
llvm-svn: 47594
2008-02-26 10:21:54 +00:00
b01b99ec78
Change the lowering of arguments for tail call optimized
...
calls. Before arguments that could overwrite each other were
explicitly lowered to a stack slot, not giving the register allocator
a chance to optimize. Now a sequence of copyto/copyfrom virtual
registers ensures that arguments are loaded in (virtual) registers
before they are lowered to the stack slot (and might overwrite each
other). Also parameter stack slots are marked mutable for
(potentially) tail calling functions.
llvm-svn: 47593
2008-02-26 09:19:59 +00:00
2ff0b0e681
This is possible:
...
vr1 = extract_subreg vr2, 3
...
vr3 = extract_subreg vr1, 2
The end result is vr3 is equal to vr2 with subidx 2.
llvm-svn: 47592
2008-02-26 08:03:41 +00:00
e7c14013f5
Fix isNegatibleForFree to not return true for ConstantFP nodes
...
after legalize. Just because a constant is legal (e.g. 0.0 in SSE)
doesn't mean that its negated value is legal (-0.0). We could make
this stronger by checking to see if the negated constant is actually
legal post negation, but it doesn't seem like a big deal.
llvm-svn: 47591
2008-02-26 07:04:54 +00:00
1da250097b
Fix PR2076. CodeGenPrepare now sinks address computation for inline asm memory
...
operands into inline asm block.
llvm-svn: 47589
2008-02-26 02:42:37 +00:00
ccc0c996a4
Refactor inline asm constraint matching code out of SDIsel into TargetLowering.
...
llvm-svn: 47587
2008-02-26 02:33:44 +00:00
443018e55e
Remove debugging help.
...
llvm-svn: 47585
2008-02-26 01:42:38 +00:00
bbfd874cb4
Update bitcode reader and writer to handle multiple return values.
...
Take 2.
llvm-svn: 47583
2008-02-26 01:29:32 +00:00
767338ccec
Pass const vectors by reference.
...
llvm-svn: 47577
2008-02-26 00:12:13 +00:00
a790af3a88
Revert the assert for MUL_LOHI with an unused high result; Chris
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pointed out that this isn't correct at -O0.
llvm-svn: 47575
2008-02-25 22:43:48 +00:00
65b404d61c
Revise previous patch per review.
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llvm-svn: 47573
2008-02-25 22:29:22 +00:00
0be2f3b941
Add an assert to verify that we don't see an
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{S,U}MUL_LOHI with an unused high value.
llvm-svn: 47569
2008-02-25 22:15:55 +00:00
2ff975e749
Remove the hack that turned an {S,U}MUL_LOHI with an unused high
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result into a MUL late in the X86 codegen process. ISD::MUL is
once again Legal on X86, so this is no longer needed. And, the
hack was suboptimal; see PR1874 for details.
llvm-svn: 47567
2008-02-25 21:57:04 +00:00
432e4a6742
Make some static variables const.
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llvm-svn: 47566
2008-02-25 21:39:34 +00:00
1f372edd97
Convert MaskedValueIsZero and all its users to use APInt. Also add
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a SignBitIsZero function to simplify a common use case.
llvm-svn: 47561
2008-02-25 21:11:39 +00:00
548677022c
All remat'ed loads cannot be folded into two-address code. Not just argument loads. This change doesn't really have any impact on codegen.
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llvm-svn: 47557
2008-02-25 19:24:01 +00:00
32d84b1772
Expand removal of MMX memory copies to allow 1 level
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of TokenFactor underneath chain (seems to be enough)
llvm-svn: 47554
2008-02-25 19:20:14 +00:00
896c519d19
In debug builds check that the key property holds: all
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result and operand types are legal.
llvm-svn: 47546
2008-02-25 16:21:21 +00:00
589a9fb6dc
Correctly determine whether a argument load can be folded into its uses.
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llvm-svn: 47545
2008-02-25 08:50:41 +00:00
df1d2b02f9
Fix an issue where GVN was performing the return slot optimization when it was
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not safe. This is fixed by more aggressively checking that the return slot is
not used elsewhere in the function.
llvm-svn: 47544
2008-02-25 04:08:09 +00:00
01d6257e81
Temporarily reverting 46959.
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llvm-svn: 47542
2008-02-25 03:57:32 +00:00
Nick Lewycky