9c8cd8c061
isel (i32 anyext i16) as insert_subreg when 16-bit ops are being promoted.
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llvm-svn: 101979
2010-04-21 01:47:12 +00:00
2ef63183a5
Separate out the AES-NI instructions from the SSE4.2 instructions. Add
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a new subtarget option for AES and check for the support. Add "westmere"
line of processors and add AES-NI support to the core i7.
Add a couple of TODOs for information I couldn't verify.
llvm-svn: 100231
2010-04-02 21:54:27 +00:00
738b0f9ec7
Nehalem unaligned memory access is fast.
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llvm-svn: 100089
2010-04-01 05:58:17 +00:00
bf724b9ee0
Turning off post-ra scheduling for x86. It isn't a consistent win.
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llvm-svn: 98810
2010-03-18 06:55:42 +00:00
a30d4ce194
add support for pentium class CPUs which do not have cmov,
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PR4841. Patch by Craig Smith!
llvm-svn: 98496
2010-03-14 18:31:44 +00:00
abd56bde0e
80-col violations/trailing whitespace.
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llvm-svn: 97427
2010-02-28 22:54:30 +00:00
c3c357006e
Setup correct data layout to match gcc's expectations on mingw32.
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llvm-svn: 95981
2010-02-12 15:28:56 +00:00
0067d6bbbe
Fix typo.
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llvm-svn: 93235
2010-01-12 08:30:46 +00:00
fd75e12954
Tweak commit 91745, which changed target data for both Mingw and Cygwin,
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to not touch Cygwin: the change caused llvm-gcc build failures due to
long double getting the wrong size. Patch by Aaron Gray.
llvm-svn: 93234
2010-01-12 08:21:07 +00:00
206351a1ff
Implement a feature (-vector-unaligned-mem) to allow targets to
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ignore alignment requirements for SIMD memory operands. This
is useful on architectures like the AMD 10h that do not trap on
unaligned references if a status bit is twiddled at startup time.
llvm-svn: 93151
2010-01-11 16:29:42 +00:00
71d7eaa87e
Remove target attribute break-sse-dep. Instead, do not fold load into sse partial update instructions unless optimizing for size.
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llvm-svn: 91910
2009-12-22 17:47:23 +00:00
148d87b0b0
Bump alignment requirements for windows targets to achieve compartibility with vcpp.
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Based on patch by Michael Beck!
llvm-svn: 91745
2009-12-19 02:04:23 +00:00
4cf30b72bf
On recent Intel u-arch's, folding loads into some unary SSE instructions can
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be non-optimal. To be precise, we should avoid folding loads if the instructions
only update part of the destination register, and the non-updated part is not
needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these instructions breaks
the partial register dependency and it can improve performance. e.g.
movss (%rdi), %xmm0
cvtss2sd %xmm0, %xmm0
instead of
cvtss2sd (%rdi), %xmm0
An alternative method to break dependency is to clear the register first. e.g.
xorps %xmm0, %xmm0
cvtss2sd (%rdi), %xmm0
llvm-svn: 91672
2009-12-18 07:40:29 +00:00
7a6611793f
Target-independent support for TargetFlags on BlockAddress operands,
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and support for blockaddresses in x86-32 PIC mode.
llvm-svn: 89506
2009-11-20 23:18:13 +00:00
b9fe5d5d02
Allow target to specify regclass for which antideps will only be broken along the critical path.
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llvm-svn: 88682
2009-11-13 19:52:48 +00:00
0d412c2528
Fixed to address code review. No functional changes.
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llvm-svn: 86634
2009-11-10 00:48:55 +00:00
cf89db135e
Allow targets to specify register classes whose member registers should not be renamed to break anti-dependencies.
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llvm-svn: 86628
2009-11-10 00:15:47 +00:00
8714348afd
indicate what the native integer types for the target are.
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Please verify.
llvm-svn: 86397
2009-11-07 19:07:32 +00:00
8b86efefec
X86 needs critical path anti-dependency breaking.
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llvm-svn: 84931
2009-10-23 05:57:35 +00:00
02ad4cb32e
Allow the target to select the level of anti-dependence breaking that should be performed by the post-RA scheduler. The default is none.
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llvm-svn: 84911
2009-10-22 23:19:17 +00:00
c436631a9c
Turn on post-alloc scheduling for x86.
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llvm-svn: 84431
2009-10-18 19:57:27 +00:00
936d87b39d
Oops. I forgot to change the tests first. Disable post-alloc scheduling.
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llvm-svn: 84425
2009-10-18 18:31:31 +00:00
0e9d9ca855
-Revert parts of 84326 and 84411. Distinquishing between fixed and non-fixed
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stack slots and giving them different PseudoSourceValue's did not fix the
problem of post-alloc scheduling miscompiling llvm itself.
- Apply Dan's conservative workaround by assuming any non fixed stack slots can
alias other memory locations. This means a load from spill slot #1 cannot
move above a store of spill slot #2 .
- Enable post-alloc scheduling for x86 at optimization leverl Default and above.
llvm-svn: 84424
2009-10-18 18:16:27 +00:00
007ceb4603
Change createPostRAScheduler so it can be turned off at llc -O1.
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llvm-svn: 84273
2009-10-16 21:06:15 +00:00
e4a2117161
Remove X86Subtarget::IsLinux. It's no longer being used.
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llvm-svn: 84200
2009-10-15 20:23:21 +00:00
46dcaadb4a
rearrange X86ATTAsmPrinter::doFinalization, making a scan of
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the global variable list only happen for COFF targets.
llvm-svn: 82010
2009-09-16 05:20:33 +00:00
c3a0aba120
Make these functions static and local.
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llvm-svn: 80892
2009-09-03 05:47:34 +00:00
47455a79ae
X86JITInfo::getLazyResolverFunction() should not read cpu id to determine whether sse is available. Just use consult subtarget.
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No functionality changes.
llvm-svn: 80880
2009-09-03 04:37:05 +00:00
cc8c581a5b
Add support for modeling whether or not the processor has support for
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conditional moves as a subtarget feature. This is the easy part of
PR4841.
llvm-svn: 80763
2009-09-02 05:53:04 +00:00
1e9097e36a
change the -x86-asm-syntax=intel/att flag to be in X86TAI
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instead of X86 Subtarget. This elimianates dependencies on
X86Subtarget from X86TAI.
llvm-svn: 78746
2009-08-11 23:01:09 +00:00
31b44e8f6c
Normalize Subtarget constructors to take a target triple string instead of
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Module*.
Also, dropped uses of TargetMachine where unnecessary. The only target which
still takes a TargetMachine& is Mips, I would appreciate it if someone would
normalize this to match other targets.
llvm-svn: 77918
2009-08-02 22:11:08 +00:00
21c2940553
remove the now-dead TM argument to these methods.
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llvm-svn: 75276
2009-07-10 21:00:45 +00:00
ba4d73310a
make PIC vs DynamicNoPIC be explicit in PICStyles.
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llvm-svn: 75275
2009-07-10 20:58:47 +00:00
e2f524f176
add a couple of predicates to test for "stub style pic in PIC mode" and "stub style pic in dynamic-no-pic" mode.
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llvm-svn: 75273
2009-07-10 20:47:30 +00:00
20073edf67
simplify fast isel by using ClassifyGlobalReference. This
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elimiantes the last use of GVRequiresExtraLoad, so delete it.
llvm-svn: 75244
2009-07-10 07:48:51 +00:00
93f0f79178
eliminate GVRequiresRegister, replacing it with predicates we
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need for other purposes.
llvm-svn: 75243
2009-07-10 07:38:24 +00:00
dc842c06c2
move some classification logic around. Now GVRequiresExtraLoad
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is just a trivial wrapper around "ClassifyGlobalReference", which
stole a ton of logic from LowerGlobalAddress.
llvm-svn: 75237
2009-07-10 07:20:05 +00:00
b9af63a4d2
GVRequiresExtraLoad is now never used for calls, simplify it based on this.
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llvm-svn: 75232
2009-07-10 05:52:02 +00:00
ace6ec26d9
actually, just eliminate PCRelGVRequiresExtraLoad. It makes the code
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more complex and slow than just directly testing what we care about.
llvm-svn: 75231
2009-07-10 05:48:03 +00:00
7277a807f0
There is only one case where GVRequiresExtraLoad returns true for calls:
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split its handling out to PCRelGVRequiresExtraLoad, and simplify code
based on this.
llvm-svn: 75230
2009-07-10 05:45:15 +00:00
1cc7ae7c3b
the "isDirectCall" operand of GVRequiresRegister is always false, eliminate it.
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llvm-svn: 75229
2009-07-10 05:37:11 +00:00
1c5bf9d26d
When in -static mode, force the PIC style to none. Doing this requires fixing
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code which conflated RIPRel PIC with x86-64. Fix these to just check for X86-64
directly.
llvm-svn: 75092
2009-07-09 03:15:51 +00:00
a4b8998fbb
Fix a subtarget feature bug.
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llvm-svn: 74428
2009-06-29 16:51:01 +00:00
8f6f72cc99
Add feature flags for AVX and FMA and fix some SSE4A feature flag
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initialization problems.
llvm-svn: 74350
2009-06-26 22:46:54 +00:00
cfad3f3807
cosmetic changes.
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llvm-svn: 73836
2009-06-21 01:27:55 +00:00
96180b5387
Update CPU capabilities for AMD machines
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- added processors k8-sse3, opteron-sse3, athlon64-sse3, amdfam10, and
barcelona with appropriate sse3/4a levels
- added FeatureSSE4A for amdfam10 processors
in X86Subtarget:
- added hasSSE4A
- updated AutoDetectSubtargetFeatures to detect SSE4A
- updated GetCurrentX86CPU to detect family 15 with sse3 as k8-sse3 and
family 10h as amdfam10
New processor names match those used by gcc.
Patch by Paul Redmond!
llvm-svn: 72434
2009-05-26 21:04:35 +00:00
08bf4c0f5a
Propagate CPU string out of SubtargetFeatures
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llvm-svn: 72335
2009-05-23 19:50:50 +00:00
960983371c
Try again. Allow call to immediate address for ELF or when in static relocation mode.
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llvm-svn: 72160
2009-05-20 04:53:57 +00:00
906152a20f
Tidy up #includes, deleting a bunch of unnecessary #includes.
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llvm-svn: 61715
2009-01-05 17:59:02 +00:00
4c91aa3418
Do not isel load folding bt instructions for pentium m, core, core2, and AMD processors. These are significantly slower than a load followed by a bt of a register.
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llvm-svn: 61557
2009-01-02 05:35:45 +00:00
Evan Cheng