6e45f1d1ff
Promoting 16-bit cmp / test aren't free. Don't do it.
...
llvm-svn: 102366
2010-04-26 19:06:11 +00:00
1ff9d1b63e
Remove a redundant comment.
...
llvm-svn: 102326
2010-04-26 08:16:57 +00:00
ed69b382ea
- Move TargetLowering::EmitTargetCodeForFrameDebugValue to TargetInstrInfo and rename it to emitFrameIndexDebugValue.
...
- Teach spiller to modify DBG_VALUE instructions to reference spill slots.
llvm-svn: 102323
2010-04-26 07:38:55 +00:00
582565e991
Stop abusing EmitInstrWithCustomInserter for target-dependent
...
form of DEBUG_VALUE, as it doesn't have reasonable default
behavior for unsupported targets. Add a new hook instead.
No functional change.
llvm-svn: 102320
2010-04-25 21:33:54 +00:00
a02d0e7d6b
Avoid promoting a i16 node if it would eliminate a (store (op (load))) opportunity.
...
llvm-svn: 102237
2010-04-24 04:44:57 +00:00
24b63f1597
Add some missing x86 patterns for movdq2q. Fixes two (LLVM-)GCC DejaGNU testcases. Radar 6881029.
...
llvm-svn: 102199
2010-04-23 19:03:32 +00:00
0367559786
Fix X86ISD::CMP i16 to i32 promotion.
...
llvm-svn: 102192
2010-04-23 18:21:16 +00:00
c594eab10f
Move HandlePHINodesInSuccessorBlocks functions out of SelectionDAGISel
...
and into SelectionDAGBuilder and FastISel.
llvm-svn: 102123
2010-04-22 20:46:50 +00:00
f1223bdec0
- It's not safe to promote rotates (at least not trivially).
...
- Some code refactoring.
llvm-svn: 102111
2010-04-22 20:19:46 +00:00
4158a0ff6b
Implement -disable-non-leaf-fp-elim which disable frame pointer elimination
...
optimization for non-leaf functions. This will be hooked up to gcc's
-momit-leaf-frame-pointer option. rdar://7886181
llvm-svn: 101984
2010-04-21 03:18:23 +00:00
9c8cd8c061
isel (i32 anyext i16) as insert_subreg when 16-bit ops are being promoted.
...
llvm-svn: 101979
2010-04-21 01:47:12 +00:00
873310f635
Trim include.
...
llvm-svn: 101978
2010-04-21 01:39:06 +00:00
11740305f9
Handle a displacement location in 64-bit as an RIP-relative displacement. It
...
fixes a bug (<rdar://problem/7880900>) in the JIT. This code wouldn't work:
target triple = "x86_64-apple-darwin"
define double @func(double %a) {
%tmp1 = fmul double %a, 5.000000e-01 ; <double> [#uses=1]
ret double %tmp1
}
define i32 @main() nounwind {
%1 = call double @func(double 4.770000e-04) ; <i64> [#uses=0]
ret i32 0
}
llvm-svn: 101965
2010-04-21 00:34:04 +00:00
84776786a7
teach the x86 address matching stuff to handle
...
(shl (or x,c), 3) the same as (shl (add x, c), 3)
when x doesn't have any bits from c set.
This finishes off PR1135. Before we compiled the block to:
to:
LBB0_3: ## %bb
cmpb $4, %dl
sete %dl
addb %dl, %cl
movb %cl, %dl
shlb $2, %dl
addb %r8b, %dl
shlb $2, %dl
movzbl %dl, %edx
movl %esi, (%rdi,%rdx,4)
leaq 2(%rdx), %r9
movl %esi, (%rdi,%r9,4)
leaq 1(%rdx), %r9
movl %esi, (%rdi,%r9,4)
addq $3, %rdx
movl %esi, (%rdi,%rdx,4)
incb %r8b
decb %al
movb %r8b, %dl
jne LBB0_1
Now we produce:
LBB0_3: ## %bb
cmpb $4, %dl
sete %dl
addb %dl, %cl
movb %cl, %dl
shlb $2, %dl
addb %r8b, %dl
shlb $2, %dl
movzbl %dl, %edx
movl %esi, (%rdi,%rdx,4)
movl %esi, 8(%rdi,%rdx,4)
movl %esi, 4(%rdi,%rdx,4)
movl %esi, 12(%rdi,%rdx,4)
incb %r8b
decb %al
movb %r8b, %dl
jne LBB0_1
llvm-svn: 101958
2010-04-20 23:18:40 +00:00
0522b90cdb
Because of the EMMS problem, right now we have to support
...
user-defined operations that use MMX register types, but
the compiler shouldn't generate them on its own. This adds
a Synthesizable abstraction to represent this, and changes
the vector widening computation so it won't produce MMX types.
(The motivation is to remove noise from the ABI compatibility
part of the gcc test suite, which has some breakage right now.)
llvm-svn: 101951
2010-04-20 22:34:09 +00:00
4025306a91
disable optimizations in this directory for MSVC9. This avoids
...
an optimizer infinite loop on the file, PR6866.
llvm-svn: 101854
2010-04-20 01:11:32 +00:00
64831c6a4c
Remove the palignr intrinsics now that we lower them to vector shuffles,
...
shifts and null vectors. Autoupgrade these to what we'd lower them to.
Add a testcase to exercise this.
llvm-svn: 101851
2010-04-20 00:59:54 +00:00
e19aa5cc52
More progress on promoting i16 operations to i32 for x86. Work in progress.
...
llvm-svn: 101808
2010-04-19 19:29:22 +00:00
b927073f2e
teach the x86 asm parser how to handle segment prefixes
...
in memory operands. rdar://7874844
llvm-svn: 101661
2010-04-17 18:56:34 +00:00
05f34394d9
remove a dead variable, PR6856
...
llvm-svn: 101648
2010-04-17 17:28:00 +00:00
53d4a08d2b
Add const qualifiers to TargetLoweringObjectFile usage.
...
llvm-svn: 101640
2010-04-17 16:44:48 +00:00
88f7f6aeda
Use const_cast instead of a C-style cast to cast away const.
...
llvm-svn: 101639
2010-04-17 16:43:55 +00:00
21cea8ac2e
Use const qualifiers with TargetLowering. This eliminates several
...
const_casts, and it reinforces the design of the Target classes being
immutable.
SelectionDAGISel::IsLegalToFold is now a static member function, because
PIC16 uses it in an unconventional way. There is more room for API
cleanup here.
And PIC16's AsmPrinter no longer uses TargetLowering.
llvm-svn: 101635
2010-04-17 15:26:15 +00:00
31ae586c74
Move per-function state out of TargetLowering subclasses and into
...
MachineFunctionInfo subclasses.
llvm-svn: 101634
2010-04-17 14:41:14 +00:00
7f5088e6de
a bunch of ssse3 instructions are misencoded to think they have an
...
i8 field when they really do not. This fixes rdar://7840289
llvm-svn: 101629
2010-04-17 07:38:24 +00:00
f1bd5fcdb4
More work to allow dag combiner to promote 16-bit ops to 32-bit.
...
llvm-svn: 101621
2010-04-17 06:13:15 +00:00
7258dcd77f
Revert 101465, it broke internal OpenGL testing.
...
Probably the best way to know that all getOperand() calls have been handled
is to replace that API instead of updating.
llvm-svn: 101579
2010-04-16 23:37:20 +00:00
9becdddc49
Add skeleton target-specific SelectionDAGInfo files.
...
llvm-svn: 101564
2010-04-16 23:04:22 +00:00
d4758fc393
add a missing break back, patch by Nico Schmidt!
...
llvm-svn: 101538
2010-04-16 21:15:15 +00:00
148c69a3f6
Eliminate an unnecessary SelectionDAG dependency in getOptimalMemOpType.
...
llvm-svn: 101531
2010-04-16 20:11:05 +00:00
f375520f7b
reapply r101434
...
with a fix for self-hosting
rotate CallInst operands, i.e. move callee to the back
of the operand array
the motivation for this patch are laid out in my mail to llvm-commits:
more efficient access to operands and callee, faster callgraph-construction,
smaller compiler binary
llvm-svn: 101465
2010-04-16 15:33:14 +00:00
af56facacd
Adding support for dag combiner to promote operations for profit. This requires target specific queries. For example, x86 should promote i16 to i32 when it does not impact load folding.
...
x86 support is off by default. It can be enabled with -promote-16bit.
Work in progress.
llvm-svn: 101448
2010-04-16 06:14:10 +00:00
403e9694f9
back out r101423 and r101397, they break llvm-gcc self-host on darwin10
...
llvm-svn: 101434
2010-04-16 01:16:20 +00:00
33ae80bff7
reapply r101364, which has been backed out in r101368
...
with a fix
rotate CallInst operands, i.e. move callee to the back
of the operand array
the motivation for this patch are laid out in my mail to llvm-commits:
more efficient access to operands and callee, faster callgraph-construction,
smaller compiler binary
llvm-svn: 101397
2010-04-15 20:51:13 +00:00
9fd00c7d25
back out r101364, as it trips the linux nightlybot on some clang C++ tests
...
llvm-svn: 101368
2010-04-15 12:46:56 +00:00
aafd209632
rotate CallInst operands, i.e. move callee to the back
...
of the operand array
the motivation for this patch are laid out in my mail to llvm-commits:
more efficient access to operands and callee, faster callgraph-construction,
smaller compiler binary
llvm-svn: 101364
2010-04-15 10:49:53 +00:00
bcaf681cde
Add const qualifiers to CodeGen's use of LLVM IR constructs.
...
llvm-svn: 101334
2010-04-15 01:51:59 +00:00
eabc9623da
Allow lowering for palignr instructions for mmx sized vectors. Add
...
patterns to handle the lowering.
llvm-svn: 101331
2010-04-15 01:40:20 +00:00
c87b74d913
Delete unneeeded arguments.
...
llvm-svn: 101276
2010-04-14 20:17:22 +00:00
7deb447781
Factor out EH landing pad code into a separate function, and constify
...
a bunch of stuff to support it.
llvm-svn: 101273
2010-04-14 19:53:31 +00:00
9078f954bf
Unbreak CMake build by improving the EnhancedDisassembly makefile a
...
bit (we're not trying to build a shared library yet) and generating
the X86GenEDInfo.inc and ARMGenEDInfo.inc files as necessary.
llvm-svn: 101188
2010-04-13 22:47:43 +00:00
814e69b171
Fixed a nasty layering violation in the edis source
...
code. It used to #include the enhanced disassembly
information for the targets it supported straight
out of lib/Target/{X86,ARM,...} but now it uses a
new interface provided by MCDisassembler, and (so
far) implemented by X86 and ARM.
Also removed hacky #define-controlled initialization
of targets in edis. If clients only want edis to
initialize a limited set of targets, they can set
--enable-targets on the configure command line.
llvm-svn: 101179
2010-04-13 21:21:57 +00:00
4ca4bc6f95
Re-apply 101075 and fix it properly. Just reuse the debug info of the branch instruction being optimized. There is no need to --I which can deref off start of the BB.
...
llvm-svn: 101162
2010-04-13 18:50:27 +00:00
d67f66dc0c
Temporarily revert r101075, it's causing invalid iterator assertions
...
in a nightly tester.
llvm-svn: 101158
2010-04-13 18:37:58 +00:00
9d2d053e11
Eliminate MachineBasicBlock::const_livein_iterator and make
...
MachineBasicBlock::livein_iterator a const_iterator, because
clients shouldn't ever be using the iterator interface to
mutate the livein set.
llvm-svn: 101147
2010-04-13 16:57:55 +00:00
d0d8e3343a
Use .set expression for x86 pic jump table reference to reduce assembly relocation. rdar://7738756
...
llvm-svn: 101085
2010-04-12 23:07:17 +00:00
b02bbe416f
Micro-optimization:
...
If we have this situation:
jCC L1
jmp L2
L1:
...
L2:
...
We can get a small performance boost by emitting this instead:
jnCC L2
L1:
...
L2:
...
This testcase shows an example of this:
float func(float x, float y) {
double product = (double)x * y;
if (product == 0.0)
return product;
return product - 1.0;
}
llvm-svn: 101075
2010-04-12 22:19:57 +00:00
5418dd5fda
move elf section uniquing to MCContext. Along the way
...
merge XCore's section into MCSectionELF
llvm-svn: 100812
2010-04-08 21:26:26 +00:00
433d40695b
remove the TargetLoweringObjectFileMachO::getMachoSection
...
api and update clients to use MCContext instead.
llvm-svn: 100808
2010-04-08 20:40:11 +00:00
ebe47c872f
Avoid using f64 to lower memcpy from constant string. It's cheaper to use i32 store of immediates.
...
llvm-svn: 100751
2010-04-08 07:37:57 +00:00
Evan Cheng