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13919 Commits

Author SHA1 Message Date
Bob Wilson 25f85947a3 Handle register-to-register copies within the tGPR class. 
Radar 7896289

llvm-svn: 102396
 2010-04-26 23:20:08 +00:00
Dale Johannesen 91358585d7 Handle target-specific form of DBG_VALUE in AsmPrinter. 
llvm-svn: 102373
 2010-04-26 20:07:31 +00:00
Dale Johannesen bc41cfa78f Add PPC AsmPrinter handling for target-specific form of 
DBG_VALUE, and a cautionary comment.

llvm-svn: 102371
 2010-04-26 20:05:01 +00:00
Evan Cheng 6e45f1d1ff Promoting 16-bit cmp / test aren't free. Don't do it. 
llvm-svn: 102366
 2010-04-26 19:06:11 +00:00
Evan Cheng 1ff9d1b63e Remove a redundant comment. 
llvm-svn: 102326
 2010-04-26 08:16:57 +00:00
Evan Cheng f19bd4ebba Add PPC specific emitFrameIndexDebugValue. 
llvm-svn: 102325
 2010-04-26 07:39:36 +00:00
Evan Cheng bcb99ecc18 Add ARM specific emitFrameIndexDebugValue. 
llvm-svn: 102324
 2010-04-26 07:39:25 +00:00
Evan Cheng ed69b382ea - Move TargetLowering::EmitTargetCodeForFrameDebugValue to TargetInstrInfo and rename it to emitFrameIndexDebugValue. 
- Teach spiller to modify DBG_VALUE instructions to reference spill slots.

llvm-svn: 102323
 2010-04-26 07:38:55 +00:00
Dale Johannesen 582565e991 Stop abusing EmitInstrWithCustomInserter for target-dependent 
form of DEBUG_VALUE, as it doesn't have reasonable default
behavior for unsupported targets.  Add a new hook instead.
No functional change.

llvm-svn: 102320
 2010-04-25 21:33:54 +00:00
Evan Cheng a02d0e7d6b Avoid promoting a i16 node if it would eliminate a (store (op (load))) opportunity. 
llvm-svn: 102237
 2010-04-24 04:44:57 +00:00
Dan Gohman e1931fa676 Change TargetData's algorithm for computing defualt vector type 
alignment to match what's used in clang and GCC for __alignof, rather
than trying to guess what Legalize is going to be doing.

llvm-svn: 102206
 2010-04-23 19:41:15 +00:00
Stuart Hastings 24b63f1597 Add some missing x86 patterns for movdq2q. Fixes two (LLVM-)GCC DejaGNU testcases. Radar 6881029. 
llvm-svn: 102199
 2010-04-23 19:03:32 +00:00
Evan Cheng 0367559786 Fix X86ISD::CMP i16 to i32 promotion. 
llvm-svn: 102192
 2010-04-23 18:21:16 +00:00
Jim Grosbach 825cb299cd Update ARM DAGtoDAG for matching UBFX instruction for unsigned bitfield 
extraction. This fixes PR5998.

llvm-svn: 102144
 2010-04-22 23:24:18 +00:00
Dan Gohman c594eab10f Move HandlePHINodesInSuccessorBlocks functions out of SelectionDAGISel 
and into SelectionDAGBuilder and FastISel.

llvm-svn: 102123
 2010-04-22 20:46:50 +00:00
Evan Cheng f1223bdec0 - It's not safe to promote rotates (at least not trivially). 
- Some code refactoring.

llvm-svn: 102111
 2010-04-22 20:19:46 +00:00
Johnny Chen d85afee134 Modified some assert() msg strings; no other functionality change. 
llvm-svn: 102008
 2010-04-21 18:37:48 +00:00
Evan Cheng 4158a0ff6b Implement -disable-non-leaf-fp-elim which disable frame pointer elimination 
optimization for non-leaf functions. This will be hooked up to gcc's
-momit-leaf-frame-pointer option. rdar://7886181

llvm-svn: 101984
 2010-04-21 03:18:23 +00:00
Evan Cheng 9c8cd8c061 isel (i32 anyext i16) as insert_subreg when 16-bit ops are being promoted. 
llvm-svn: 101979
 2010-04-21 01:47:12 +00:00
Evan Cheng 873310f635 Trim include. 
llvm-svn: 101978
 2010-04-21 01:39:06 +00:00
Dan Gohman 57c732b032 Add more const qualifiers on TargetMachine and friends. 
llvm-svn: 101977
 2010-04-21 01:34:56 +00:00
Johnny Chen dd56c40591 Thumb instructions which have reglist operands at the end and predicate operands 
before reglist were not properly handled with respect to IT Block.  Fix that by
creating a new method ARMBasicMCBuilder::DoPredicateOperands() used by those
instructions for disassembly.  Add a test case.

llvm-svn: 101974
 2010-04-21 01:01:19 +00:00
Bill Wendling 11740305f9 Handle a displacement location in 64-bit as an RIP-relative displacement. It 
fixes a bug (<rdar://problem/7880900>) in the JIT. This code wouldn't work:

target triple = "x86_64-apple-darwin"

define double @func(double %a) {
  %tmp1 = fmul double %a, 5.000000e-01            ; <double> [#uses=1]
  ret double %tmp1
}

define i32 @main() nounwind {
  %1 = call double @func(double 4.770000e-04) ; <i64> [#uses=0]
  ret i32 0
}

llvm-svn: 101965
 2010-04-21 00:34:04 +00:00
Chris Lattner 84776786a7 teach the x86 address matching stuff to handle 
(shl (or x,c), 3) the same as (shl (add x, c), 3)
when x doesn't have any bits from c set.

This finishes off PR1135.  Before we compiled the block to:
to:

LBB0_3:                                 ## %bb
	cmpb	$4, %dl
	sete	%dl
	addb	%dl, %cl
	movb	%cl, %dl
	shlb	$2, %dl
	addb	%r8b, %dl
	shlb	$2, %dl
	movzbl	%dl, %edx
	movl	%esi, (%rdi,%rdx,4)
	leaq	2(%rdx), %r9
	movl	%esi, (%rdi,%r9,4)
	leaq	1(%rdx), %r9
	movl	%esi, (%rdi,%r9,4)
	addq	$3, %rdx
	movl	%esi, (%rdi,%rdx,4)
	incb	%r8b
	decb	%al
	movb	%r8b, %dl
	jne	LBB0_1

Now we produce:

LBB0_3:                                 ## %bb
	cmpb	$4, %dl
	sete	%dl
	addb	%dl, %cl
	movb	%cl, %dl
	shlb	$2, %dl
	addb	%r8b, %dl
	shlb	$2, %dl
	movzbl	%dl, %edx
	movl	%esi, (%rdi,%rdx,4)
	movl	%esi, 8(%rdi,%rdx,4)
	movl	%esi, 4(%rdi,%rdx,4)
	movl	%esi, 12(%rdi,%rdx,4)
	incb	%r8b
	decb	%al
	movb	%r8b, %dl
	jne	LBB0_1

llvm-svn: 101958
 2010-04-20 23:18:40 +00:00
Dale Johannesen 0522b90cdb Because of the EMMS problem, right now we have to support 
user-defined operations that use MMX register types, but
the compiler shouldn't generate them on its own.  This adds
a Synthesizable abstraction to represent this, and changes
the vector widening computation so it won't produce MMX types.
(The motivation is to remove noise from the ABI compatibility
part of the gcc test suite, which has some breakage right now.)

llvm-svn: 101951
 2010-04-20 22:34:09 +00:00
Johnny Chen 8bcc00b43e Better error-handling of getBitFieldInvMask() where msb < lsb (encoding error), 
instead of just asserting.

llvm-svn: 101942
 2010-04-20 21:29:28 +00:00
Johnny Chen 7be315c414 For t2LDRT, t2LDRBT, t2LDRHT, t2LDRSBT, and t2LDRSHT, if Rn(Inst{19-16})=='1111', 
transform the Opcode to the corresponding t2LDR*pci counterpart.

Ref: A8.6.86 LDRT, A8.6.65 LDRBT, A8.6.77 LDRHT, A8.6.81 LDRSBT, A8.6.85 LDRSHT
llvm-svn: 101915
 2010-04-20 17:28:50 +00:00
Chris Lattner 38c1a1a247 teach cellspu how to return i8 and i16 from calls, 
patch by Kalle Raiskila!

llvm-svn: 101875
 2010-04-20 05:36:09 +00:00
Chris Lattner 4025306a91 disable optimizations in this directory for MSVC9. This avoids 
an optimizer infinite loop on the file, PR6866.

llvm-svn: 101854
 2010-04-20 01:11:32 +00:00
Johnny Chen 2161e9f03b Better error-handling for DisassembleThumb2DPModImm() with 2-reg operands where 
d==15 is considered illegal.  Return false instead of assert().

llvm-svn: 101852
 2010-04-20 01:01:57 +00:00
Eric Christopher 64831c6a4c Remove the palignr intrinsics now that we lower them to vector shuffles, 
shifts and null vectors. Autoupgrade these to what we'd lower them to.

Add a testcase to exercise this.

llvm-svn: 101851
 2010-04-20 00:59:54 +00:00
Johnny Chen f3dd8b9487 More IT instruction error-handling improvements from fuzzing. 
llvm-svn: 101839
 2010-04-20 00:15:41 +00:00
Johnny Chen e62b680965 Better error handling of invalid IT mask '0000', instead of just asserting. 
llvm-svn: 101827
 2010-04-19 23:02:58 +00:00
Dan Gohman 5ccd0b3686 Delete an unnecessary reference to SelectionDAGISel::BB. 
llvm-svn: 101824
 2010-04-19 22:48:45 +00:00
Johnny Chen 777346e749 According to A8.6.16 B (Encoding T3) and A8.3 Conditional execution -- A8.3.1 
Pseudocode details of conditional, Condition bits '111x' indicate the
instruction is always executed.  That is, '1111' is a leagl condition field
value, which is now mapped to ARMCC::AL.

Also add a test case for condition field '1111'.

llvm-svn: 101817
 2010-04-19 21:19:52 +00:00
Evan Cheng e19aa5cc52 More progress on promoting i16 operations to i32 for x86. Work in progress. 
llvm-svn: 101808
 2010-04-19 19:29:22 +00:00
Johnny Chen 25df2a75bd Better error-handling for DisassembleThumb2DPSoReg() where the 3-reg operand 
instructions should have Rd (Inst{11-8}) != 0b1111.

Ref: A6.3 32-bit Thumb instruction encoding
     A6.3.11 Data-processing (shifted register)
llvm-svn: 101788
 2010-04-19 17:16:40 +00:00
Johnny Chen cbe3e1a3df ARM disassembler did not react to recent changes to the NEON instruction table. 
VLD1q*_UPD and VST1q*_UPD have the ${dst:dregpair} operand now.

llvm-svn: 101784
 2010-04-19 16:20:34 +00:00
Anton Korobeynikov 7b056bfed0 Add missed part of prev. commit 
llvm-svn: 101755
 2010-04-18 20:41:42 +00:00
Anton Korobeynikov 7d62e33291 Make processor FUs unique for given itinerary. This extends the limit of 32 
FU per CPU arch to 32 per intinerary allowing precise modelling of quite
complex pipelines in the future.

llvm-svn: 101754
 2010-04-18 20:31:01 +00:00
Chris Lattner 0a8d91a816 fix PR6332, allowing an index of zero into a zero sized array 
even if the element of the array has no size.

llvm-svn: 101662
 2010-04-17 19:02:33 +00:00
Chris Lattner b927073f2e teach the x86 asm parser how to handle segment prefixes 
in memory operands.  rdar://7874844

llvm-svn: 101661
 2010-04-17 18:56:34 +00:00
Dan Gohman 1f0f2142cc Fix -Wcast-qual warnings. 
llvm-svn: 101655
 2010-04-17 17:42:52 +00:00
Chris Lattner 05f34394d9 remove a dead variable, PR6856 
llvm-svn: 101648
 2010-04-17 17:28:00 +00:00
Dan Gohman 53d4a08d2b Add const qualifiers to TargetLoweringObjectFile usage. 
llvm-svn: 101640
 2010-04-17 16:44:48 +00:00
Dan Gohman 88f7f6aeda Use const_cast instead of a C-style cast to cast away const. 
llvm-svn: 101639
 2010-04-17 16:43:55 +00:00
Dan Gohman 8422e57baa Delete now-unnecessary const_casts. 
llvm-svn: 101637
 2010-04-17 15:32:28 +00:00
Dan Gohman 20e094c711 Use cast instead of dyn_cast when assuming success. 
llvm-svn: 101636
 2010-04-17 15:31:16 +00:00
Dan Gohman 21cea8ac2e Use const qualifiers with TargetLowering. This eliminates several 
const_casts, and it reinforces the design of the Target classes being
immutable.

SelectionDAGISel::IsLegalToFold is now a static member function, because
PIC16 uses it in an unconventional way. There is more room for API
cleanup here.

And PIC16's AsmPrinter no longer uses TargetLowering.

llvm-svn: 101635
 2010-04-17 15:26:15 +00:00
Dan Gohman 31ae586c74 Move per-function state out of TargetLowering subclasses and into 
MachineFunctionInfo subclasses.

llvm-svn: 101634
 2010-04-17 14:41:14 +00:00