18277eafb0
llvmc: Fix alias generation.
...
llvm-svn: 111662
2010-08-20 18:16:26 +00:00
a931605647
Convert DbgInfoPrinter to use errs() instead of outs().
...
llvm-svn: 111659
2010-08-20 18:03:05 +00:00
8264a68b4c
Fix the running of ocaml tests.
...
llvm-svn: 111626
2010-08-20 14:51:26 +00:00
b4d48706ca
Expose LLVMSetOperand and LLVMGetNumOperands to llvm-c and ocaml.
...
llvm-svn: 111625
2010-08-20 14:51:22 +00:00
21b62ac673
Fix some Ocaml tests: the %t substitution now returns an absolute path.
...
llvm-svn: 111623
2010-08-20 14:20:17 +00:00
6c66144eb3
The %ocamlopt setting has embedded quotes. Copy the entire value instead
...
of stopping at the first embedded quote.
llvm-svn: 111622
2010-08-20 14:19:38 +00:00
18f47c7105
Update LLVMC tests for r111620.
...
llvm-svn: 111621
2010-08-20 13:03:33 +00:00
9a511c07e4
Replace the arm.neon.vmovls and vmovlu intrinsics with vector sign-extend and
...
zero-extend operations.
llvm-svn: 111614
2010-08-20 04:54:02 +00:00
3323651ec7
Previous revert failed to remove this file.
...
llvm-svn: 111582
2010-08-19 23:45:15 +00:00
43057cd56a
Revert r111568 to unbreak clang self-host.
...
llvm-svn: 111571
2010-08-19 23:25:16 +00:00
bb723b228a
When a set of bitmask operations, typically from a bitfield initialization, only modifies the low bytes of a value,
...
we can narrow the store to only over-write the affected bytes.
llvm-svn: 111568
2010-08-19 22:15:40 +00:00
361b9be7c6
It's possible to sink a def if its local uses are PHI's.
...
llvm-svn: 111537
2010-08-19 18:33:29 +00:00
0d7e9538db
tests: Haste makes waste.
...
llvm-svn: 111525
2010-08-19 16:47:54 +00:00
471a649c6b
tests: Ignore whitespace in llvm_supports_binding() and llvm_gcc_supports().
...
llvm-svn: 111524
2010-08-19 16:46:52 +00:00
d4b6ab9888
Fixed and reactivated a partial specialization test
...
llvm-svn: 111516
2010-08-19 12:42:38 +00:00
f547740d3f
fix PR7465, mishandling of lcall and ljmp: intersegment long
...
call and jumps.
llvm-svn: 111496
2010-08-19 01:18:43 +00:00
8d5f0208f2
Testcase for llvm-gcc checkin 111482.
...
llvm-svn: 111483
2010-08-19 00:09:07 +00:00
3decde9305
refix PR1143 by making basicaa analyze zexts of indices aggresively,
...
which I broke with a recent patch.
llvm-svn: 111452
2010-08-18 23:09:49 +00:00
492c2ea31e
Add a testcase to verify that commands don't crash when they hit
...
errors on stderr.
llvm-svn: 111440
2010-08-18 22:35:56 +00:00
82656fb0e1
When sending stats output to stdout for grepping, don't emit normal
...
output to standard output also.
llvm-svn: 111435
2010-08-18 22:22:44 +00:00
2470818942
When sending stats output to stdout for grepping, don't emit normal
...
output to standard output also.
llvm-svn: 111401
2010-08-18 20:32:46 +00:00
8e92d9b68d
MC/ELF: Allow null values in virtual sections, ELF doesn't use special
...
directives for putting contents in .bss, for example.
llvm-svn: 111376
2010-08-18 18:22:37 +00:00
e60b5161d1
Fix a bug with insertelement on SPU.
...
The previous algorithm in LowerVECTOR_SHUFFLE
didn't check all requirements for "monotonic" shuffles.
llvm-svn: 111361
2010-08-18 10:20:29 +00:00
ab49360f59
Remove all traces of v2[i,f]32 on SPU.
...
The "half vectors" are now widened to full size by the legalizer.
The only exception is in parameter passing, where half vectors are
expanded. This causes changes to some dejagnu tests.
llvm-svn: 111360
2010-08-18 10:04:39 +00:00
f3984d1ef6
Change SPU C calling convention to match that described in
...
"SPU Application Binary Interface Specification, v1.9" by
IBM.
Specifically: use r3-r74 to pass parameters and the return value.
llvm-svn: 111358
2010-08-18 09:50:30 +00:00
a25c05ed15
fix a buggy test
...
llvm-svn: 111354
2010-08-18 04:55:12 +00:00
a33edcb56c
fix PR7589: In brief:
...
gep P, (zext x) != gep P, (sext x)
DecomposeGEPExpression was getting this wrong, confusing
basicaa.
llvm-svn: 111352
2010-08-18 04:28:19 +00:00
c8e38eb60b
filecheckize and detrivialize.
...
llvm-svn: 111350
2010-08-18 04:25:43 +00:00
3c603024bb
Fix PR7755: knowing something about an inval for a pred
...
from the LHS should disable reconsidering that pred on the
RHS. However, knowing something about the pred on the RHS
shouldn't disable subsequent additions on the RHS from
happening.
llvm-svn: 111349
2010-08-18 03:14:36 +00:00
fb7eaff759
Expand ZERO_EXTEND operations for NEON vector types.
...
Testcase from Nick Lewycky.
llvm-svn: 111341
2010-08-18 01:45:52 +00:00
51edc7b7e1
Temporarily revert r110987 as it's causing some miscompares in
...
vector heavy code. I'll re-enable when we've tracked down the problem.
llvm-svn: 111318
2010-08-17 22:55:27 +00:00
ed2b005842
Tweak IVUsers' concept of "interesting" to exclude add recurrences
...
where the step value is an induction variable from an outer loop, to
avoid trouble trying to re-expand such expressions. This effectively
hides such expressions from indvars and lsr, which prevents them
from getting into trouble.
llvm-svn: 111317
2010-08-17 22:50:37 +00:00
efdc74ea59
Add nounwind.
...
llvm-svn: 111312
2010-08-17 22:35:20 +00:00
16f96445c3
Make fast scheduler handle asm clobbers correctly.
...
PR 7882. Follows suggestion by Amaury Pouly, thanks.
llvm-svn: 111306
2010-08-17 22:17:24 +00:00
14be4dff8e
Add some win64 coff goodness.
...
Patch by Cameron Esfahani!
llvm-svn: 111287
2010-08-17 21:05:54 +00:00
5047ca0c02
When rotating loops, put the original header at the bottom of the
...
loop, making the resulting loop significantly less ugly. Also, zap
its trivial PHI nodes, since it's easy.
llvm-svn: 111255
2010-08-17 17:39:21 +00:00
942b10f511
Change ARM PKHTB and PKHBT instructions to use a shift_imm operand to avoid
...
printing "lsl #0". This fixes the remaining parts of pr7792. Make
corresponding changes for encoding/decoding these instructions.
llvm-svn: 111251
2010-08-17 17:23:19 +00:00
411dfad981
Allow more cases of undef shuffle indices and add tests for them.
...
llvm-svn: 111226
2010-08-17 05:54:34 +00:00
f259efde47
PHI elimination should not break back edge. It can cause some significant code placement issues. rdar://8263994
...
good:
LBB0_2:
mov r2, r0
. . .
mov r1, r2
bne LBB0_2
bad:
LBB0_2:
mov r2, r0
. . .
@ BB#3:
mov r1, r2
b LBB0_2
llvm-svn: 111221
2010-08-17 01:20:36 +00:00
eee4824f74
Add a testcase for svn 111208.
...
llvm-svn: 111212
2010-08-16 23:44:29 +00:00
804f6159f1
Generalize a pattern for PKHTB: an SRL of 16-31 bits will guarantee
...
that the high halfword is zero. The shift need not be exactly 16 bits.
llvm-svn: 111196
2010-08-16 22:26:55 +00:00
3fd1e0dcda
Convert test to FileCheck.
...
llvm-svn: 111195
2010-08-16 22:21:13 +00:00
8f553757c4
Convert a test to use FileCheck.
...
llvm-svn: 111153
2010-08-16 17:05:27 +00:00
250b754428
Instead, teach SimplifyCFG to trim non-address-taken blocks from
...
indirectbr destination lists.
llvm-svn: 111122
2010-08-16 14:41:14 +00:00
fb83b043eb
Revert r111058, the lint check for indirectbr successors that aren't
...
address-taken. This can occur normally, if the code which took the
address got DCEd.
llvm-svn: 111121
2010-08-16 14:39:19 +00:00
cbc55d9dc0
Test expects SSE, give him SSE.
...
llvm-svn: 111115
2010-08-15 23:32:03 +00:00
4566466b7f
Restore arch on these test, they fail on arm.
...
llvm-svn: 111109
2010-08-15 20:42:56 +00:00
339423c460
Mark as XFAIL on darwin 8. PR 7886.
...
llvm-svn: 111108
2010-08-15 19:40:29 +00:00
b1ec90bcf4
Update tests.
...
llvm-svn: 111096
2010-08-15 07:07:24 +00:00
aa445c0751
LoopSimplify shouldn't split loop backedges that use indirectbr. PR7867.
...
llvm-svn: 111061
2010-08-14 00:43:09 +00:00
4a63fad976
Teach SimplifyCFG how to simplify indirectbr instructions.
...
- Eliminate redundant successors.
- Convert an indirectbr with one successor into a direct branch.
Also, generalize SimplifyCFG to be able to be run on a function entry block.
It knows quite a few simplifications which are applicable to the entry
block, and it only needs a few checks to avoid trouble with the entry block.
llvm-svn: 111060
2010-08-14 00:29:42 +00:00
21e6dc6aa3
Add a lint check for an indirectbr destination which has not
...
had its address taken.
llvm-svn: 111058
2010-08-13 23:56:28 +00:00
4577f37d49
Add a Thumb2 t2RSBrr instruction for disassembly only.
...
This fixes another part of PR7792.
llvm-svn: 111057
2010-08-13 23:24:25 +00:00
3c9ed76ba5
Temporarily disable tail calls on ARM to work around some linker problems.
...
llvm-svn: 111050
2010-08-13 22:43:33 +00:00
15b3c3d0ac
Move the Thumb2 SSAT and USAT optional shift operator out of the
...
instruction opcode. This fixes part of PR7792.
llvm-svn: 111047
2010-08-13 21:48:10 +00:00
8d3c89e765
Revert 110491. While not wrong, it was based on a
...
misanalysis and is undesirable.
llvm-svn: 111028
2010-08-13 18:43:45 +00:00
1d54a4ea1d
One more XFAIL.
...
llvm-svn: 111010
2010-08-13 07:03:56 +00:00
49fd7d3a5f
More XFAILs.
...
llvm-svn: 111008
2010-08-13 07:01:55 +00:00
143a33758c
Add an XFAIL.
...
llvm-svn: 111004
2010-08-13 04:15:45 +00:00
ee1ef8c402
Remove -fexceptions from llvmc tests.
...
llvm-svn: 110999
2010-08-13 02:29:35 +00:00
d2cc5fb971
llvmc: fix two tests, remove XFAILs.
...
Tested on Linux and Darwin; please add platform-specific XFAILs/mail me a bug
report if this still fails.
llvm-svn: 110998
2010-08-13 02:29:24 +00:00
2a0ca3e937
Reapply this transformation now that it is passing the external test which it previously failed.
...
llvm-svn: 110987
2010-08-13 00:17:53 +00:00
363226dfe8
fix PR7876: If ipsccp decides that a function's address is taken
...
before it rewrites the code, we need to use that in the post-rewrite pass.
llvm-svn: 110962
2010-08-12 22:25:23 +00:00
8e8f1c133a
Cleaned up the for-disassembly-only entries in the arm instruction table so that
...
the memory barrier variants (other than 'SY' full system domain read and write)
are treated as one instruction with option operand.
llvm-svn: 110951
2010-08-12 20:46:17 +00:00
7f704b31a9
- Teach SSEDomainFix to switch between different levels of AVX instructions. Here we guess that AVX will have domain issues, so just implement them for consistency and in the future we remove if it's unnecessary.
...
- Make foldMemoryOperandImpl aware of 256-bit zero vectors folding and support the 128-bit counterparts of AVX too.
- Make sure MOV[AU]PS instructions are only selected when SSE1 is enabled, and duplicate the patterns to match AVX.
- Add a testcase for a simple 128-bit zero vector creation.
llvm-svn: 110946
2010-08-12 20:20:53 +00:00
86fa07ea05
Add a test for llvm-gcc svn 110632.
...
llvm-svn: 110935
2010-08-12 17:31:41 +00:00
ac40d49c70
Temporarily revert 110737 and 110734, they were causing failures
...
in an external testsuite.
llvm-svn: 110905
2010-08-12 07:01:22 +00:00
7306c86886
Begin to support some vector operations for AVX 256-bit intructions. The long
...
term goal here is to be able to match enough of vector_shuffle and build_vector
so all avx intrinsics which aren't mapped to their own built-ins but to
shufflevector calls can be codegen'd. This is the first (baby) step, support
building zeroed vectors.
llvm-svn: 110897
2010-08-12 02:06:36 +00:00
74491bb52c
The autogened decoder was confusing the ARM STRBT for ARM USAT, because the .td
...
entry for ARM STRBT is actually a super-instruction for A8.6.199 STRBT A1 & A2.
Recover by looking for ARM:USAT encoding pattern before delegating to the auto-
gened decoder.
Added a "usat" test case to arm-tests.txt.
llvm-svn: 110894
2010-08-12 01:40:54 +00:00
7d7b4d1b0f
MC/X86/AsmParser: Give an explicit error message when we reject an instruction
...
because it could have an ambiguous suffix.
llvm-svn: 110890
2010-08-12 00:55:42 +00:00
48595bf2bc
This is x86 only test.
...
llvm-svn: 110887
2010-08-12 00:17:38 +00:00
d59c73f998
Changed the format of DMBsy, DSBsy, and friends from Pseudo to MiscFrm.
...
Added two test cases to arm-tests.txt.
llvm-svn: 110880
2010-08-11 23:35:12 +00:00
add513112a
Move the ARM SSAT and USAT optional shift amount operand out of the
...
instruction opcode. This also fixes part of PR7792.
llvm-svn: 110875
2010-08-11 23:10:46 +00:00
1675ee7a02
Add testcases for all AVX 256-bit intrinsics added in the last couple days
...
llvm-svn: 110854
2010-08-11 21:12:09 +00:00
29c8818ad9
Reapply r109881 using a more strict command line for llc.
...
llvm-svn: 110833
2010-08-11 17:39:23 +00:00
a5f923b1a1
fix silly typo
...
llvm-svn: 110831
2010-08-11 17:32:46 +00:00
2bf8bd1e19
Add a target triple, as the runtime library invocation varies a bit by
...
platform. It's apparently "bl __muldf3" on linux, for example. Since that's
not what we're checking here, it's more robust to just force a triple. We
just wwant to check that the inline FP instructions are only generated
on cpus that have them."
llvm-svn: 110830
2010-08-11 17:31:12 +00:00
b0276814d5
Fix test and re-enable it.
...
llvm-svn: 110829
2010-08-11 17:25:51 +00:00
4df4114870
Temporarily disable some failing tests, until they can be
...
properly investigated.
llvm-svn: 110825
2010-08-11 16:36:07 +00:00
4d5dc3e7e5
cortex m4 has floating point support, but only single precision.
...
llvm-svn: 110810
2010-08-11 15:44:15 +00:00
f3d783a6d2
Temporarily disable some failing tests, until they can be
...
properly investigated.
llvm-svn: 110808
2010-08-11 15:09:00 +00:00
6a98131468
Consider this code snippet:
...
float t1(int argc) {
return (argc == 1123) ? 1.234f : 2.38213f;
}
We would generate truly awful code on ARM (those with a weak stomach should look
away):
_t1:
movw r1, #1123
movs r2, #1
movs r3, #0
cmp r0, r1
mov.w r0, #0
it eq
moveq r0, r2
movs r1, #4
cmp r0, #0
it ne
movne r3, r1
adr r0, #LCPI1_0
ldr r0, [r0, r3]
bx lr
The problem was that legalization was creating a cascade of SELECT_CC nodes, for
for the comparison of "argc == 1123" which was fed into a SELECT node for the ?:
statement which was itself converted to a SELECT_CC node. This is because the
ARM back-end doesn't have custom lowering for SELECT nodes, so it used the
default "Expand".
I added a fairly simple "LowerSELECT" to the ARM back-end. It takes care of this
testcase, but can obviously be expanded to include more cases.
Now we generate this, which looks optimal to me:
_t1:
movw r1, #1123
movs r2, #0
cmp r0, r1
adr r0, #LCPI0_0
it eq
moveq r2, #4
ldr r0, [r0, r2]
bx lr
.align 2
LCPI0_0:
.long 1075344593 @ float 2.382130e+00
.long 1067316150 @ float 1.234000e+00
llvm-svn: 110799
2010-08-11 08:43:16 +00:00
5190f09291
Report error if codegen tries to instantiate a ARM target when the cpu does support it. e.g. cortex-m* processors.
...
llvm-svn: 110798
2010-08-11 07:17:46 +00:00
40921a4e62
Add ARM Archv6M and let it implies FeatureDB (having dmb, etc.)
...
llvm-svn: 110795
2010-08-11 06:51:54 +00:00
188b47b214
MC/ARM: Add basic support for handling predication by parsing it out of the mnemonic into a separate operand form.
...
llvm-svn: 110794
2010-08-11 06:37:20 +00:00
49e02fc414
Add Cortex-M0 support. It's a ARMv6m device (no ARM mode) with some 32-bit
...
instructions: dmb, dsb, isb, msr, and mrs.
llvm-svn: 110786
2010-08-11 06:30:38 +00:00
6e809de90c
- Add subtarget feature -mattr=+db which determine whether an ARM cpu has the
...
memory and synchronization barrier dmb and dsb instructions.
- Change instruction names to something more sensible (matching name of actual
instructions).
- Added tests for memory barrier codegen.
llvm-svn: 110785
2010-08-11 06:22:01 +00:00
79937dfc5b
Update test to match output of optimize compares for ARM.
...
llvm-svn: 110765
2010-08-11 01:05:02 +00:00
f7495f286a
When analyzing loop exit conditions combined with and and or, don't
...
make any assumptions about when the two conditions will agree on when
to permit the loop to exit. This fixes PR7845.
llvm-svn: 110758
2010-08-11 00:12:36 +00:00
871d4e1170
The optimize comparisons pass removes the "cmp" instruction this is checking for.
...
llvm-svn: 110739
2010-08-10 22:16:05 +00:00
3ec892c167
Add test for recent instcombine vector shuffle enhancement
...
llvm-svn: 110737
2010-08-10 21:58:00 +00:00
18cc4acb00
tests: Don't error out if HOME isn't present in t the environment.
...
llvm-svn: 110711
2010-08-10 19:36:25 +00:00
3f251fb26e
Re-apply r110655 with fixes. Epilogue must restore sp from fp if the function stack frame has a var-sized object.
...
Also added a test case to check for the added benefit of this patch: it's optimizing away the unnecessary restore of sp from fp for some non-leaf functions.
llvm-svn: 110707
2010-08-10 19:30:19 +00:00
0dd47bfca3
Revert r110655, "Fix ARM hasFP() semantics. It should return true whenever FP
...
register is", it breaks a couple test-suite tests.
llvm-svn: 110701
2010-08-10 18:32:02 +00:00
d215976208
MC/AsmParser: Fix a bug in macro argument parsing, which was dropping
...
parentheses from argument lists.
llvm-svn: 110692
2010-08-10 17:38:52 +00:00
5730846c2f
Fix test for more architectures. Patch by Tobias Grosser.
...
llvm-svn: 110685
2010-08-10 16:48:24 +00:00
7fbe6cb429
RegionInfo: Do not assert if a BB is not part of the dominance tree.
...
llvm-svn: 110665
2010-08-10 09:54:35 +00:00
fedeff8015
Fix failing testcase.
...
Those look like typos to me.
llvm-svn: 110664
2010-08-10 09:54:29 +00:00
b219746c80
Handle TAG_constant for integers.
...
llvm-svn: 110656
2010-08-10 07:11:13 +00:00
8d5d1c1331
Fix ARM hasFP() semantics. It should return true whenever FP register is
...
reserved, not available for general allocation. This eliminates all the
extra checks for Darwin.
This change also fixes the use of FP to access frame indices in leaf
functions and cleaned up some confusing code in epilogue emission.
llvm-svn: 110655
2010-08-10 06:26:49 +00:00
f99e7e6643
PR7853: fix a silly mistake introduced in r101899, and add a test to make sure
...
it doesn't regress again.
llvm-svn: 110597
2010-08-09 20:49:43 +00:00
999da1f3a0
Have SPU handle halfvec stores aligned by 8 bytes.
...
llvm-svn: 110576
2010-08-09 16:33:00 +00:00
cc4a9670d3
XFAIL for mingw that has no plugins.
...
llvm-svn: 110574
2010-08-09 15:14:06 +00:00
7f36ac54d7
Reject unrepresentable pointer types in intrinsics. Fixes PR7316.
...
llvm-svn: 110541
2010-08-08 06:12:09 +00:00
8aa19b05ee
Use %shlibext instead of .so
...
llvm-svn: 110529
2010-08-08 00:55:59 +00:00
92a4a833f9
Move the bugpoint test passes to a plugin in preparation for having bugpoint
...
use opt.
llvm-svn: 110520
2010-08-07 21:48:09 +00:00
a3bd31a923
Use sdmem and sse_load_f64 (etc.) for the vector
...
form of CMPSD (etc.) Matching a 128-bit memory
operand is wrong, the instruction uses only 64 bits
(same as ADDSD etc.) 8193553.
llvm-svn: 110491
2010-08-07 00:33:42 +00:00
5afa738d7f
Test case for r110459. Radar 8264751. Test case by Fariborz Jahanian!
...
llvm-svn: 110467
2010-08-06 19:02:24 +00:00
e68958fcdf
Implement a proper getModRefInfo for va_arg.
...
llvm-svn: 110458
2010-08-06 18:24:38 +00:00
027d5bcf89
Fix eabi calling convention when a 64 bit value shadows r3.
...
Without this what was happening was:
* R3 is not marked as "used"
* ARM backend thinks it has to save it to the stack because of vaarg
* Offset computation correctly ignores it
* Offsets are wrong
llvm-svn: 110446
2010-08-06 15:35:32 +00:00
e1fb772aa5
Add an option to always emit realignment code for a particular module.
...
llvm-svn: 110404
2010-08-05 23:57:43 +00:00
884dd752c3
Implement AccessesArguments checking in the two-callsite form
...
of BasicAA::getModRefInfo. This allows BasicAA to say that two
memset calls to non-aliasing memory locations don't interfere.
llvm-svn: 110393
2010-08-05 23:34:50 +00:00
26ef7c7ab7
Fix memdep's code for reasoning about dependences between two calls. A Ref
...
response from getModRefInfo is not useful here. Instead, check for identical
calls only in the NoModRef case.
Reapply r110270, and strengthen it to compensate for the memdep changes.
When both calls are readonly, there is no dependence between them.
llvm-svn: 110382
2010-08-05 22:09:15 +00:00
cc3f3b341d
Move x86 specific tests into test/CodeGen/X86.
...
llvm-svn: 110372
2010-08-05 20:25:37 +00:00
72de307116
Add an ARM RSCrr instruction for disassembly only.
...
Partial fix for PR7792.
llvm-svn: 110361
2010-08-05 18:59:36 +00:00
adb93e56a3
Add an ARM RSBrr instruction for disassembly only.
...
Partial fix for PR7792.
llvm-svn: 110358
2010-08-05 18:23:43 +00:00
c53ee449a5
Move x86-specific tests out of test/Transforms/LoopStrengthReduce and
...
into test/CodeGen/X86, so that they aren't run when the x86 target is
not enabled.
Fix uglygep.ll to not be x86-specific.
llvm-svn: 110343
2010-08-05 17:04:15 +00:00
e62e664656
tests: CodeGen/X86/GC tests require X86.
...
llvm-svn: 110338
2010-08-05 15:45:33 +00:00
57e3f71538
tests: Mark MC/AsmParser tests as requiring x86 for now -- almost all of them
...
rely on using a specific x86 triple to test what they want to test.
llvm-svn: 110337
2010-08-05 15:44:15 +00:00
5bca58a290
check-lit was failing again on F13 64 bits :-(
...
llvm-svn: 110311
2010-08-05 03:35:01 +00:00
554b012f67
Revert r110270 for now. It appears to uncover a memdep bug.
...
llvm-svn: 110293
2010-08-05 00:43:10 +00:00
97886d59d1
ARM "rrx" shift operands do not have an immediate. PR7790.
...
llvm-svn: 110292
2010-08-05 00:34:42 +00:00
109561845b
The trouble with testing for "ModRef" and "NoModRef" is that
...
one is a suffix of the other, and FileCheck accepts superstrings.
Adjust the output to avoid this problem.
llvm-svn: 110280
2010-08-04 23:37:55 +00:00
ca1cb13646
The lower invoke pass needs to have unreachable code elimination run after it
...
because it could create such things. This fixes a MingW buildbot test failure.
llvm-svn: 110279
2010-08-04 23:36:02 +00:00
bd33dab633
The two-callsite form of AliasAnalysis::getModRefInfo is documented
...
to return Ref if the left callsite only reads memory read or written
by the right callsite; fix BasicAliasAnalysis to implement this.
Add AliasAnalysisEvaluator support for testing the two-callsite
form of getModRefInfo.
llvm-svn: 110270
2010-08-04 22:56:29 +00:00
39d0f57cab
PR7814: Truncates cannot be ignored for signed comparisons.
...
llvm-svn: 110268
2010-08-04 22:40:58 +00:00
49af1ebf2e
Test case for r110250. Radar 8264670. Test case by Fariborz Jahanian!
...
llvm-svn: 110254
2010-08-04 22:05:38 +00:00
26feb849a4
Testcase for r110248.
...
llvm-svn: 110249
2010-08-04 21:56:30 +00:00
5c1f56b78f
Test case for combination of r110234 & r110235.
...
llvm-svn: 110238
2010-08-04 18:42:46 +00:00
6786a04d0d
These tests are no longer stored in *CVS*.
...
llvm-svn: 110201
2010-08-04 15:58:01 +00:00
cba0d06b7c
call-imm.ll test case regex fix. Patch by Dimitry Andric!
...
llvm-svn: 110199
2010-08-04 15:31:35 +00:00
8b2f70125f
Make SPU backend handle insertelement and
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store for "half vectors"
llvm-svn: 110198
2010-08-04 13:59:48 +00:00
79daf7e0ae
Combine NEON VABD (absolute difference) intrinsics with ADDs to make VABA
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(absolute difference with accumulate) intrinsics. Radar 8228576.
llvm-svn: 110170
2010-08-04 00:12:08 +00:00
3619660529
Make instcombine set explicit alignments on load or store
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instructions with alignment 0, so that subsequent passes don't
need to bother checking the TargetData ABI size manually.
llvm-svn: 110128
2010-08-03 18:20:32 +00:00
011ff9bec9
OK, that's it. This test is going away now. But don't worry, I am taking it to a
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nice farm in the country where it can play with other tests. And bunnies.
It is not clear what is being tested, and the revision history shows a bunch of
random changes to the expected instruction count. Clearly, we are just fudging
it to pass whenever it fails.
llvm-svn: 110118
2010-08-03 17:21:14 +00:00
ddaaf40d24
Add an atomic lowering pass
...
llvm-svn: 110113
2010-08-03 16:19:16 +00:00
54cfd42c33
MC: Fix symbol fragment offsets in COFF.
...
Patch by Cameron Esfahani!
llvm-svn: 110104
2010-08-03 05:02:46 +00:00
d32764c8a0
Revert "MC: Fix symbol fragment offsets in COFF."
...
This reverts commit r110100
Wrong path caps.
llvm-svn: 110103
2010-08-03 04:53:28 +00:00
cf3d8b4ec4
MC: Fix symbol fragment offsets in COFF.
...
Patch by Cameron Esfahani!
llvm-svn: 110100
2010-08-03 04:43:24 +00:00
460a356bf6
Diabolical hack to make a test compatible with clang. (Thanks to Dale!) Radar 8246180.
...
llvm-svn: 110081
2010-08-02 23:29:03 +00:00
d8968da2c5
Add a lint check for indirectbr with no successors.
...
llvm-svn: 110074
2010-08-02 23:06:43 +00:00
0e6e8858ff
Testcase for r110043. Radar 8246180.
...
llvm-svn: 110070
2010-08-02 22:09:53 +00:00
77558b7d13
More SPU v2f32 stuff added: insertelement and shuffle.
...
llvm-svn: 110038
2010-08-02 11:22:10 +00:00
68b3886678
Add preliminary v2f32 support for SPU. Like with v2i32, we just
...
duplicate the instructions and operate on half vectors.
Also reorder code in SPUInstrInfo.td for better coherency.
llvm-svn: 110037
2010-08-02 10:25:47 +00:00
8f306a779b
Re-apply the infamous r108614, with a fix pointed out by Dirk Steinke.
...
llvm-svn: 110036
2010-08-02 09:32:13 +00:00
622f8eb981
Add preliminary v2i32 support for SPU backend. As there are no
...
such registers in SPU, this support boils down to "emulating"
them by duplicating instructions on the general purpose registers.
This adds the most basic operations on v2i32: passing parameters,
addition, subtraction, multiplication and a few others.
llvm-svn: 110035
2010-08-02 08:54:39 +00:00
1465d7cffa
Fix comment.
...
llvm-svn: 110006
2010-08-02 01:25:20 +00:00
5eeae48783
tests: Kill off custom targets which were just there for TestRunner.sh.
...
llvm-svn: 110003
2010-08-02 00:52:44 +00:00
4b77d23d40
tests: Deprecate TestRunner.sh, and have it just invoke 'llvm-lit' (which will
...
need to be in your path). Please move to using 'llvm-lit' if you are still using
TestRunner.sh.
llvm-svn: 110002
2010-08-02 00:52:41 +00:00
7595ce05a2
PR7781: Fix incorrect shifting in PPCTargetLowering::LowerBUILD_VECTOR.
...
llvm-svn: 109998
2010-08-02 00:18:19 +00:00
b1af605e58
tests: Make 'lit' the default test tool. You can still use 'make check-dg' to
...
run the tests using DejaGNU, but not for much longer. This is a last call for
DejaGNU supporters, if no one complains soon the DejaGNU support is going to
die.
llvm-svn: 109997
2010-08-02 00:05:18 +00:00
1b2bc1b844
PR7774: Fix undefined shifts in Alpha backend. As a bonus, this actually
...
improves the generated code in some cases.
llvm-svn: 109985
2010-08-01 21:13:28 +00:00
66161f5eb4
Revert new AVX intrinsic tests. They are breaking buildbots and Bruno is
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away from a computer now.
--- Reverse-merging r109881 into '.':
D test/CodeGen/X86/avx-intrinsics-x86.ll
D test/CodeGen/X86/avx-intrinsics-x86_64.ll
llvm-svn: 109959
2010-07-31 22:36:03 +00:00
0b636a24c7
Speculatively revert r108614, "Another attempt at getting the clang self-host to
...
like my instcombine patch.", in an attempt to fix Clang i386 bootstrap.
- Also PR7719.
llvm-svn: 109953
2010-07-31 19:51:11 +00:00
cd5fc7bef1
Add support for disassembling VMVN (immediate) instructions. PR7747.
...
llvm-svn: 109946
2010-07-31 05:57:44 +00:00
cf0287e56d
PPC doesn't supported VLA with large alignment. This was
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formerly rejected by the FE, so asserted in the BE; now the FE only
warns, so we treat it as a legitimate fatal error in PPC BE.
This means the test for the feature won't pass, so it's xfail'd.
llvm-svn: 109892
2010-07-30 21:09:48 +00:00
92941fdb26
A *bunch* of tests for AVX intrinsics
...
llvm-svn: 109881
2010-07-30 19:57:56 +00:00
964179cb58
Attempt to fix the llvm-gcc-powerpc-darwin9 buildbot.
...
llvm-svn: 109876
2010-07-30 18:52:47 +00:00
ffe64c06ef
Fix for bug reported by Evzen Muller on llvm-commits: make sure to correctly
...
check the range of the constant when optimizing a comparison between a
constant and a sign_extend_inreg node.
llvm-svn: 109854
2010-07-30 06:44:31 +00:00
d343166a0b
Many Thumb2 instructions can reference the full ARM register set (i.e.,
...
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
llvm-svn: 109842
2010-07-30 02:41:01 +00:00
2e276485cb
Fix this up per llvm-gcc r109819.
...
llvm-svn: 109820
2010-07-29 23:20:29 +00:00
d9624e2d2e
Remove XFAIL, test doesn't leak anymore.
...
llvm-svn: 109801
2010-07-29 20:36:36 +00:00
2bff50546c
Implement vector constants which are splat of
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integers with mov + vdup. 8003375. This is
currently disabled by default because LICM will
not hoist a VDUP, so it pessimizes the code if
the construct occurs inside a loop (8248029).
llvm-svn: 109799
2010-07-29 20:10:08 +00:00
390914cbe8
Make GlobalValue alignment consistent with load, store, and alloca
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alignment, fixing silent truncation of alignment values.
llvm-svn: 109653
2010-07-28 20:56:48 +00:00
a7e5a24093
Define a maximum supported alignment value for load, store, and
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alloca instructions (constrained by their internal encoding),
and add error checking for it. Fix an instcombine bug which
generated huge alignment values (null is infinitely aligned).
This fixes undefined behavior noticed by John Regehr.
llvm-svn: 109643
2010-07-28 20:12:04 +00:00
53afc8f06a
Implement a vectorized algorithm for <16 x i8> << <16 x i8>
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This is about 4x faster and smaller than the existing scalarization.
llvm-svn: 109566
2010-07-28 00:21:48 +00:00
a7f1d4a2ba
Testcase for r109556. Radar 8198362.
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llvm-svn: 109557
2010-07-27 23:15:25 +00:00
269a6da023
~40% faster vector shl <4 x i32> on SSE 4.1 Larger improvements for smaller types coming in future patches.
...
For:
define <2 x i64> @shl(<4 x i32> %r, <4 x i32> %a) nounwind readnone ssp {
entry:
%shl = shl <4 x i32> %r, %a ; <<4 x i32>> [#uses=1]
%tmp2 = bitcast <4 x i32> %shl to <2 x i64> ; <<2 x i64>> [#uses=1]
ret <2 x i64> %tmp2
}
We get:
_shl: ## @shl
pslld $23, %xmm1
paddd LCPI0_0, %xmm1
cvttps2dq %xmm1, %xmm1
pmulld %xmm1, %xmm0
ret
Instead of:
_shl: ## @shl
pshufd $3, %xmm0, %xmm2
movd %xmm2, %eax
pshufd $3, %xmm1, %xmm2
movd %xmm2, %ecx
shll %cl, %eax
movd %eax, %xmm2
pshufd $1, %xmm0, %xmm3
movd %xmm3, %eax
pshufd $1, %xmm1, %xmm3
movd %xmm3, %ecx
shll %cl, %eax
movd %eax, %xmm3
punpckldq %xmm2, %xmm3
movd %xmm0, %eax
movd %xmm1, %ecx
shll %cl, %eax
movd %eax, %xmm2
movhlps %xmm0, %xmm0
movd %xmm0, %eax
movhlps %xmm1, %xmm1
movd %xmm1, %ecx
shll %cl, %eax
movd %eax, %xmm0
punpckldq %xmm0, %xmm2
movdqa %xmm2, %xmm0
punpckldq %xmm3, %xmm0
ret
llvm-svn: 109549
2010-07-27 22:37:06 +00:00
bd32256e25
Update tests to not rely on input file's absolute path.
...
llvm-svn: 109521
2010-07-27 18:13:53 +00:00
317b969ac5
Fix a crash in the dag combiner caused by ConstantFoldBIT_CONVERTofBUILD_VECTOR calling itself
...
recursively and returning a SCALAR_TO_VECTOR node, but assuming the input was always a BUILD_VECTOR.
llvm-svn: 109519
2010-07-27 18:02:18 +00:00
731b079edb
Make coff-dump.py executable and add python as executable for this script.
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This fixes the MC/COFF/basic-coff.ll test case.
llvm-svn: 109497
2010-07-27 09:01:26 +00:00
f8270bdb2d
Make MC use Windows COFF on Windows and add tests.
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llvm-svn: 109494
2010-07-27 06:46:15 +00:00
6bcea068db
Currently EH lowering code expects typeinfo to be global only.
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This assumption is not satisfied due to global mergeing.
Workaround the issue by temporary disablinge mergeing of const globals.
Also, ignore LLVM "special" globals. This fixes PR7716
llvm-svn: 109423
2010-07-26 18:45:39 +00:00
bb4c4b59a4
Fix a test with malformed IR. Not sure why this didn't fail before.
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llvm-svn: 109422
2010-07-26 18:44:56 +00:00
cd83870faf
Fix SCEVExpander::visitAddRecExpr so that it remembers the induction variable
...
it inserted rather than using LoopInfo::getCanonicalInductionVariable to
rediscover it, since that doesn't work on non-canonical loops. This fixes
infinite recurrsion on such loops; PR7562.
llvm-svn: 109419
2010-07-26 18:28:14 +00:00
b0961f2443
Avoid depending on LCSSA implicitly pulling in LoopSimplify.
...
llvm-svn: 109410
2010-07-26 18:00:43 +00:00
306a1f9721
Support x86 "eiz" and "riz" pseudo index registers in the assembler.
...
llvm-svn: 109295
2010-07-24 00:06:39 +00:00
fbd7f65248
Consolidate the ELF section directive tests into a single file as
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suggested by Chris Lattner.
llvm-svn: 109290
2010-07-23 23:40:41 +00:00
df907f4594
- Allow target to specify when is register pressure "too high". In most cases,
...
it's too late to start backing off aggressive latency scheduling when most
of the registers are in use so the threshold should be a bit tighter.
- Correctly handle live out's and extract_subreg etc.
- Enable register pressure aware scheduling by default for hybrid scheduler.
For ARM, this is almost always a win on # of instructions. It's runtime
neutral for most of the tests. But for some kernels with high register
pressure it can be a huge win. e.g. 464.h264ref reduced number of spills by
54 and sped up by 20%.
llvm-svn: 109279
2010-07-23 22:39:59 +00:00
6f38011196
Move AVX encoding tests to different files
...
llvm-svn: 109269
2010-07-23 21:25:26 +00:00
55e244698a
Use the proper type for shift counts. This fixes a bootstrap error.
...
llvm-svn: 109265
2010-07-23 21:08:12 +00:00
caf8e3a2db
Test case to insure template function declaration refers to correct filename. Radar 8063111.
...
llvm-svn: 109258
2010-07-23 20:15:49 +00:00
ea0e05a3ce
Add AVX version of CLMUL instructions
...
llvm-svn: 109248
2010-07-23 18:41:12 +00:00
0818684a70
DAGCombine (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits
...
are not demanded. This often allows the anyext to be folded away.
llvm-svn: 109242
2010-07-23 18:03:30 +00:00
acd9230b1b
Add complete assembler support for FMA3 instructions, with descriptions and encodings taken from the AVX manual
...
llvm-svn: 109204
2010-07-23 00:54:35 +00:00
0710c74f29
Add remaining AVX instructions (most of them dealing with GR64 destinations. This complete the assembler support for the general AVX ISA. But we still miss instructions from FMA3 and CLMUL specific feature flags, which are now the next step
...
llvm-svn: 109168
2010-07-22 21:18:49 +00:00
336734aca6
Add new RegionInfo pass.
...
The RegionInfo pass detects single entry single exit regions in a function,
where a region is defined as any subgraph that is connected to the remaining
graph at only two spots.
Furthermore an hierarchical region tree is built.
Use it by calling "opt -regions analyze" or "opt -view-regions".
llvm-svn: 109089
2010-07-22 07:46:31 +00:00
9a77382685
Custom lower the memory barrier instructions and add support
...
for lowering without sse2. Add a couple of new testcases.
Fixes a few libgomp tests and latent bugs. Remove a few todos.
llvm-svn: 109078
2010-07-22 02:48:34 +00:00
285903853f
More register pressure aware scheduling work.
...
llvm-svn: 109064
2010-07-21 23:53:58 +00:00
e3acfd4d58
Add more 256-bit forms for a bunch of regular AVX instructions
...
Add 64-bit (GR64) versions of some instructions (which are not
described in their SSE forms, but are described in AVX)
llvm-svn: 109063
2010-07-21 23:53:50 +00:00
84bdfd80df
Baby steps towards ARM fast-isel.
...
llvm-svn: 109047
2010-07-21 22:26:11 +00:00
6238c1d102
Add missing AVX convert instructions. Those instructions are not described in their SSE forms (although they exist), but add the AVX forms anyway, so the assembler can benefit from it
...
llvm-svn: 109039
2010-07-21 21:37:59 +00:00
093cb79d4b
Disallow null as a named metadata operand.
...
Make MDNode::destroy private.
Fix the one thing that used MDNode::destroy, outside of MDNode itself.
One should never delete or destroy an MDNode explicitly. MDNodes
implicitly go away when there are no references to them (implementation
details aside).
llvm-svn: 109028
2010-07-21 18:54:18 +00:00
4277e14dc4
Fix calling convention on ARM if vfp2+ is enabled.
...
llvm-svn: 109009
2010-07-21 11:38:30 +00:00
cdbec62510
Add AVX only vzeroall and vzeroupper instructions
...
llvm-svn: 109002
2010-07-21 08:56:24 +00:00
690aa72437
Turn this test on again after the llvm-gcc change in r108986.
...
llvm-svn: 108987
2010-07-21 04:54:06 +00:00
8d95d26eb1
Update this to use a "valid" alignment.
...
llvm-svn: 108985
2010-07-21 04:51:24 +00:00
3499934da6
Add new AVX vpermilps, vpermilpd and vperm2f128 instructions
...
llvm-svn: 108984
2010-07-21 03:07:42 +00:00
3ceaf7a0a2
Add new AVX vmaskmov instructions, and also fix the VEX encoding bits to support it
...
llvm-svn: 108983
2010-07-21 02:46:58 +00:00
e706501975
Add new AVX vextractf128 instructions
...
llvm-svn: 108964
2010-07-20 23:19:02 +00:00
c3eb5e3d4b
Include some tests for the recently committed ELF section directive
...
handlers.
llvm-svn: 108938
2010-07-20 21:37:30 +00:00
3f696ff489
Testcase for llvm-gcc commit r108910.
...
llvm-svn: 108918
2010-07-20 20:32:47 +00:00
3b505848fd
Add new AVX instruction vinsertf128
...
llvm-svn: 108892
2010-07-20 19:44:51 +00:00
625fd2292d
Fix SCEV denormalization of expressions where the exit value from
...
one loop is involved in the increment of an addrec for another
loop. This fixes rdar://8168938.
llvm-svn: 108863
2010-07-20 17:06:20 +00:00
badf087e45
update tests for smarter BIC usage
...
llvm-svn: 108846
2010-07-20 16:16:48 +00:00
2e839de377
The same problem was being tracked in PR7652.
...
llvm-svn: 108843
2010-07-20 15:52:32 +00:00
160695fecb
Fix PR7174, a couple o Mips fixes:
...
- Fix a typo for PIC check during jmp table lowering
- Also fix the "first jump table basic block is not
considered only reachable by fall through" problem, use this
ad-hoc solution until I come up with something better.
Patch by stetorvs@gmail.com
llvm-svn: 108820
2010-07-20 08:37:04 +00:00
ea7863647b
Fix Mips PR7473. Patch by stetorvs@gmail.com
...
llvm-svn: 108816
2010-07-20 07:58:51 +00:00
6c8041ea34
x86_32 tests for vbroadcast
...
llvm-svn: 108789
2010-07-20 00:11:50 +00:00
14c5fd437c
Add AVX vbroadcast new instruction
...
llvm-svn: 108788
2010-07-20 00:11:13 +00:00
9de0ca73d4
Add 256-bit vaddsub, vhadd, vhsub, vblend and vdpp instructions!
...
llvm-svn: 108769
2010-07-19 23:32:44 +00:00
b5e918dc05
After a custom inserter, in a block which has constant instructions,
...
update the current basic block in addition to the current insert
position, so that they remain consistent. This fixes rdar://8204072.
llvm-svn: 108765
2010-07-19 22:48:56 +00:00
9db7d0addd
X86: Mark JMP{32,64}[mr] as requires 32-bit/64-bit mode. They are the same
...
instruction, we only want to allow the one for the current subtarget.
- This also fixes suffix matching for jmp instructions, because it eliminates
the ambiguity between 'jmpl' and 'jmpq'.
llvm-svn: 108746
2010-07-19 20:44:16 +00:00
d4e389441d
Testcase for 108732 (8195660).
...
llvm-svn: 108733
2010-07-19 18:22:40 +00:00
18efced1a2
Fix PR 7662.
...
Do not try to insert local variable info to a DIE used for function declaration.
llvm-svn: 108731
2010-07-19 17:53:55 +00:00
3ccd81864f
Testcase for r108687.
...
llvm-svn: 108689
2010-07-19 08:14:26 +00:00
9c271e2835
Remove r108639 now that it is handled by InstCombine instead.
...
llvm-svn: 108688
2010-07-19 08:10:24 +00:00
9aefb8ee4c
X86-64: Mark WINCALL and more tail call instructions as code gen only.
...
llvm-svn: 108685
2010-07-19 07:21:07 +00:00
b82cd9319b
MC/X86: We now match instructions like "incl %eax" correctly for the arch we are
...
assembling; remove crufty custom cleanup code.
llvm-svn: 108681
2010-07-19 06:14:54 +00:00
af75e1923c
tests: Force another triple.
...
llvm-svn: 108666
2010-07-19 00:43:58 +00:00
3b4621103a
tests: Force triples.
...
llvm-svn: 108658
2010-07-18 21:16:10 +00:00
40a564f09f
MC/AsmParser: Fix .abort and .secure_log_unique to accept arbitrary token
...
sequences, not just strings.
llvm-svn: 108655
2010-07-18 20:15:59 +00:00
6fb1c3ad8a
MC/AsmParser: Add macro argument substitution support.
...
llvm-svn: 108654
2010-07-18 19:00:10 +00:00
4323571efb
MC/AsmParser: Add basic support for macro instantiation.
...
llvm-svn: 108653
2010-07-18 18:54:11 +00:00
c1f58ec83c
MC/AsmParser: Add basic parsing support for .macro definitions.
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llvm-svn: 108652
2010-07-18 18:47:21 +00:00
ede90a2a58
daniel doesn't hate me, he hates macpython 2.5, which
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is a very reasonable position on life!
llvm-svn: 108650
2010-07-18 18:42:18 +00:00
828984ff4e
MC/AsmParser: Add .macros_{off,on} support, not that makes sense since we don't
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support macros.
llvm-svn: 108649
2010-07-18 18:38:02 +00:00
41670a11a8
Add a testcase for r108639.
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llvm-svn: 108640
2010-07-18 08:57:19 +00:00
7d2818b073
Another attempt at getting the clang self-host to like my instcombine patch.
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llvm-svn: 108614
2010-07-17 06:56:35 +00:00
b97e2bbe32
Add combiner patterns to more effectively utilize the BFI (bitfield insert)
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instruction for non-constant operands. This includes the case referenced
in the README.txt regarding a bitfield copy.
llvm-svn: 108608
2010-07-17 03:30:54 +00:00
ceb16a5ce9
Test for ELF .size directive.
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llvm-svn: 108607
2010-07-17 03:15:24 +00:00
11013eda5a
Add basic support to code-gen the ARM/Thumb2 bit-field insert (BFI) instruction
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and a combine pattern to use it for setting a bit-field to a constant
value. More to come for non-constant stores.
llvm-svn: 108570
2010-07-16 23:05:05 +00:00
bf8370ff36
Consider this function:
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void foo() { __builtin_unreachable(); }
It will output the following on Darwin X86:
_func1:
Leh_func_begin0:
pushq %rbp
Ltmp0:
movq %rsp, %rbp
Ltmp1:
Leh_func_end0:
This prolog adds a new Call Frame Information (CFI) row to the FDE with an
address that is not within the address range of the code it describes -- part is
equal to the end of the function -- and therefore results in an invalid EH
frame. If we emit a nop in this situation, then the CFI row is now within the
address range.
llvm-svn: 108568
2010-07-16 22:51:10 +00:00
c30b4ddc58
Remove the X86::FP_REG_KILL pseudo-instruction and the X86FloatingPointRegKill
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pass that inserted it.
It is no longer necessary to limit the live ranges of FP registers to a single
basic block.
llvm-svn: 108536
2010-07-16 17:41:44 +00:00
50729ad717
Feed the right output into FileCheck.
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llvm-svn: 108523
2010-07-16 10:58:02 +00:00
375efe3157
Arrays and vectors with different numbers of elements are not equivalent.
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llvm-svn: 108517
2010-07-16 06:31:12 +00:00
3d84c9c793
LoopSimplify does not update domfrontier correctly.
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This fixes PR7649.
llvm-svn: 108513
2010-07-16 05:59:45 +00:00
37c42a3d02
Remove many calls to TII::isMoveInstr. Targets should be producing COPY anyway.
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TII::isMoveInstr is going tobe completely removed.
llvm-svn: 108507
2010-07-16 04:45:42 +00:00
b1671271ab
Add forgotten test case.
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llvm-svn: 108506
2010-07-16 04:45:35 +00:00
103c4ebea5
Use the source-order scheduler instead of the "fast" scheduler at -O0,
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because it's more likely to keep debug line information in its original
order.
llvm-svn: 108496
2010-07-16 02:01:19 +00:00
15a81cddb4
Also revert 108422, it's causing some test failures.
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Working on testcases for Owen.
llvm-svn: 108494
2010-07-16 01:36:12 +00:00
c6eefe4d4e
Fix this test.
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llvm-svn: 108491
2010-07-16 01:28:45 +00:00
bfd4fd7bb7
The SelectionDAGBuilder's handling of debug info, on rare
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occasions, caused code to be generated in a different order.
All cases I've seen involved float softening in the type
legalizer, and this could be perhaps be fixed there, but
it's better not to generate things differently in the first
place. 7797940 (6/29/2010..7/15/2010).
llvm-svn: 108484
2010-07-16 00:02:08 +00:00
4bda1c8e68
Revert. This isn't the correct way to go.
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llvm-svn: 108478
2010-07-15 23:42:21 +00:00
fbbdfcaea7
Fix the order that SCEVExpander considers add operands in so that
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it doesn't miss an opportunity to form a GEP, regardless of the
relative loop depths of the operands. This fixes rdar://8197217.
llvm-svn: 108475
2010-07-15 23:38:13 +00:00
973dc3b1d8
Handle code gen for the unreachable instruction if it's the only instruction in
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the function. We'll just turn it into a "trap" instruction instead.
The problem with not handling this is that it might generate a prologue without
the equivalent epilogue to go with it:
$ cat t.ll
define void @foo() {
entry:
unreachable
}
$ llc -o - t.ll -relocation-model=pic -disable-fp-elim -unwind-tables
.section __TEXT,__text,regular,pure_instructions
.globl _foo
.align 4, 0x90
_foo: ## @foo
Leh_func_begin0:
## BB#0: ## %entry
pushq %rbp
Ltmp0:
movq %rsp, %rbp
Ltmp1:
Leh_func_end0:
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The unwind tables then have bad data in them causing all sorts of problems.
Fixes <rdar://problem/8096481>.
llvm-svn: 108473
2010-07-15 23:32:40 +00:00
55f0c6b9fc
Split -enable-finite-only-fp-math to two options:
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-enable-no-nans-fp-math and -enable-no-infs-fp-math. All of the current codegen fp math optimizations only care whether the fp arithmetics arguments and results can never be NaN.
llvm-svn: 108465
2010-07-15 22:07:12 +00:00
60b131654b
fix the definitions of ConstTextCoalSection/ConstDataCoalSection
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to keep "Text" in sync with the "pure instructions" section attribute.
Lack of this attribute was preventing the assembler from emitting
multibyte noops instructions for templates (and inlines, and other
coalesced stuff) and was causing the assembler to mismatch .o files.
This fixes rdar://8018335
llvm-svn: 108461
2010-07-15 21:22:00 +00:00
df09db62e2
Fix crash reported in PR7653.
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llvm-svn: 108441
2010-07-15 18:45:27 +00:00
4afd412d6b
Watch out for a constant offset cancelling out a base register, forming
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a zero. This situation arrises in Fortran code with induction variables
that start at 1 instead of 0. This fixes PR7651.
llvm-svn: 108424
2010-07-15 15:14:45 +00:00
Mikhail Glushenkov