b89805c77d
Add HasAVX predicate to some of the AVX patterns.
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llvm-svn: 147769
2012-01-09 08:34:00 +00:00
a51f7f75c2
Reorder a bunch of patterns to put the AVX version first thus giving it priority over the SSE version. Another step towards trying to remove the AVX hack that disables SSE from X86Subtarget.
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llvm-svn: 147768
2012-01-09 08:10:38 +00:00
ef7f5bf8c9
Clean up patterns for MOVNT*. Not sure why there were floating point types on MOVNTPS and MOVNTDQ. And v4i64 was completely missing.
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llvm-svn: 147767
2012-01-09 06:52:46 +00:00
c1f5622ad3
Mark MOVNTI as being supported in SSE2 OR AVX mode. This instruction has no AVX equivalent so we should use the SSE version.
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llvm-svn: 147766
2012-01-09 06:38:55 +00:00
a081644f8a
Move SSE2 logical operations PAND/POR/PXOR/PANDN above SSE1 logical operations ANDPS/ORPS/XORPS/ANDNPS. This fixes a pattern ordering issue that meant that the SSE2 instructions could never be directly selected since the SSE1 patterns would always match first. This is largely moot with the ExeDepsFix pass, but I'm trying to audit for all such ordering issues.
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llvm-svn: 147765
2012-01-09 05:07:01 +00:00
210e4f81b3
Change some places that were checking for AVX OR SSE1/2 to use hasXMM/hasXMMInt instead. Also fix one place that checked SSE3, but accidentally excluded AVX to use hasSSE3orAVX. This is a step towards removing the AVX hack from the X86Subtarget.h
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llvm-svn: 147764
2012-01-09 02:28:15 +00:00
f28213ca01
Don't print an unused label before .cfi_endproc.
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llvm-svn: 147763
2012-01-09 00:17:29 +00:00
744f6311d3
Don't disable MMX support when AVX is enabled. Fix predicates for MMX instructions that were added along with SSE instructions to check for AVX in addition to SSE level.
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llvm-svn: 147762
2012-01-09 00:11:29 +00:00
c1ab7afec8
Enable FISTTP* instructions when AVX is enabled.
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llvm-svn: 147758
2012-01-08 23:04:21 +00:00
6609f741b9
Tweak my last commit to be less conservative about uses.
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We still save an instruction when just the "and" part is replaced.
Also change the code to match comments more closely.
llvm-svn: 147753
2012-01-08 21:12:51 +00:00
4882e488f7
Don't forget to transfer implicit uses of return instruction.
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llvm-svn: 147752
2012-01-08 20:41:16 +00:00
520730ff23
Avoid eraseing copies from a reserved register unless the definition can be
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safely proven not to have been clobbered. No small test case possible.
llvm-svn: 147751
2012-01-08 19:52:28 +00:00
da37e15345
InstCombine: If we have a bit test and a sign test anded/ored together, merge the sign bit into the bit test.
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This is common in bit field code, e.g. checking if the first or the last bit of a bit field is set.
llvm-svn: 147749
2012-01-08 18:32:24 +00:00
540651cf59
Reverted commit #147601 upon Evan's request.
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llvm-svn: 147748
2012-01-08 17:20:33 +00:00
81a6274e7c
Remove MCELFStreamer.h.
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llvm-svn: 147745
2012-01-07 23:18:39 +00:00
382412032c
Don't print a label before .cfi_startproc when we don't need to. This makes
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the produce assembly when using CFI just a bit more readable.
llvm-svn: 147743
2012-01-07 22:42:19 +00:00
083dbdca7f
Match SelectionDAG logic for enabling movt.
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Darwin doesn't do static, and ELF targets only support static.
llvm-svn: 147740
2012-01-07 20:49:15 +00:00
f210619d08
Fix typo in the X86 backend readme. Patch from Jaeden Amero.
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llvm-svn: 147739
2012-01-07 20:35:21 +00:00
6898db6269
Remove VectorExtras. This unused helper was written for a type of API that is discouraged now.
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llvm-svn: 147738
2012-01-07 19:42:13 +00:00
ca66bba45e
Remove unnecessary check of hasAVX(). It's already included in hasXMM().
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llvm-svn: 147734
2012-01-07 18:48:43 +00:00
0515cd41e4
Replace some uses of hasNUsesOfValue(0, X) with !hasAnyUseOfValue(X)
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llvm-svn: 147733
2012-01-07 18:31:09 +00:00
43a1bd6ac7
Add some DAG combines for SUBC/SUBE. If nothing uses the carry/borrow out of subc, turn it into a sub. Turn (subc x, x) into 0 with no borrow. Turn (subc x, 0) into x with no borrow. Turn (subc -1, x) into (xor x, -1) with no borrow. Turn sube with no borrow in into subc.
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llvm-svn: 147728
2012-01-07 09:06:39 +00:00
434fb37bb4
Optimize reserved register coalescing.
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Reserved registers don't have proper live ranges, their LiveInterval
simply has a snippet of liveness for each def. Virtual registers with a
single value that is a copy of a reserved register (typically %esp) can
be coalesced with the reserved register if the live range doesn't
overlap any reserved register defs.
When coalescing with a reserved register, don't modify the reserved
register live range. Just leave it as a bunch of dead defs. This
eliminates quadratic coalescer behavior in i386 functions with many
function calls.
PR11699
llvm-svn: 147726
2012-01-07 07:39:50 +00:00
a8879087b5
Use the 'regalloc' debug tag for most register allocator tracing.
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llvm-svn: 147725
2012-01-07 07:39:47 +00:00
06f6c05d08
Enable redundant phi elimination after LSR.
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This will be more important as we extend the LSR pass in ways that don't rely on the formula solver. In particular, we need it for constructing IV chains.
llvm-svn: 147724
2012-01-07 07:08:17 +00:00
8cdce7e690
Use getRegForValue() to materialize the address of ARM globals.
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This enables basic local CSE, giving us 20% smaller code for
consumer-typeset in -O0 builds.
<rdar://problem/10658692>
llvm-svn: 147720
2012-01-07 04:07:22 +00:00
6cc8d49885
Revert part of r147716. Looks like x87 instructions kill markers are all messed
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up so branch folding pass can't use the scavenger. :-( This doesn't breaks
anything currently. It just means targets which do not carefully update kill
markers cannot run post-ra scheduler (not new, it has always been the case).
We should fix this at some point since it's really hacky.
llvm-svn: 147719
2012-01-07 03:35:48 +00:00
732ad80dbb
LSR: Don't optimize loops if an outer loop has no preheader.
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LoopSimplify may not run on some outer loops, e.g. because of indirect
branches. SCEVExpander simply cannot handle outer loops with no preheaders.
Fixes rdar://10655343 SCEVExpander segfault.
llvm-svn: 147718
2012-01-07 03:16:50 +00:00
0708209642
Split Finish into Finish and FinishImpl to have a common place to do end of
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file error checking. Use that to error on an unfinished cfi_startproc.
The error is not nice, but is already better than a segmentation fault.
llvm-svn: 147717
2012-01-07 03:13:18 +00:00
00b1a3cd7e
Added a late machine instruction copy propagation pass. This catches
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opportunities that only present themselves after late optimizations
such as tail duplication .e.g.
## BB#1:
movl %eax, %ecx
movl %ecx, %eax
ret
The register allocator also leaves some of them around (due to false
dep between copies from phi-elimination, etc.)
This required some changes in codegen passes. Post-ra scheduler and the
pseudo-instruction expansion passes have been moved after branch folding
and tail merging. They were before branch folding before because it did
not always update block livein's. That's fixed now. The pass change makes
independently since we want to properly schedule instructions after
branch folding / tail duplication.
rdar://10428165
rdar://10640363
llvm-svn: 147716
2012-01-07 03:02:36 +00:00
501e3095e8
Copy implicit defs (e.g. r0) when changing tBX_RET to tPOP_RET. This bug is
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exposed with an upcoming change will would delete the copy to return register
because there is no use! It's amazing anything works.
llvm-svn: 147715
2012-01-07 02:55:54 +00:00
68f034ee1a
Use movw+movt in ARMFastISel::ARMMaterializeGV.
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This eliminates a lot of constant pool entries for -O0 builds of code
with many global variable accesses.
This speeds up -O0 codegen of consumer-typeset by 2x because the
constant island pass no longer has to look at thousands of constant pool
entries.
<rdar://problem/10629774>
llvm-svn: 147712
2012-01-07 01:47:05 +00:00
2ec61a896b
LSR: run DeleteDeadPhis before replaceCongruentPhis.
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llvm-svn: 147711
2012-01-07 01:36:44 +00:00
f730f39f3f
Cleanup comments and argument types related to my previous replaceCongruentPhis checkin.
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llvm-svn: 147709
2012-01-07 01:29:21 +00:00
5adedf5d47
Extended replaceCongruentPhis to handle mixed phi types.
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llvm-svn: 147707
2012-01-07 01:12:09 +00:00
c206d46709
Make the 'x' constraint work for AVX registers as well.
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Fixes rdar://10614894
llvm-svn: 147704
2012-01-07 01:02:09 +00:00
ff4e2b7d23
Missing raw_ostream.h breaks MSVC build.
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llvm-svn: 147703
2012-01-07 00:54:28 +00:00
881a776875
Expose isNonConstantNegative to users of ScalarEvolution.
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llvm-svn: 147700
2012-01-07 00:27:31 +00:00
73a3fab480
Add comment.
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llvm-svn: 147696
2012-01-06 23:45:47 +00:00
8ea8e4fc76
Add a comment and ensure that anyone else looking at this code doesn't start
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to bleed from the eyes.
llvm-svn: 147695
2012-01-06 23:03:37 +00:00
090fcc1a10
Use const vector references instead of a vector copy. Spotted by Devang.
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llvm-svn: 147694
2012-01-06 23:03:34 +00:00
5a28a6ee2f
Use -> instead of (*iter).
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llvm-svn: 147693
2012-01-06 23:03:27 +00:00
68a922c0e9
Enable aligned NEON spilling by default.
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Experiments show this to be a small speedup for modern ARM cores.
llvm-svn: 147689
2012-01-06 22:19:37 +00:00
9a5b242d3c
Put all IVUsers in the processed set. Allow querying IVUsers with isIVUserOrOperand.
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llvm-svn: 147686
2012-01-06 21:41:55 +00:00
690511137c
Abort AdjustBBOffsetsAfter early when possible.
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llvm-svn: 147685
2012-01-06 21:40:15 +00:00
b8045cbcb1
SCEVExpander: hoistStep should check strict dominance.
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llvm-svn: 147683
2012-01-06 21:23:43 +00:00
85460d0d32
Tracing to help investigate issues with SjLj spill code.
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llvm-svn: 147682
2012-01-06 21:16:27 +00:00
64dc8aa44f
Initializing to false makes better sense. Thanks, David.
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llvm-svn: 147679
2012-01-06 20:11:59 +00:00
a3d90a9467
Fix uninitialized variable warning.
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llvm-svn: 147676
2012-01-06 20:02:49 +00:00
6b64c3c683
Fix uninitialized variable warning.
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llvm-svn: 147675
2012-01-06 19:59:58 +00:00
Craig Topper