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Author SHA1 Message Date
Juergen Ributzka c611d72754 [FastISel][AArch64] Simplify mul to shift when possible. 
This is related to rdar://problem/18369687.

llvm-svn: 217980
 2014-09-17 20:35:41 +00:00
Juergen Ributzka addb75a4f3 [FastISel][AArch64] Use the correct register class to make the MI verifier happy. 
This is mostly achieved by providing the correct register class manually,
because getRegClassFor always returns the GPR*AllRegClass for MVT::i32 and
MVT::i64.

Also cleanup the code to use the FastEmitInst_* method whenever possible. This
makes sure that the operands' register class is properly constrained. For all
the remaining cases this adds the missing constrainOperandRegClass calls for
each operand.

llvm-svn: 216225
 2014-08-21 20:57:57 +00:00
Tim Northover fee2adefba AArch64: correctly fast-isel i8 & i16 multiplies 
We were asking for a register for type i8 or i16 which caused an assert.

rdar://problem/17620015

llvm-svn: 212718
 2014-07-10 14:18:46 +00:00