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183 Commits

Author SHA1 Message Date
Craig Topper c7de3a1018 [AVX512] Remove the intrinsic forms of VMOVSS/VMOVSD. We don't need two different forms of 'rr' and 'rm'. This matches SSE/AVX. 
I'm not convinced the patterns for the rm_Int was correct anyway. It had a tied source that should't exist for the unmasked version. The load form of MOVSS always zeros the most significant bits. I've left the patterns off the masked load instructions as I'm not sure what the correct pattern should be and we don't have any tests currently. Nor do we implement masked scalar load intrinsics in clang currently.

llvm-svn: 277098
 2016-07-29 02:49:08 +00:00
Craig Topper f4151bea72 [AVX512] Add initial support for the Execution Domain fixing pass to change some EVEX instructions. 
llvm-svn: 276393
 2016-07-22 05:00:52 +00:00
Craig Topper a6e6febe2c [AVX512] Remove masked logic op intrinsics and autoupgrade them to native IR. 
llvm-svn: 275155
 2016-07-12 05:27:53 +00:00
Craig Topper 70610cf7b6 [X86] Remove and autoupgrade 512-bit non-temporal store intrinsics. 
llvm-svn: 274966
 2016-07-09 04:38:27 +00:00
Matthias Braun 152e7c8b12 VirtRegMap: Replace some identity copies with KILL instructions. 
An identity COPY like this:
   %AL = COPY %AL, %EAX<imp-def>
has no semantic effect, but encodes liveness information: Further users
of %EAX only depend on this instruction even though it does not define
the full register.

Replace the COPY with a KILL instruction in those cases to maintain this
liveness information. (This reverts a small part of r238588 but this
time adds a comment explaining why a KILL instruction is useful).

llvm-svn: 274952
 2016-07-09 00:19:07 +00:00
Craig Topper f7bf6de0af [AVX512] Remove and autoupgrade a duplicate set of 512-bit masked shift intrinsics. 
I'm not sure if clang ever used these builtin names or not.

llvm-svn: 274827
 2016-07-08 06:14:47 +00:00
Michael Kuperstein 3e3652aef2 Recommit r274692 - [X86] Transform setcc + movzbl into xorl + setcc 
xorl + setcc is generally the preferred sequence due to the partial register
stall setcc + movzbl suffers from. As a bonus, it also encodes one byte smaller.
This fixes PR28146.

The original commit tried inserting an 8bit-subreg into a GR32 (not GR32_ABCD)
which was not appreciated by fast regalloc on 32-bit.

llvm-svn: 274802
 2016-07-07 22:50:23 +00:00
Michael Kuperstein edb38a94f8 Revert r274692 to check whether this is what breaks windows selfhost. 
llvm-svn: 274771
 2016-07-07 16:55:35 +00:00
Michael Kuperstein 1ef6c59b1d [X86] Transform setcc + movzbl into xorl + setcc 
xorl + setcc is generally the preferred sequence due to the partial register
stall setcc + movzbl suffers from. As a bonus, it also encodes one byte smaller.

This fixes PR28146.

Differential Revision: http://reviews.llvm.org/D21774

llvm-svn: 274692
 2016-07-06 21:56:18 +00:00
Elena Demikhovsky ad0a56f3da Re-commit of 274613. 
The prev commit failed on compilation.
A minor change in one pattern in lib/Target/X86/X86InstrAVX512.td fixes the failure.

llvm-svn: 274626
 2016-07-06 14:15:43 +00:00
Elena Demikhovsky 02ced295aa Reverted 274613 due to compilation failue. 
llvm-svn: 274615
 2016-07-06 09:11:49 +00:00
Elena Demikhovsky 5a4f2476fd AVX-512: Optimization for patterns with i1 scalar type 
The patch removes redundant kmov instructions (not all, we still have a lot of work here) and redundant "and" instructions after "setcc".
I use "AssertZero" marker between X86ISD::SETCC node and "truncate" to eliminate extra "and $1" instruction.
I also changed zext, aext and trunc patterns in the .td file. It allows to remove extra "kmov" instruictions.

This patch fixes https://llvm.org/bugs/show_bug.cgi?id=28173.

Fast ISEL mode is not supported correctly for AVX-512. ICMP/FCMP scalar instruction should return result in k-reg. It will be fixed in one of the next patches. I redirected handling of "cmp" to the DAG builder mode. (The code looks worse in one specific test case, but without this fix the new patch fails).

Differential revision: http://reviews.llvm.org/D21956

llvm-svn: 274613
 2016-07-06 09:01:20 +00:00
Simon Pilgrim 4e96fbf3c1 [X86][AVX512] Autoupgrade the BROADCAST intrinsics 
llvm-svn: 274550
 2016-07-05 13:58:47 +00:00
Simon Pilgrim 02d435d2f4 [X86][AVX512] Autoupgrade the VPERMPD/VPERMQ intrinsics 
llvm-svn: 274506
 2016-07-04 14:19:05 +00:00
Simon Pilgrim 9fca300cbe [X86][AVX512] Autoupgrade the VPERMILPD/VPERMILPS intrinsics 
llvm-svn: 274498
 2016-07-04 12:40:54 +00:00
Simon Pilgrim 68ea80649b [X86][AVX512] Add support for VPERMPD/VPERMQ masked shuffle comments 
llvm-svn: 274469
 2016-07-03 18:40:24 +00:00
Simon Pilgrim a0d73835b2 [X86][AVX512] Add support for 512-bit shuffle decoding of VPERMPD/VPERMQ 
llvm-svn: 274468
 2016-07-03 18:27:37 +00:00
Simon Pilgrim 1f59076196 [X86][AVX512] Add support for VPERM/VSHUF masked shuffle comments 
llvm-svn: 274462
 2016-07-03 13:55:41 +00:00
Simon Pilgrim 68f438a036 [X86][AVX512] Add support for PMOVZX masked shuffle comments 
llvm-svn: 274461
 2016-07-03 13:33:28 +00:00
Simon Pilgrim 19adee9d84 [X86][AVX512] Autoupgrade the MOVDDUP/MOVSLDUP/MOVSHDUP intrinsics 
llvm-svn: 274439
 2016-07-02 14:42:35 +00:00
Craig Topper 597aa42fec [AVX512] Remove masked unpack intrinsics and autoupgrade to vectorshuffle and selects. 
llvm-svn: 273543
 2016-06-23 07:37:33 +00:00
Craig Topper 283418fbb6 [AVX512] Add patterns for any-extending a mask that use the def of KMOVW/KMOVB without going through an EXTRACT_SUBREG and a MOVZX. 
llvm-svn: 273253
 2016-06-21 07:37:32 +00:00
Craig Topper 0a0fb0fda1 [AVX512] Remove the masked vpcmpeq/vcmpgt intrinsics and autoupgrade them to native icmps. 
llvm-svn: 273240
 2016-06-21 03:53:24 +00:00
Craig Topper 13cf7cac07 [AVX512] Remove maksed pshufd, pshuflw, and phufhw intrinsics and autoupgrade them to selects and shufflevector. 
llvm-svn: 272527
 2016-06-13 02:36:48 +00:00
Craig Topper 89c1761474 [AVX512] Fix shuffle comment printing to handle the masked versions of some shuffles. Previously we were printing the mask operands as the register names. 
llvm-svn: 272367
 2016-06-10 04:48:05 +00:00
Igor Breger f635367e2b [AVX512] Remove masked_move/blendm intrinsic from back-end. 
This is complement patch to D21060.

Differential Revision: http://reviews.llvm.org/D21174

llvm-svn: 272257
 2016-06-09 11:46:55 +00:00
Craig Topper 6f7288dc44 [AVX512] Fix shuffle decode printing for several instructions with write masks. There are still more bugs here with UNPCK and PALIGN for sure. But these were the easiest ones to fix. 
llvm-svn: 272252
 2016-06-09 07:49:08 +00:00
Craig Topper 01f53b1773 [AVX512] Fix shuffle comment printing for EVEX encoded PSHUFD, PSHUFHW, and PSHUFLW. 
llvm-svn: 271628
 2016-06-03 05:31:00 +00:00
Craig Topper f10fbfa738 [AVX512] Remove masked load intrinsics. Clang now emits generic masked load intrinsics instead. 
The intrinsics will be autoupgraded to the same generic masked loads.

llvm-svn: 271478
 2016-06-02 04:19:36 +00:00
Igor Breger 73ee8ba9b0 [AVX512] Fix intrinsic vcvtps2ph lowering. 
Differential Revision: http://reviews.llvm.org/D20788

llvm-svn: 271255
 2016-05-31 08:04:21 +00:00
Craig Topper 50f85c22c5 [AVX512] Remove masked store intrinsics. Clang now emits generic masked store intrinsics instead. 
The intrinsics will be autoupgraded to the same generic masked stores.

llvm-svn: 271245
 2016-05-31 01:50:02 +00:00
Igor Breger 8437bb70fd [AVX512] Fix intrinsic cmp{sd|ss} lowering. 
Differential Revision: http://reviews.llvm.org/D20615

llvm-svn: 270843
 2016-05-26 12:42:25 +00:00
Igor Breger 23c2090606 [llvm][AVX512][intrinsics] Fix vperm{b|w|d|q|ps|pd} intrinsics. Index is second argument to buildin function but it is first instruction operand. 
Differential Revision: http://reviews.llvm.org/D20515

llvm-svn: 270548
 2016-05-24 11:06:22 +00:00
Michael Zuckerman a63a129749 [Clang][AVX512][intrinsics] Fix rcp and sqrt intrinsics. 
Differential Revision: http://reviews.llvm.org/D20438

llvm-svn: 270322
 2016-05-21 14:44:18 +00:00
Michael Zuckerman 11b55b29d1 [Clang][AVX512][intrinsics] Fix vscalef intrinsics. 
Differential Revision: http://reviews.llvm.org/D20324

llvm-svn: 270321
 2016-05-21 11:09:53 +00:00
Craig Topper 726cb506ff [AVX512] Fix mask argument type for insertf32x4/inserti32x4. 
llvm-svn: 269616
 2016-05-15 21:24:45 +00:00
Craig Topper 258f874bb9 [AVX512] Make the permd intrinsics take a 32-bit immediate to match the software spec. 
llvm-svn: 269579
 2016-05-14 21:13:20 +00:00
Elena Demikhovsky e79b716daf Fixed lowering of _comi_ intrinsics from all sets - SSE/SSE2/AVX/AVX-512 
Differential revision http://reviews.llvm.org/D19261

llvm-svn: 269569
 2016-05-14 15:06:09 +00:00
Craig Topper d8a9c0d120 [AVX512] Fix types for pshufd intrinsics. The immediate is the second argument and the mask is the 4th argument. Also move the 128/256 tests to the right test file. 
Prior to this the immediate was a strange 16-bits and the 512-bit intrinsic couldn't receive the full 16 mask bits it needs.

llvm-svn: 269526
 2016-05-14 00:47:18 +00:00
Simon Pilgrim 6ce35dd9ea [X86][AVX512] Fixed VPERMILPD/VPERMILPS shuffle comments. 
Fixed incorrect operands indices used to access src registers

llvm-svn: 269221
 2016-05-11 18:53:44 +00:00
Simon Pilgrim 87d05b9852 [X86][AVX512] Regenerate intrinsics test 
llvm-svn: 269193
 2016-05-11 15:13:29 +00:00
Craig Topper a58abd1cc6 [AVX512] Fix up types for arguments of int_x86_avx512_mask_cvtsd2ss_round and int_x86_avx512_mask_cvtss2sd_round. Only the argument being converted should be a different type. The other 2 argument should have the same type as the result. 
llvm-svn: 268891
 2016-05-09 05:34:12 +00:00
Michael Zuckerman 1bd66dd1c2 Fixing wrong mask size error. From __mmask8 to __mmask16. 
Was reviewed over the shoulder by AsafBadouh.
Connected to review http://reviews.llvm.org/D19195.

llvm-svn: 267379
 2016-04-25 05:27:51 +00:00
Simon Pilgrim 7ec092d0f8 [X86][AVX512] Regenerated intrinsics tests 
llvm-svn: 265135
 2016-04-01 11:57:51 +00:00
Michael Zuckerman 927fdaee88 [LLVM][AVX512]PSRAWI Change imm8 to int. 
Differential Revision: http://reviews.llvm.org/D17705

llvm-svn: 262480
 2016-03-02 12:05:07 +00:00
Michael Zuckerman 433b241570 [LLVM][AVX512] PSRL{DI|QI} Change imm8 to int 
Differential Revision: http://reviews.llvm.org/D17713

llvm-svn: 262353
 2016-03-01 17:46:32 +00:00
Michael Zuckerman 7878888690 [AVX512][PSRAQ][PSRAD] Change imm8 to int. 
Differential Revision: http://reviews.llvm.org/D17692

llvm-svn: 262320
 2016-03-01 11:36:23 +00:00
Michael Zuckerman 529c27f408 [AVX512][PROLQ][PROLD] Change imm8 to int 
Differential Revision: http://reviews.llvm.org/D16983

llvm-svn: 260101
 2016-02-08 15:13:32 +00:00
Asaf Badouh ad5c3fc47d [X86][AVX512] add intrinsics of Scalar FP to integer conversion with rounding mode 
Differential Revision: http://reviews.llvm.org/D16629

llvm-svn: 260033
 2016-02-07 14:59:13 +00:00
Igor Breger 0aeda37464 AVX512: VPBROADCASTB/W/D/Q from GPR intrinsics implementation. 
Differential Revision: http://reviews.llvm.org/D16813

llvm-svn: 260024
 2016-02-07 08:30:50 +00:00