Commit Graph

1317 Commits

Author SHA1 Message Date
Chris Lattner d7fec20cba convert to filecheck style, simplify RUN line, and add comment.
llvm-svn: 75667
2009-07-14 19:49:11 +00:00
Chris Lattner 8c9a96b966 Reapply my previous asmprinter changes now with more testing and two
additional bug fixes:

1. The bug that everyone hit was a problem in the asmprinter where it
   would remove $stub but keep the L prefix on a name when emitting the
   indirect symbol.  This is easy to fix by keeping the name of the stub
   and the name of the symbol in a StringMap instead of just keeping a
   StringSet and trying to reconstruct it late.

2. There was a problem printing the personality function.  The current
   logic to print out the personality function from the DWARF information
   is a bit of a cesspool right now that duplicates a bunch of other 
   logic in the asm printer.  The short version of it is that it depends
   on emitting both the L and _ prefix for symbols (at least on darwin)
   and until I can untangle it, it is best to switch the mangler back to
   emitting both prefixes.

llvm-svn: 75646
2009-07-14 18:17:16 +00:00
Daniel Dunbar 966932ccb7 Revert r75610 (and r75620, which was blocking the revert), in the hopes of
unbreaking llvm-gcc (on Darwin).

--- Reverse-merging r75620 into '.':
U    include/llvm/Support/Mangler.h
--- Reverse-merging r75610 into '.':
U    test/CodeGen/X86/loop-hoist.ll
G    include/llvm/Support/Mangler.h
U    lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
U    lib/VMCore/Mangler.cpp

llvm-svn: 75636
2009-07-14 15:57:55 +00:00
Chris Lattner 774f2a2d51 Change the X86 asmprinter to use the mangler to apply suffixes like "$non_lazy_ptr"
to symbols instead of doing it with "printSuffixedName".  This gets us to the point
where there is a real separation between computing a symbol name and printing it,
something I need for MC printer stuff.

This patch also fixes a corner case bug where unnamed private globals wouldn't get
the private label prefix.

Next up, rename all uses of getValueName -> getMangledName for better greppability,
and then tackle the ppc/arm backends to eliminate "printSuffixedName".

llvm-svn: 75610
2009-07-14 06:04:35 +00:00
Chris Lattner f34815b32f Change the internal interface to makeNameProper to take a bool that
indicates whether the label is private or not, instead of taking
prefix stuff.  One effect of this is that symbols will be generated
with *just* the private prefix, instead of both the private prefix
*and* the user-label-prefix, but this doesn't matter as long as it
is consistent.  For example we'll now get "Lfoo" instead of "L_foo".
These are just assembler temporary labels anyway, so they never even
make it into the .o file.

llvm-svn: 75607
2009-07-14 04:50:12 +00:00
Bill Wendling e604b776a7 Check for the correct unnamed name.
llvm-svn: 75573
2009-07-14 00:53:58 +00:00
Chris Lattner ec8efcb44e Two changes:
1) unique globals with the existing "Count" local in Mangler, not with
atomic nonsense.  Using atomics will give us nondeterminstic output
from the compiler when using multiple threads, which is bad.

2) Do not mangle an unknown global name with a type suffix.  We don't
   need this anymore now that llvm ir doesn't have type planes.

llvm-svn: 75541
2009-07-13 22:48:46 +00:00
Chris Lattner f39f55d46c add nounwind
llvm-svn: 75407
2009-07-12 00:46:16 +00:00
Nick Lewycky d57fb023e0 Darwin prepends an _ to internal globals, Linux doesn't.
llvm-svn: 75405
2009-07-11 23:48:59 +00:00
Chris Lattner 38df005e12 fix x86-64 static codegen to materialize the address of a global with movl instead
of lea.  It is better for code size (and presumably efficiency) to use:

  movl $foo, %eax

rather than:

  leal foo, eax

Both give a nice zero extending "move immediate" instruction, the former is just
smaller.  Note that global addresses should be handled different by the x86
backend, but I chose to follow the style already in place and add more fixme's.

llvm-svn: 75403
2009-07-11 23:17:29 +00:00
Chris Lattner 056dfc6f90 this test was incorrect for x86-64 static. It passed on darwin, because darwin
doesn't have static x86-64 mode.

llvm-svn: 75392
2009-07-11 22:30:05 +00:00
Chris Lattner e91900097e Fix PR4533, which is about buggy codegen in x86-64 -static mode.
Basically, using:
  lea symbol(%rip), %rax

is not valid in -static mode, because the current RIP may not be
within 32-bits of "symbol" when an app is built partially pic and
partially static.  The fix for this is to compile it to:

  lea symbol, %rax

It would be better to codegen this as:

  movq $symbol, %rax

but that will come next.


The hard part of fixing this bug was fixing abi-isel, which was actively
testing for the wrong behavior.  Also, the RUN lines are completely impossible
to understand what they are testing.  To help with this, convert the -static 
x86-64 codegen tests to use filecheck.  This is much more stable and makes it
more clear what the codegen is expected to be.

llvm-svn: 75382
2009-07-11 20:29:19 +00:00
Chris Lattner 20adc670b2 We get the P modifier wrong in a lot of cases, just add some more rigorous testing.
In addition to fixing this, I still need to do some more testing on darwin.

llvm-svn: 75362
2009-07-11 08:30:22 +00:00
Eli Friedman 2b77eef160 Make EXTRACT_VECTOR_ELT a bit more flexible in terms of the returned
value.  Adjust other code to deal with that correctly.  Make 
DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT take advantage of 
this new flexibility to simplify the code and make it deal with unusual 
vectors (like <4 x i1>) correctly.  Fixes PR3037.

llvm-svn: 75176
2009-07-09 22:01:03 +00:00
Evan Cheng 7452c968e4 Targets sometimes assign fixed stack object to spill certain callee-saved
registers based on dynamic conditions. For example, X86 EBP/RBP, when used as
frame register has to be spilled in the first fixed object. It should inform
PEI this so it doesn't get allocated another stack object. Also, it should not
be spilled as other callee-saved registers but rather its spilling and restoring
are being handled by emitPrologue and emitEpilogue. Avoid spilling it twice.

llvm-svn: 75116
2009-07-09 06:53:48 +00:00
Chris Lattner 44f6bcfa0b remove eh, convert to FileCheck style
llvm-svn: 75087
2009-07-09 01:07:22 +00:00
Chris Lattner 212f44d180 we have no tests for dllimport/export. Add one.
llvm-svn: 75085
2009-07-09 00:53:44 +00:00
Chris Lattner ade55bc8dd * add some assertions for sanity checking.
* remove some old code that was needed when we'd put ESP in the scale instead of 
  the base of some instructions.
* Fix a bug with the P modifier in inline asm that caused us to drop it.

llvm-svn: 75077
2009-07-09 00:27:29 +00:00
Chris Lattner da0cf0b134 add a test for dale's recent change.
llvm-svn: 75074
2009-07-09 00:00:16 +00:00
Chris Lattner f65129cb6a switch test to FileCheck-style and test the P and non-P cases.
llvm-svn: 75071
2009-07-08 23:44:06 +00:00
Chris Lattner 334e561e35 rename a test to make it a feature test.
llvm-svn: 75070
2009-07-08 23:40:57 +00:00
Chris Lattner d5ffa8ffb6 add some more check for vector compares.
llvm-svn: 75024
2009-07-08 18:51:25 +00:00
Chris Lattner 072198a2a1 convert a test to "FileCheck" style.
llvm-svn: 75023
2009-07-08 18:48:24 +00:00
Chris Lattner 04bf64d43c eliminate the v[if]cmp versions of these tests, now that [if]cmp+sext works.
llvm-svn: 74980
2009-07-08 00:49:35 +00:00
Chris Lattner 4ac607332d dag combine sext(setcc) -> vsetcc before legalize. To make this safe,
VSETCC must define all bits, which is different than it was documented
to before.  Since all targets that implement VSETCC already have this
behavior, and we don't optimize based on this, just change the 
documentation.  We now get nice code for vec_compare.ll

llvm-svn: 74978
2009-07-08 00:31:33 +00:00
Chris Lattner fc74e8241a add support for legalizing an icmp where the result is illegal (4xi1) but
the input is legal (4 x i32)

llvm-svn: 74964
2009-07-07 23:03:54 +00:00
Chris Lattner cbbf747b7b add a trivial test that vector compares work.
llvm-svn: 74963
2009-07-07 22:51:09 +00:00
Chris Lattner 30220d8f98 implement support for spliting and scalarizing vector setcc's. This
finishes off enough support for vector compares to get the icmp/fcmp
version of 2008-07-23-VSetCC.ll passing.

llvm-svn: 74961
2009-07-07 22:47:46 +00:00
Chris Lattner 87d4f309f5 verify that the fcmp version of this works just as well as the
vfcmp version.  We actually get better code for this silly testcase.

llvm-svn: 74954
2009-07-07 22:07:47 +00:00
Evan Cheng ba2410b7ca Avoid adding a duplicate def. This fixes PR4478.
llvm-svn: 74857
2009-07-06 21:34:05 +00:00
Chris Lattner 87bb642676 @GOTPCREL is also rip-relative. Fix fast-isel to do the right thing.
This fixes an llvm-gcc bootstrap problem I introduced.

llvm-svn: 74691
2009-07-02 04:22:01 +00:00
Chris Lattner d1c5951615 Fix yet-another bug I introduced into fastisel, this time handling
constant pool references that weren't getting properly rip-relative.

llvm-svn: 74689
2009-07-02 03:14:25 +00:00
Chris Lattner f95fa1b721 Fix some fast-isel problems selecting global variable addressing in
pic mode.

llvm-svn: 74582
2009-07-01 03:27:19 +00:00
Rafael Espindola 317fd045e2 Fix PR4485.
Avoid unnecessary duplication of operand 0 of X86::FpSET_ST0_80. This duplication would
cause one register to remain on the stack at the function return.

llvm-svn: 74534
2009-06-30 16:40:03 +00:00
Rafael Espindola bd971ffcc6 Fix PR4484.
This was caused by me confounding FP0 and ST(0).

llvm-svn: 74523
2009-06-30 12:18:16 +00:00
Rafael Espindola 538064d6b1 FIX PR 4459.
Not sure I understand how the temp register gets used,
but this fixes a bug and introduces no regressions.

llvm-svn: 74446
2009-06-29 20:29:59 +00:00
Chris Lattner 9876bd8257 factor some logic out into a helper function, allow remat of loads from constant
globals.  This implements remat-constant.ll even without aggressive-remat.

llvm-svn: 74373
2009-06-27 04:38:55 +00:00
Chris Lattner fea81da433 Reimplement rip-relative addressing in the X86-64 backend. The new
implementation primarily differs from the former in that the asmprinter
doesn't make a zillion decisions about whether or not something will be
RIP relative or not.  Instead, those decisions are made by isel lowering
and propagated through to the asm printer.  To achieve this, we:

1. Represent RIP relative addresses by setting the base of the X86 addr
   mode to X86::RIP.
2. When ISel Lowering decides that it is safe to use RIP, it lowers to
   X86ISD::WrapperRIP.  When it is unsafe to use RIP, it lowers to
   X86ISD::Wrapper as before.
3. This removes isRIPRel from X86ISelAddressMode, representing it with
   a basereg of RIP instead.
4. The addressing mode matching logic in isel is greatly simplified.
5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate
   passed through various printoperand routines is gone now.
6. The various symbol printing routines in asmprinter now no longer infer
   when to emit (%rip), they just print the symbol.

I think this is a big improvement over the previous situation.  It does have
two small caveats though: 1. I implemented a horrible "no-rip" modifier for
the inline asm "P" constraint modifier.  This is a short term hack, there is
a much better, but more involved, solution.  2. I had to xfail an 
-aggressive-remat testcase because it isn't handling the use of RIP in the
constant-pool reading instruction.  This specific test is easy to fix without
-aggressive-remat, which I intend to do next.

llvm-svn: 74372
2009-06-27 04:16:01 +00:00
Chris Lattner df92e147c9 remove some unneeded eh info.
llvm-svn: 74371
2009-06-27 04:07:31 +00:00
Chris Lattner de36afc1fe testcase for PR4466
llvm-svn: 74367
2009-06-27 01:33:35 +00:00
Dan Gohman d3b930d426 Add some testcases for some of the recent ScalarEvolution bug fixes.
llvm-svn: 74353
2009-06-26 22:54:11 +00:00
Chris Lattner b5c2639f83 remove unwind info, add test for asmprinting of jump table labels with (%rip)
llvm-svn: 74337
2009-06-26 22:16:49 +00:00
Evan Cheng 07b016856d Add x86 support for 'n' inline asm modifier. This will be handled target independently as part of MC work.
llvm-svn: 74336
2009-06-26 22:00:19 +00:00
Chris Lattner a4194b1082 down with unwind info :)
llvm-svn: 74206
2009-06-25 21:48:17 +00:00
Chris Lattner 01d5049dc2 unwind info not needed.
llvm-svn: 74112
2009-06-24 19:48:04 +00:00
Evan Cheng 38f2453817 Fix support for inline asm input / output operand tying when operand spans across multiple registers (e.g. two i64 operands in 32-bit mode).
llvm-svn: 74053
2009-06-24 02:05:51 +00:00
Dan Gohman f19aeec3f5 Extend ScalarEvolution's multiple-exit support to compute exact
trip counts in more cases.

Generalize ScalarEvolution's isLoopGuardedByCond code to recognize
And and Or conditions, splitting the code out into an
isNecessaryCond helper function so that it can evaluate Ands and Ors
recursively, and make SCEVExpander be much more aggressive about
hoisting instructions out of loops.

test/CodeGen/X86/pr3495.ll has an additional instruction now, but
it appears to be due to an arbitrary register allocation difference.

llvm-svn: 74048
2009-06-24 01:18:18 +00:00
Rafael Espindola 6ead59f8ed Fix PR4185.
Handle FpSET_ST0_80 being used when ST0 is still alive.

llvm-svn: 73850
2009-06-21 12:02:51 +00:00
Chris Lattner 7d2b049404 change TLS_ADDR lowering to lower to a real mem operand, instead of matching as
a global with that gets printed with the :mem modifier.  All operands to lea's 
should be handled with the lea32mem operand kind, and this allows the TLS stuff
to do this.  There are several better ways to do this, but I went for the minimal
change since I can't really test this (beyond make check).

This also makes the use of EBX explicit in the operand list in the 32-bit, 
instead of implicit in the instruction.

llvm-svn: 73834
2009-06-20 20:38:48 +00:00
Chris Lattner 1771a852f0 no need for unwind info
llvm-svn: 73832
2009-06-20 19:48:26 +00:00
Chris Lattner fbc9778a1b no need for unwind info here.
llvm-svn: 73831
2009-06-20 19:43:09 +00:00
Dan Gohman cc31110b95 Re-apply r73718, now that the fix in r73787 is in, and add a
hand-crafted testcase which demonstrates the bug that was exposed
in 254.gap.

llvm-svn: 73793
2009-06-19 23:23:27 +00:00
Evan Cheng 86076c9e30 Revert 73718. It's breaking 254.gap.
llvm-svn: 73783
2009-06-19 21:15:06 +00:00
Eli Friedman 2fc939c809 Fix for PR2484: add an SSE1 pattern for a shuffle we normally prefer to
handle with an SSE2 instruction.

llvm-svn: 73760
2009-06-19 07:00:55 +00:00
Evan Cheng de9e36a74e On Darwin, ams printer should output a second label before a jump table so the linker knows it's a new atom. But this is only needed if the jump table is put in a separate section from the function body.
llvm-svn: 73720
2009-06-18 20:37:15 +00:00
Dan Gohman 8c9ac59455 Generalize LSR's OptimizeSMax to handle unsigned max tests as well
as signed max tests. Along with r73717, this helps CodeGen avoid
emitting code for a maximum operation for this class of loop.

llvm-svn: 73718
2009-06-18 20:23:18 +00:00
Dan Gohman a0348809b6 Remove the code from IVUsers that attempted to handle
casted induction variables in cases where the cast
isn't foldable. It ended up being a pessimization in
many cases. This could be fixed, but it would require
a bunch of complicated code in IVUsers' clients. The
advantages of this approach aren't visible enough to
justify it at this time.

llvm-svn: 73706
2009-06-18 16:54:06 +00:00
Eli Friedman abfad5d61e Add some generic expansion logic for SMULO and UMULO. Fixes UMULO
support for x86, and UMULO/SMULO for many architectures, including PPC 
(PR4201), ARM, and Cell. The resulting expansion isn't perfect, but it's
not bad.

llvm-svn: 73477
2009-06-16 06:58:29 +00:00
Dan Gohman 8e85118943 Update this test to use fmul instead of mul.
llvm-svn: 73436
2009-06-15 22:49:34 +00:00
Bill Wendling 20f0adfc0e This test is failing. Revert for now.
llvm-svn: 73404
2009-06-15 19:10:56 +00:00
Bill Wendling 66e104cd11 Add another testcase for r71478.
llvm-svn: 73399
2009-06-15 18:36:34 +00:00
Arnold Schwaighofer cb9046cfc8 CheckTailCallReturnConstraints is missing a check on the
incomming chain of the RETURN node. The incomming chain must
be the outgoing chain of the CALL node. This causes the
backend to identify tail calls that are not tail calls. This
patch fixes this.

llvm-svn: 73387
2009-06-15 14:43:36 +00:00
Arnold Schwaighofer e3a018d707 Fix Bug 4278: X86-64 with -tailcallopt calling convention
out of sync with regular cc.

The only difference between the tail call cc and the normal
cc was that one parameter register - R9 - was reserved for
calling functions through a function pointer. After time the
tail call cc has gotten out of sync with the regular cc. 

We can use R11 which is also caller saved but not used as
parameter register for potential function pointers and
remove the special tail call cc on x86-64.

llvm-svn: 73233
2009-06-12 16:26:57 +00:00
Eli Friedman 0b387fbd1b Fix the run-line for this test to work correctly outside of x86.
llvm-svn: 73025
2009-06-07 09:44:19 +00:00
Eli Friedman 516479d6e7 Tweak the expansion code for BIT_CONVERT to generate better code
converting from an MMX vector to an i64.

llvm-svn: 73024
2009-06-07 09:41:57 +00:00
Eli Friedman 3234587213 Slightly generalize the code that handles shuffles of consecutive loads
on x86 to handle more cases.  Fix a bug in said code that would cause it 
to read past the end of an object.  Rewrite the code in 
SelectionDAGLegalize::ExpandBUILD_VECTOR to be a bit more general. 
Remove PerformBuildVectorCombine, which is no longer necessary with 
these changes.  In addition to simplifying the code, with this change, 
we can now catch a few more cases of consecutive loads.

llvm-svn: 73012
2009-06-07 06:52:44 +00:00
Eli Friedman c61e357aa6 Fix the expansion for CONCAT_VECTORS so that it doesn't create illegal
types.

llvm-svn: 72993
2009-06-06 07:08:26 +00:00
Eli Friedman 75c496f920 Avoid crashing on a variable-index insertelement with element type i16.
llvm-svn: 72991
2009-06-06 06:32:50 +00:00
Eli Friedman 1b1844ad1f Get rid of some bogus patterns for X86vzmovl. Don't create VZEXT_MOVL
nodes for vectors with an i16 element type.  Add an optimization for 
building a vector which is all zeros/undef except for the bottom 
element, where the bottom element is an i8 or i16.

llvm-svn: 72988
2009-06-06 06:05:10 +00:00
Eli Friedman 868bd6ab52 Fix an obvious typo.
llvm-svn: 72987
2009-06-06 05:55:37 +00:00
Eli Friedman 6c101ebfa8 Get rid of a bogus pattern that interferes with optimization.
llvm-svn: 72985
2009-06-06 04:17:04 +00:00
Eli Friedman b45e8ce69a PR2598: make sure to expand illegal forms of integer/floating-point
conversions for x86, like <2 x i32> -> <2 x float> and <4 x i16> -> 
<4 x float>.

llvm-svn: 72983
2009-06-06 03:57:58 +00:00
Nate Begeman 624690c6b2 Adapt the x86 build_vector dagcombine to the current state of the legalizer.
build vectors with i64 elements will only appear on 32b x86 before legalize.
Since vector widening occurs during legalize, and produces i64 build_vector 
elements, the dag combiner is never run on these before legalize splits them
into 32b elements.

Teach the build_vector dag combine in x86 back end to recognize consecutive 
loads producing the low part of the vector.

Convert the two uses of TLI's consecutive load recognizer to pass LoadSDNodes
since that was required implicitly.

Add a testcase for the transform.

Old:
	subl	$28, %esp
	movl	32(%esp), %eax
	movl	4(%eax), %ecx
	movl	%ecx, 4(%esp)
	movl	(%eax), %eax
	movl	%eax, (%esp)
	movaps	(%esp), %xmm0
	pmovzxwd	%xmm0, %xmm0
	movl	36(%esp), %eax
	movaps	%xmm0, (%eax)
	addl	$28, %esp
	ret

New:
	movl	4(%esp), %eax
	pmovzxwd	(%eax), %xmm0
	movl	8(%esp), %eax
	movaps	%xmm0, (%eax)
	ret

llvm-svn: 72957
2009-06-05 21:37:30 +00:00
Dan Gohman a5b9645c4b Split the Add, Sub, and Mul instruction opcodes into separate
integer and floating-point opcodes, introducing
FAdd, FSub, and FMul.

For now, the AsmParser, BitcodeReader, and IRBuilder all preserve
backwards compatability, and the Core LLVM APIs preserve backwards
compatibility for IR producers. Most front-ends won't need to change
immediately.

This implements the first step of the plan outlined here:
http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt

llvm-svn: 72897
2009-06-04 22:49:04 +00:00
Devang Patel 72a4d2fec1 Add new function attribute - noredzone.
Update code generator to use this attribute and remove DisableRedZone target option.
Update llc to set this attribute when -disable-red-zone command line option is used.

llvm-svn: 72894
2009-06-04 22:05:33 +00:00
Evan Cheng fa0ac19b82 RALinScan::attemptTrivialCoalescing() was returning a virtual register instead of the physical register it is allocated to. This resulted in virtual register(s) being added the live-in sets.
llvm-svn: 72890
2009-06-04 20:53:36 +00:00
Dan Gohman 1aa86203f6 Check in test changes that I accidentally left out of r72872.
llvm-svn: 72875
2009-06-04 18:22:31 +00:00
Eli Friedman 63488f1fbf PR3739, part 2: Use an explicit store to spill XMM registers. (Previously,
the code tried to use "push", which doesn't exist for XMM registers.)

llvm-svn: 72836
2009-06-04 02:32:04 +00:00
Eli Friedman 0cb0c78a26 PR3739, part 1: Disable the red zone on Win64.
llvm-svn: 72830
2009-06-04 02:02:01 +00:00
Evan Cheng ad6f3ff2c0 For Darwin / x86_64, override -relocation-model=static to pic if the output is assembly since Darwin assembler does not really support -static codeine.
I view this as a temporary workaround until the assembler / linker changes.

llvm-svn: 72806
2009-06-03 21:13:54 +00:00
Evan Cheng b39a6be77a Fix for PR4225: When rewriter reuse a value in a physical register , it clear the register kill operand marker and its kill ops information. However, the cleared operand may be a def of a super-register. Clear the kill ops info for the super-register's sub-registers as well.
llvm-svn: 72758
2009-06-03 09:00:27 +00:00
Dan Gohman fc262babc3 Revert r72734. The Darwin assembler doesn't support the static
relocation model on x86-64. Higher level logic should override
the relocation model to PIC on x86_64-apple-darwin.

llvm-svn: 72746
2009-06-03 00:37:20 +00:00
Dan Gohman 760377effc Fix CodeGenPrepare's address-mode sinking to handle unusual
addresses, involving Base values which do not have Pointer type.
This fixes PR4297.

llvm-svn: 72739
2009-06-02 21:29:13 +00:00
Evan Cheng 448641d87c On Darwin x86_64 small code model doesn't guarantee code address fits in 32-bit.
llvm-svn: 72734
2009-06-02 20:09:31 +00:00
Evan Cheng 7142ad75a1 (i64 (zext (srl GR32 8))) -> movzbl AH is not safe since srl 8 only clear the top 8 bits.
llvm-svn: 72618
2009-05-30 08:43:27 +00:00
Evan Cheng 8e97b85cde Remove an accidental commit.
llvm-svn: 72560
2009-05-29 05:28:52 +00:00
Evan Cheng 716e688fca More h-registers tricks: folding zext nodes.
llvm-svn: 72558
2009-05-29 01:44:43 +00:00
Evan Cheng 86cdb4b345 Do not try to create a MVT type of width 0.
llvm-svn: 72557
2009-05-28 23:52:18 +00:00
Eli Friedman 1f906448bc Add a testcase which got fixed by recent legalization work.
llvm-svn: 72517
2009-05-28 05:10:20 +00:00
Evan Cheng a9cda8abf2 Added optimization that narrow load / op / store and the 'op' is a bit twiddling instruction and its second operand is an immediate. If bits that are touched by 'op' can be done with a narrower instruction, reduce the width of the load and store as well. This happens a lot with bitfield manipulation code.
e.g.
orl     $65536, 8(%rax)
=>
orb     $1, 10(%rax)

Since narrowing is not always a win, e.g. i32 -> i16 is a loss on x86, dag combiner consults with the target before performing the optimization.

llvm-svn: 72507
2009-05-28 00:35:15 +00:00
Torok Edwin be6a9a151a Fix PR4254.
The DAGCombiner created a negative shiftamount, stored in an
unsigned variable. Later the optimizer eliminated the shift entirely as being
undefined.
Example: (srl (shl X, 56) 48). ShiftAmt is 4294967288.
Fix it by checking that the shiftamount is positive, and storing in a signed
variable.

llvm-svn: 72331
2009-05-23 17:29:48 +00:00
Torok Edwin 7996339dd8 available_externall linkage is not local, this was confusing the codegenerator,
and it wasn't generating calls through @PLT for these functions.
hasLocalLinkage() is now false for available_externally,
I attempted to fix the inliner and dce to handle available_externally properly.
It passed make check.

llvm-svn: 72328
2009-05-23 14:06:57 +00:00
Eli Friedman 53a71147ba Fix test to account for legalization changes; I think this ends up
running an extra DAGCombine pass which improves the code a bit.

llvm-svn: 72326
2009-05-23 13:15:11 +00:00
Evan Cheng 1fbc2a4754 Fix test on non-darwin hosts.
llvm-svn: 72161
2009-05-20 05:45:36 +00:00
Evan Cheng 960983371c Try again. Allow call to immediate address for ELF or when in static relocation mode.
llvm-svn: 72160
2009-05-20 04:53:57 +00:00
Evan Cheng 61da18645b Cannot use immediate as call absolute target in PIC mode.
llvm-svn: 72154
2009-05-20 01:11:00 +00:00
Dan Gohman b81dd48fd2 Add nounwind to a few tests.
llvm-svn: 72002
2009-05-18 15:16:49 +00:00
Jakob Stoklund Olesen 9d7fb58581 Help DejaGnu avoid pipe-jam by producing less output from certain test cases.
When a test fails with more than a pipeful of output on stdout AND stderr, one
of the DejaGnu programs blocks. The problem can be avoided by redirecting
stdout to a file.

llvm-svn: 71919
2009-05-16 00:34:42 +00:00
Dan Gohman 6b43dd7664 Add nounwind to this test.
llvm-svn: 71734
2009-05-13 22:29:12 +00:00
Evan Cheng 85cca64dd7 If header of inner loop is aligned, do not align the outer loop header. We don't want to add nops in the outer loop for the sake of aligning the inner loop.
llvm-svn: 71609
2009-05-12 23:58:14 +00:00
Evan Cheng df1aeeeb90 Teach TransferDeadness to delete truly dead instructions if they do not produce side effects.
llvm-svn: 71606
2009-05-12 23:07:00 +00:00
Evan Cheng 79afe74195 Add nounwind.
llvm-svn: 71575
2009-05-12 18:35:43 +00:00
Evan Cheng c94de92c54 Fixed a stack slot coloring with reg bug: do not update implicit use / def when doing forward / backward propagation.
llvm-svn: 71574
2009-05-12 18:31:57 +00:00
Dan Gohman d76d71a291 Factor the code for collecting IV users out of LSR into an IVUsers class,
and generalize it so that it can be used by IndVarSimplify. Implement the
base IndVarSimplify transformation code using IVUsers. This removes
TestOrigIVForWrap and associated code, as ScalarEvolution now has enough
builtin overflow detection and folding logic to handle all the same cases,
and more. Run "opt -iv-users -analyze -disable-output" on your favorite
loop for an example of what IVUsers does.

This lets IndVarSimplify eliminate IV casts and compute trip counts in
more cases. Also, this happens to finally fix the remaining testcases
in PR1301.

Now that IndVarSimplify is being more aggressive, it occasionally runs
into the problem where ScalarEvolutionExpander's code for avoiding
duplicate expansions makes it difficult to ensure that all expanded
instructions dominate all the instructions that will use them. As a
temporary measure, IndVarSimplify now uses a FixUsesBeforeDefs function
to fix up instructions inserted by SCEVExpander. Fortunately, this code
is contained, and can be easily removed once a more comprehensive
solution is available.

llvm-svn: 71535
2009-05-12 02:17:14 +00:00
Evan Cheng 78a4eb844b Teach LSR to optimize more loop exit compares, i.e. change them to use postinc iv value. Previously LSR would only optimize those which are in the loop latch block. However, if LSR can prove it is safe (and profitable), it's now possible to change those not in the latch blocks to use postinc values.
Also, if the compare is the only use, LSR would place the iv increment instruction before the compare instead in the latch.

llvm-svn: 71485
2009-05-11 22:33:01 +00:00
Dale Johannesen b571463363 Fix PR4188. TailMerging can't tolerate inexact
sucessor info.

llvm-svn: 71478
2009-05-11 21:54:13 +00:00
Dan Gohman 5b3a56bfac Make this grep line a little more specific so that it doesn't
accidentally match something unrelated.

llvm-svn: 71458
2009-05-11 18:49:56 +00:00
Dan Gohman 9521cadff7 When scalarizing a vector BITCAST, check whether the operand has vector
type, rather than assume that it does. If the operand is not vector, it
shouldn't be run through ScalarizeVectorOp. This fixes one of the
testcases in PR3886.

llvm-svn: 71453
2009-05-11 18:30:42 +00:00
Dan Gohman faf75c8c9a Convert a subtract into a negate and an add when it helps x86
address folding.

llvm-svn: 71446
2009-05-11 18:02:53 +00:00
Dale Johannesen 02cb2bf2e3 Reverse a loop that is counting up to a maximum to
count down to 0 instead, under very restricted
circumstances.  Adjust 4 testcases in which this
optimization fires.

llvm-svn: 71439
2009-05-11 17:15:42 +00:00
Evan Cheng 51fa9c7138 Enable loop bb placement optimization.
llvm-svn: 71291
2009-05-08 23:35:49 +00:00
Chris Lattner f1d9b91434 Fix PR4152: asm constraint validation happens before dag combine, so we
need to work a bit to combine things like (x+c1+c2) into x+c3.

llvm-svn: 71232
2009-05-08 18:23:14 +00:00
Evan Cheng 2fa281106a Optimize code placement in loop to eliminate unconditional branches or move unconditional branch to the outside of the loop. e.g.
///       A:                                                                                                                                                                 
///       ...                                                                                                                                                                
///       <fallthrough to B>                                                                                                                                                 
///                                                                                                                                                                          
///       B:  --> loop header                                                                                                                                                
///       ...                                                                                                                                                                
///       jcc <cond> C, [exit]                                                                                                                                               
///                                                                                                                                                                          
///       C:                                                                                                                                                                 
///       ...                                                                                                                                                                
///       jmp B                                                                                                                                                              
///                                                                                                                                                                          
/// ==>                                                                                                                                                                      
///                                                                                                                                                                          
///       A:                                                                                                                                                                 
///       ...                                                                                                                                                                
///       jmp B                                                                                                                                                              
///                                                                                                                                                                          
///       C:  --> new loop header                                                                                                                                            
///       ...                                                                                                                                                                
///       <fallthough to B>                                                                                                                                                  
///                                                                                                                                                                          
///       B:                                                                                                                                                                 
///       ...                                                                                                                                                                
///       jcc <cond> C, [exit] 

llvm-svn: 71209
2009-05-08 06:34:09 +00:00
Bill Wendling 759de47964 THis doesn't fail.
llvm-svn: 71142
2009-05-07 01:41:42 +00:00
Bill Wendling 6144f63bd5 Temporarily revert r71010. It was causing massive failures during self-hosting.
llvm-svn: 71138
2009-05-07 01:27:25 +00:00
Lang Hames ab68cf24bb Renamed Spiller classes (plus uses and related files) to VirtRegRewriter.
llvm-svn: 71057
2009-05-06 02:36:21 +00:00
Evan Cheng cfdbfccd91 Quotes should be printed before private prefix; some code clean up.
llvm-svn: 71032
2009-05-05 22:50:29 +00:00
Dan Gohman bb2f10759e If a MachineBasicBlock has multiple ways of reaching another block,
allow it to have multiple CFG edges to that block. This is needed
to allow MachineBasicBlock::isOnlyReachableByFallthrough to work
correctly. This fixes PR4126.

llvm-svn: 71018
2009-05-05 21:10:19 +00:00
Evan Cheng 9bf9002161 Enable stack coloring with regs at -O3.
llvm-svn: 71010
2009-05-05 20:30:36 +00:00
Chris Lattner be9fa506ad Add basic support for code generation of
addrspace(257) -> FS relative on x86.  Patch by Zoltan Varga!

llvm-svn: 70992
2009-05-05 18:52:19 +00:00
Dan Gohman bb525f7e02 X86FastISel doesn't support the -tailcallopt ABI.
llvm-svn: 70902
2009-05-04 19:50:33 +00:00
Dan Gohman ff08995589 Previously, RecursivelyDeleteDeadInstructions provided an option
of returning a list of pointers to Values that are deleted. This was
unsafe, because the pointers in the list are, by nature of what
RecursivelyDeleteDeadInstructions does, always dangling. Replace this
with a simple callback mechanism. This may eventually be removed if
all clients can reasonably be expected to use CallbackVH.

Use this to factor out the dead-phi-cycle-elimination code from LSR
utility function, and generalize it to use the
RecursivelyDeleteTriviallyDeadInstructions utility function.

This makes LSR more aggressive about eliminating dead PHI cycles;
adjust tests to either be less trivial or to simply expect fewer
instructions.

llvm-svn: 70636
2009-05-02 18:29:22 +00:00
Evan Cheng 99578674fd Mark MOV8mr_NOREX and MOV8rm_NOREX as mayStore / mayLoad respectively.
llvm-svn: 70461
2009-04-30 00:58:57 +00:00
Chris Lattner 5ab42e93c4 fix a regression handling indirect results: these need to be considered
memory operands otherwise the writebacks get lost when the inline asm 
doesn't otherwise have side effects.  This fixes rdar://6839427, though
clang really shouldn't generate these anymore.

llvm-svn: 70455
2009-04-30 00:48:50 +00:00
Nate Begeman 7e6e352735 Fix infinite recursion in the C++ code which handles movddup by making it unnecessary.
llvm-svn: 70425
2009-04-29 22:47:44 +00:00
Evan Cheng 9cce299cc8 spillPhysRegAroundRegDefsUses() may have invalidated iterators stored in fixed_ IntervalPtrs. Reset them.
llvm-svn: 70378
2009-04-29 07:16:34 +00:00
Bill Wendling 084669a1c9 Second attempt:
Massive check in. This changes the "-fast" flag to "-O#" in llc. If you want to
use the old behavior, the flag is -O0. This change allows for finer-grained
control over which optimizations are run at different -O levels.

Most of this work was pretty mechanical. The majority of the fixes came from
verifying that a "fast" variable wasn't used anymore. The JIT still uses a
"Fast" flag. I'll change the JIT with a follow-up patch.

llvm-svn: 70343
2009-04-29 00:15:41 +00:00
Anton Korobeynikov dac88bae4f Properly print 'P' modifier on inline asm memory operands.
This should fix PR3379 and PR4064.
Patch inspired by Edwin Török!

llvm-svn: 70328
2009-04-28 21:49:33 +00:00
Evan Cheng 7e09994cb8 Fix PR4034. Bug in LiveInterval::join when it's compacting new valno's.
llvm-svn: 70291
2009-04-28 06:24:09 +00:00
Evan Cheng c3884be983 Fix for PR4051. When 2address pass delete an instruction, update kill info when necessary.
llvm-svn: 70279
2009-04-28 02:12:36 +00:00
Bill Wendling 56f2987a87 r70270 isn't ready yet. Back this out. Sorry for the noise.
llvm-svn: 70275
2009-04-28 01:04:53 +00:00
Bill Wendling d0ae15946c Massive check in. This changes the "-fast" flag to "-O#" in llc. If you want to
use the old behavior, the flag is -O0. This change allows for finer-grained
control over which optimizations are run at different -O levels.

Most of this work was pretty mechanical. The majority of the fixes came from
verifying that a "fast" variable wasn't used anymore. The JIT still uses a
"Fast" flag. I'm not 100% sure if it's necessary to change it there...

llvm-svn: 70270
2009-04-28 00:21:31 +00:00
Evan Cheng 093e4c578d Fix PR4076. Correctly create live interval of physical register with two-address update.
llvm-svn: 70245
2009-04-27 20:42:46 +00:00
Dan Gohman e99f98262c Permit ChangeCompareStride to rewrite a comparison when the factor
between the comparison's iv stride and the candidate stride is
exactly -1.

llvm-svn: 70244
2009-04-27 20:35:32 +00:00
Dan Gohman 7646637379 Teach getZeroExtendExpr and getSignExtendExpr to use trip-count
information to simplify [sz]ext({a,+,b}) to {zext(a),+,[zs]ext(b)},
as appropriate.

These functions and the trip count code each call into the other, so
this requires careful handling to avoid infinite recursion. During
the initial trip count computation, conservative SCEVs are used,
which are subsequently discarded once the trip count is actually
known.

Among other benefits, this change lets LSR automatically eliminate
some unnecessary zext-inreg and sext-inreg operation where the
operand is an induction variable.

llvm-svn: 70241
2009-04-27 20:16:15 +00:00
Nate Begeman 8d6d4b9289 2nd attempt, fixing SSE4.1 issues and implementing feedback from duncan.
PR2957

ISD::VECTOR_SHUFFLE now stores an array of integers representing the shuffle
mask internal to the node, rather than taking a BUILD_VECTOR of ConstantSDNodes
as the shuffle mask.  A value of -1 represents UNDEF.

In addition to eliminating the creation of illegal BUILD_VECTORS just to 
represent shuffle masks, we are better about canonicalizing the shuffle mask,
resulting in substantially better code for some classes of shuffles.

llvm-svn: 70225
2009-04-27 18:41:29 +00:00
Evan Cheng 0f85bd368c Fix PR4056. It's possible a physical register def is dead if its implicit use is deleted by two-address pass.
llvm-svn: 70213
2009-04-27 17:36:47 +00:00
Dan Gohman 3266391e86 Fix the syntax for a PR number in a test.
llvm-svn: 70208
2009-04-27 15:08:34 +00:00
Dan Gohman be36f5ccda When transforming sext(trunc(load(x))) into sext(smaller load(x)),
the trunc is directly replaced with the smaller load, so don't
try to create a new sext node. This fixes PR4050.

llvm-svn: 70179
2009-04-27 02:00:55 +00:00
Evan Cheng 362acf8a56 Do not share a single unknown val# for all the live ranges merged into a physical sub-register live interval. When coalescer is merging in clobbered virtaul register live interval into a physical register live interval, give each virtual register val# a separate val# in the physical register live interval. Otherwise, the coalescer would have lost track of the definitions information it needs to make correct coalescing decisions.
llvm-svn: 70026
2009-04-25 09:25:19 +00:00
Rafael Espindola c1396a2313 Fix PR 4004 by including the call to __tls_get_addr in X86tlsaddr. This is not
very elegant, but neither is the tls specification :-(

llvm-svn: 69968
2009-04-24 12:59:40 +00:00
Rafael Espindola b93db668b3 Revert 69952. Causes testsuite failures on linux x86-64.
llvm-svn: 69967
2009-04-24 12:40:33 +00:00
Nate Begeman bb881d66f4 PR2957
ISD::VECTOR_SHUFFLE now stores an array of integers representing the shuffle
mask internal to the node, rather than taking a BUILD_VECTOR of ConstantSDNodes
as the shuffle mask.  A value of -1 represents UNDEF.

In addition to eliminating the creation of illegal BUILD_VECTORS just to 
represent shuffle masks, we are better about canonicalizing the shuffle mask,
resulting in substantially better code for some classes of shuffles.

A clean up of x86 shuffle code, and some canonicalizing in DAGCombiner is next.

llvm-svn: 69952
2009-04-24 03:42:54 +00:00
Dan Gohman 723f175bc9 Explicitly pass -tailcallopt=false to these tests so that they
work as intended no matter what the default setting of that
option is.

llvm-svn: 69911
2009-04-23 19:39:41 +00:00
Evan Cheng 1a99a5f501 It has finally happened. Spiller is now using live interval info.
This fixes a very subtle bug. vr defined by an implicit_def is allowed overlap with any register since it doesn't actually modify anything. However, if it's used as a two-address use, its live range can be extended and it can be spilled. The spiller must take care not to emit a reload for the vn number that's defined by the implicit_def. This is both a correctness and performance issue.

llvm-svn: 69743
2009-04-21 22:46:52 +00:00
Evan Cheng d67efaa847 Added a linearscan register allocation optimization. When the register allocator spill an interval with multiple uses in the same basic block, it creates a different virtual register for each of the reloads. e.g.
%reg1498<def> = MOV32rm %reg1024, 1, %reg0, 12, %reg0, Mem:LD(4,4) [sunkaddr39 + 0]
        %reg1506<def> = MOV32rm %reg1024, 1, %reg0, 8, %reg0, Mem:LD(4,4) [sunkaddr42 + 0]
        %reg1486<def> = MOV32rr %reg1506
        %reg1486<def> = XOR32rr %reg1486, %reg1498, %EFLAGS<imp-def,dead>
        %reg1510<def> = MOV32rm %reg1024, 1, %reg0, 4, %reg0, Mem:LD(4,4) [sunkaddr45 + 0]

=>

        %reg1498<def> = MOV32rm %reg2036, 1, %reg0, 12, %reg0, Mem:LD(4,4) [sunkaddr39 + 0]
        %reg1506<def> = MOV32rm %reg2037, 1, %reg0, 8, %reg0, Mem:LD(4,4) [sunkaddr42 + 0]
        %reg1486<def> = MOV32rr %reg1506
        %reg1486<def> = XOR32rr %reg1486, %reg1498, %EFLAGS<imp-def,dead>
        %reg1510<def> = MOV32rm %reg2038, 1, %reg0, 4, %reg0, Mem:LD(4,4) [sunkaddr45 + 0]

From linearscan's point of view, each of reg2036, 2037, and 2038 are separate registers, each is "killed" after a single use. The reloaded register is available and it's often clobbered right away. e.g. In thise case reg1498 is allocated EAX while reg2036 is allocated RAX. This means we end up with multiple reloads from the same stack slot in the same basic block.

Now linearscan recognize there are other reloads from same SS in the same BB. So it'll "downgrade" RAX (and its aliases) after reg2036 is allocated until the next reload (reg2037) is done. This greatly increase the likihood reloads from SS are reused.

This speeds up sha1 from OpenSSL by 5.8%. It is also an across the board win for SPEC2000 and 2006.

llvm-svn: 69585
2009-04-20 08:01:12 +00:00
Dale Johannesen 2f6263fea3 Adjust XFAIL syntax, maybe that will help. The other
way worked for me...

llvm-svn: 69414
2009-04-18 02:01:23 +00:00
Dale Johannesen e34fb6b5ce patch 69408 breaks this by removing the opportunity
for the optimization it's testing to kick in (although
it improves the code, getting rid of all spills).
I don't understand the optimization well enough to
rescue the test, so XFAILing.

llvm-svn: 69409
2009-04-18 00:11:50 +00:00
Rafael Espindola 355fe12c82 For general dynamic TLS access we must use
leaq	foo@TLSGD(%rip), %rdi

as part of the instruction sequence. Using a register other than %rdi and then
copying it to %rdi is not valid.

llvm-svn: 69350
2009-04-17 14:35:58 +00:00
Evan Cheng b96a1082a9 Teach spiller to unfold instructions which modref spill slot when a scratch
register is available and when it's profitable.

e.g.
     xorq  %r12<kill>, %r13
     addq  %rax, -184(%rbp)
     addq  %r13, -184(%rbp)
==>
     xorq  %r12<kill>, %r13
     movq  -184(%rbp), %r12
     addq  %rax, %r12
     addq  %r13, %r12
     movq  %r12, -184(%rbp)

Two more instructions, but fewer memory accesses. It can also open up
opportunities for more optimizations.

llvm-svn: 69341
2009-04-17 01:29:40 +00:00