d8dd194f03
TableGen/X86RecognizableInstr.h: Prune out-of-date "@param isSSE". [-Wdocumentation]
...
llvm-svn: 200628
2014-02-02 10:53:36 +00:00
fa6298a162
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64.
...
llvm-svn: 200626
2014-02-02 09:25:09 +00:00
8e92e85ac7
Simplify some code since VEX and EVEX instructions never have HasOpSizePrefix.
...
llvm-svn: 200625
2014-02-02 07:46:05 +00:00
d402df3ce8
Merge HasVEXPrefix/HasEVEXPrefix/HasXOPPrefix into a 2-bit 'encoding' field in TSFlags.
...
llvm-svn: 200624
2014-02-02 07:08:01 +00:00
10243c8907
Separate x86 opcode maps and 0x66/0xf2/0xf3 prefixes from each other in the TSFlags. This greatly simplifies the switch statements in the disassembler tables and the code emitters.
...
llvm-svn: 200522
2014-01-31 08:47:06 +00:00
ec68866f55
Move REP out of the Prefix field of the X86 format. Give it its own bit. It had special handling anyway and this enables a future patch.
...
llvm-svn: 200520
2014-01-31 07:00:55 +00:00
9b37d35051
Comment out unused macro because of warning
...
Modern compilers (Clang 3.4, GCC 4.8) warn on variadic macros being
introduced in C99, which produces a huge number of useless diagnostics
since this macro is unused in the whole project.
llvm-svn: 200479
2014-01-30 18:55:47 +00:00
bdf33ca08d
Couple minor formatting fixes to the XXXGenDAGISel.inc files.
...
llvm-svn: 200459
2014-01-30 06:42:52 +00:00
0d16d2dc31
Delete the Matchers stored in the SmallVectors in SwitchOpcodeMatcher/SwitchTypeMatcher.
...
llvm-svn: 200377
2014-01-29 07:06:07 +00:00
3fa98a65e9
Propagate MCSubtargetInfo through TableGen's getBinaryCodeForInstr()
...
llvm-svn: 200349
2014-01-28 23:13:18 +00:00
e6c13e4abd
Change MCStreamer EmitInstruction interface to take subtarget info
...
llvm-svn: 200345
2014-01-28 23:12:42 +00:00
5c65e7f345
Use the proper SDK when building iOS sim builds of LLVM and/or Mac OS X builds.
...
llvm-svn: 200335
2014-01-28 19:57:18 +00:00
74169dcf45
Improve handling of EnforceSmallerThan. Remove all types that are smaller from the larger set not just the smallest type from the smaller set. Ensure 'smaller' vectors have the same or fewer total bits. Similar for 'larger' vectors.
...
llvm-svn: 200287
2014-01-28 04:49:01 +00:00
6e1faaf886
Don't use EnforceSmallerThan for EnforceVectorSubVectorTypeIs. EnforceSmallerThan doesn't handle vectors quite right and should really enforce that vectors have the same number of elements. Add explicit checks for vector element count differing in EnforceVectorSubVectorTypeIs instead. This removes some unnecessary type checks in X86GenDAGISel.inc.
...
llvm-svn: 200091
2014-01-25 17:40:33 +00:00
336e1f1179
Fix typo in commment tyep->type.
...
llvm-svn: 200089
2014-01-25 17:34:23 +00:00
5f730e8ef1
Use isConcrete and getConcrete instead of using TypeVec directly.
...
llvm-svn: 200071
2014-01-25 05:33:48 +00:00
6dbcb945a2
Fix EnforceSmallerThan to check !hasVectorTypes on the other type instead of this type to force this type to be scalar.
...
llvm-svn: 200070
2014-01-25 05:17:38 +00:00
3f9978e65a
Remove TGValueTypes.cpp from CMakeLists.txt which I forgot to do in r200036.
...
llvm-svn: 200037
2014-01-24 20:51:32 +00:00
8561de90d7
Replace tablegen uses of EVT with MVT. Add isOverloaded() to MVT to facilitate. Remove TGValueTypes.cpp since its unused now (and may have been before).
...
llvm-svn: 200036
2014-01-24 20:50:47 +00:00
cb40291100
Fix known typos
...
Sweep the codebase for common typos. Includes some changes to visible function
names that were misspelt.
llvm-svn: 200018
2014-01-24 17:20:08 +00:00
9bbf7ca13d
]x86] Allow segment and address-size overrides for CMPS[BWLQ] (PR9385)
...
llvm-svn: 199806
2014-01-22 15:08:36 +00:00
b33c2ef215
[x86] Allow address-size overrides for STOS[BWLQ] (PR9385)
...
llvm-svn: 199804
2014-01-22 15:08:21 +00:00
2ef8d9c05c
[x86] Allow segment and address-size overrides for LODS[BWLQ] (PR9385)
...
llvm-svn: 199803
2014-01-22 15:08:08 +00:00
a2c60197bf
Use ArrayRef to simplify some code.
...
llvm-svn: 199712
2014-01-21 07:20:05 +00:00
caaa2850c0
[x86] Fix disassembly of MOV16ao16 et al.
...
The addition of IC_OPSIZE_ADSIZE in r198759 wasn't quite complete. It
also turns out to have been unnecessary. The disassembler handles the
AdSize prefix for itself, and doesn't care about the difference between
(e.g.) MOV8ao8 and MOB8ao8_16 definitions. So just let them coexist and
don't worry about it.
llvm-svn: 199654
2014-01-20 12:02:53 +00:00
35da3d190a
Allow x86 mov instructions to/from memory with absolute address to be encoded and disassembled with a segment override prefix. Fixes PR16962.
...
llvm-svn: 199364
2014-01-16 07:36:58 +00:00
317e2c499d
replace LeakSanitizerIsTurnedOffForTheCurrentProcess with __lsan_is_turned_off, but this time hide it under __has_feature(address_sanitizer); also include <sanitizer/lsan_interface.h>
...
llvm-svn: 199303
2014-01-15 07:59:37 +00:00
b7c7f38918
Simplify x86 disassembler table handling of when to use TYPE_Rv/TYPE_R16/TYPE_R32 now that HasOpSizePrefix only means 16-bit instructions.
...
llvm-svn: 199295
2014-01-15 05:02:02 +00:00
ad07d08c8d
Add the lld root to llvm-lit, so llvm-lit can be used
...
to run lld tests individually.
llvm-svn: 199264
2014-01-14 22:52:24 +00:00
06234ec147
Add FPExt option to CCValAssign::LocInfo. When generating calling-convention
...
promotion code, Tablegen will now select FPExt for floating point promotions
(previously it had returned AExt, which is not valid for floating point types).
Any out-of-tree targets that were relying on AExt being returned for FP
promotions will need to update their code check for FPExt instead.
llvm-svn: 199252
2014-01-14 19:56:36 +00:00
ad60708a72
Remove stray comma in enum to satisfy -Wpedantic.
...
llvm-svn: 199194
2014-01-14 08:07:10 +00:00
ae11aed9d7
Separate the concept of 16-bit/32-bit operand size controlled by 0x66 prefix and the current mode from the concept of SSE instructions using 0x66 prefix as part of their encoding without being affected by the mode.
...
This should allow SSE instructions to be encoded correctly in 16-bit mode which r198586 probably broke.
llvm-svn: 199193
2014-01-14 07:41:20 +00:00
b19c9dc1a1
AVX-512: Embedded Rounding Control - encoding and printing
...
Changed intrinsics for vrcp14/vrcp28 vrsqrt14/vrsqrt28 - aligned with GCC.
llvm-svn: 199102
2014-01-13 12:55:03 +00:00
749971901a
lit: Provide source locations in cfg files with older Python versions
...
This commit prospectively brings the benefits of r198766 to older supported
Python versions (2.5+).
Tested with Python 2.6, 2.7, 3.1 and 3.3 (!)
llvm-svn: 199009
2014-01-11 14:34:18 +00:00
f0a245944e
lit: execfile() isn't present in Python 3.3
...
On the other hand, exec(compile()) doesn't work in older Python versions in the
2.x series.
This commit introduces exec(compile()) with a fallback to plain exec(). That'll
hopefully hit the sweet spot in terms of version support.
Followup to r198766 which added enhanced source locations for lit cfg parsing.
llvm-svn: 199006
2014-01-11 13:27:28 +00:00
9dc6df5744
Constant propagate MachineInstrClassName.
...
llvm-svn: 198969
2014-01-10 22:59:49 +00:00
f581314932
All backends use MC now.
...
llvm-svn: 198959
2014-01-10 21:49:27 +00:00
1f5cf85fd4
Sink add_llvm_library(gtest_main) to UnitTestMain/CMakeLists.txt.
...
llvm-svn: 198933
2014-01-10 11:02:26 +00:00
a6afef7a51
reapply r198858: Disable LeakSanitizer in TableGen binaries, see PR18325; this time LeakSanitizerIsTurnedOffForTheCurrentProcess is used instead of __lsan_is_turned_off
...
llvm-svn: 198922
2014-01-10 08:05:42 +00:00
2a2a354ee9
Revert "Disable LeakSanitizer in TableGen binaries, see PR18325"
...
To declare or define reserved identifers is undefined behaviour in standard
C++. This needs to be addressed in compiler-rt before it can be used in LLVM.
See the list discussion for details.
This reverts commit r198858.
llvm-svn: 198884
2014-01-09 19:40:55 +00:00
bc60254543
Disable LeakSanitizer in TableGen binaries, see PR18325
...
llvm-svn: 198858
2014-01-09 09:26:26 +00:00
9e628916f6
lit: Provide file location in cfg error messages
...
Python doesn't do a good job at diagnosing string exec() so use execfile()
where available.
This should be a timesaver when trying to get to the bottom of build bot
failures.
Before:
File "llvm/utils/lit/lit/TestingConfig.py", line 93, in load_from_path
exec("exec data in cfg_globals")
File "<string>", line 1, in <module>
File "<string>", line 194, in <module>
NameError: name 'typo' is not defined
After:
File "llvm/utils/lit/lit/TestingConfig.py", line 95, in load_from_path
execfile(path, cfg_globals)
File "clang/test/lit.cfg", line 194, in <module>
typo
^~~~
NameError: name 'typo' is not defined
llvm-svn: 198766
2014-01-08 14:20:59 +00:00
32da3c8f3b
[x86] Fix MOV8ao8 et al for 16-bit mode, fix up disassembler to understand
...
It seems there is no separate instruction class for having AdSize *and*
OpSize bits set, which is required in order to disambiguate between all
these instructions. So add that to the disassembler.
Hm, perhaps we do need an AdSize16 bit after all?
llvm-svn: 198759
2014-01-08 12:58:24 +00:00
2ea87dad77
The rest of r198588. Remove SegOvrBits from X86 TSFlags since they weren't being used.
...
llvm-svn: 198589
2014-01-06 06:57:27 +00:00
d9e1669d1c
Use patterns to remove some duplicate instructions.
...
llvm-svn: 198550
2014-01-05 06:55:48 +00:00
34db6523f3
Fix encoding for PUSH64i16. Add In64BitMode Predicate. Remove disassembler hack.
...
llvm-svn: 198547
2014-01-05 05:46:38 +00:00
c0107977d9
Remove no longer needed x86 disassembler hack.
...
llvm-svn: 198546
2014-01-05 05:10:07 +00:00
0550ce7ac1
Mark x86 _alt instructions as AsmParserOnly so they will be omitted from disassembler without string matches.
...
llvm-svn: 198545
2014-01-05 04:55:55 +00:00
5165cf78b0
Use new ForceDisassemble flag on the 2-byte forms of INC/DEC for 32-bit mode and remove disassmbler table emitter hack.
...
llvm-svn: 198544
2014-01-05 04:32:42 +00:00
3484fc2161
Add a new x86 specific instruction flag to force some isCodeGenOnly instructions to go through to the disassembler tables without resorting to string matches. Apply flag to all _REV instructions.
...
llvm-svn: 198543
2014-01-05 04:17:28 +00:00
NAKAMURA Takumi