Commit Graph

92482 Commits

Author SHA1 Message Date
Sean Silva b7e82adb72 Rename BinaryRef::isBinary to more descriptive DataIsHexString.
And add a doxygen comment.

llvm-svn: 183350
2013-06-05 23:32:31 +00:00
Sean Silva 5fbb154d04 Add BinaryRef binary_size() method.
This avoids making assumptions about the data representation.

llvm-svn: 183349
2013-06-05 23:32:27 +00:00
Sean Silva b4e21201d7 Comment BinaryRef::Data.
Also, state an invariant.

llvm-svn: 183348
2013-06-05 23:32:23 +00:00
Bill Wendling 6fd15ca02e Add space to assert message.
llvm-svn: 183346
2013-06-05 23:13:26 +00:00
Sean Silva 23f3b82790 Add writeAsBinary(raw_ostream &) method to BinaryRef.
Previously, yaml2coff.cpp had a writeHexData static helper function to
do this, but it is generally useful functionality.

Also, validate hex strings up-front to avoid running having to handle
errors "deep inside" the yaml2obj code (it also gives better diagnostics
than it used to).

llvm-svn: 183345
2013-06-05 22:59:00 +00:00
Vincent Lejeune dec1875207 R600: Add a pass that merge Vector Register
Previously commited @183279 but tests were failing, reverted @183286
It was broken because @183336 was missing, now it's there.

llvm-svn: 183343
2013-06-05 21:38:04 +00:00
Sean Silva 69fd257802 [docs] Add link to C++ ABI document.
llvm-svn: 183342
2013-06-05 21:11:16 +00:00
Sean Silva ce4bb3cb12 [docs] Add link to SysV ABI document.
llvm-svn: 183341
2013-06-05 21:11:11 +00:00
Sean Silva 23bcd0ad81 [ELF] Add ELFOSABI_GNU.
ELFOSABI_LINUX is a historical alias for ELFOSABI_GNU according to
<http://www.sco.com/developers/gabi/latest/ch4.eheader.html>.

llvm-svn: 183339
2013-06-05 20:55:58 +00:00
Rafael Espindola 7c346c2cc9 Don't hide the first ELF symbol.
The first symbol on ELF is dummy, but it has a defined content and readelf
normally displays it. With this change llvm-readobj also displays it and we
can check that llvm-mc output is correct according to the standard.

llvm-svn: 183337
2013-06-05 20:33:54 +00:00
Vincent Lejeune 4b5b849753 R600: Schedule copy from phys register at beginning of block
It allows regalloc pass to remove them by trivially assigning associated reg

llvm-svn: 183336
2013-06-05 20:27:35 +00:00
Sean Silva 3b76e4044b yaml2obj: split out COFF logic into separate file
llvm-svn: 183335
2013-06-05 19:56:47 +00:00
Akira Hatanaka da4496c860 [mips] brcond + setgt/setugt instruction selection patterns.
llvm-svn: 183334
2013-06-05 19:49:55 +00:00
Sean Silva 741cebbea0 yaml2obj: add -format=<fmt> to choose input YAML interpretation
See the comment in yaml2obj.cpp for why this is currently needed.
Eventually we can get rid of this, but for now it is needed in order to
make forward progress with adding ELF support, and should be
straightforward to remove later.

Also, preserve the default of COFF, to avoid breaking existing tests.
This policy can easily be changed later though.

llvm-svn: 183332
2013-06-05 18:51:34 +00:00
Jakub Staszak 2f390b755a Use IRBuilder instead of ConstantInt methods. It simplifies code a little bit.
llvm-svn: 183328
2013-06-05 18:27:02 +00:00
Michael Liao 00b20cc924 [PATCH] Fix VGATHER* operand constraints
Add earlyclobber constaints to prevent input register being allocated as
the output register because, according to Intel spec [1], "If any pair
of the index, mask, or destination registers are the same, this
instruction results a UD fault."

---
[1] http://software.intel.com/sites/default/files/319433-014.pdf

llvm-svn: 183327
2013-06-05 18:12:26 +00:00
Rafael Espindola 4e75df1560 Represent symbols with a SymbolIndex,SectionIndex pair.
With this patch we use the SectionIndex directly, instead of counting the
number of symbol tables. This saves a DenseMap lookup every time we want to
find which symbol a relocation refers to.

Also simplify based on the fact that there is at most one SHT_SYMTAB and one
SHT_DYNSYM.

llvm-svn: 183326
2013-06-05 17:54:19 +00:00
Arnold Schwaighofer 81910d0ee1 ARM sched model: Add more ALU and CMP instructions
Reapply of 183258.

llvm-svn: 183321
2013-06-05 16:36:51 +00:00
Arnold Schwaighofer 2773f1deb4 ARM sched model: Add divsion, loads, branches, vfp cvt
Add some generic SchedWrites and assign resources for Swift and Cortex A9.

Reapply of r183257. (Removed empty InstRW for division on swift)

llvm-svn: 183319
2013-06-05 16:06:11 +00:00
Arnold Schwaighofer e937592ef2 ARMInstrInfo: Improve isSwiftFastImmShift
An instruction with less than 3 inputs is trivially a fast immediate shift.

Reapply of 183256, should not have caused the tablegen segfault on linux either.

llvm-svn: 183314
2013-06-05 14:59:36 +00:00
Arnold Schwaighofer 218f6d8f59 SubtargetEmitter fix
Don't output data if we are supposed to ignore the record.

Reapply of 183255, I don't think this was causing the tablegen segfault on linux
testers.

llvm-svn: 183311
2013-06-05 14:06:50 +00:00
Mihai Popa 0e9892fe3a This is a simple patch that changes RRX and RRXS to accept all registers as operands.
According to the ARM reference manual, RRX(S) have defined encodings for lr, pc and sp.

llvm-svn: 183307
2013-06-05 13:23:51 +00:00
Sylvestre Ledru 15a5eea3a1 The GNU/HURD is also using the libc. Therefor, endian.h should be included, not machine/endian.h. See full build log https://buildd.debian.org/status/fetch.php?pkg=llvm-toolchain-3.3&arch=hurd-i386&ver=1%3A3.3~%2Brc3-1~exp1&stamp=1370358869
llvm-svn: 183303
2013-06-05 09:17:26 +00:00
Andrew Trick 78a085170a Fix a tblgen subtargetemitter bug, for future Swift support.
This fixes some of the ridiculously complex code for optimizing the
machine model tables that are shared among all processors of a given
target. A9 and Swift both use the "special" feature that maps old
itinerary classes to new machine model defs. They map different
overlapping subsets of instructions, which wasn't handled correctly.

llvm-svn: 183302
2013-06-05 06:55:20 +00:00
David Blaikie 6f1a8067fb PR15662: Optimized debug info produces out of order function parameters
When a function is inlined we lazily construct the variables
representing the function's parameters. After that, we add any remaining
unused parameters.

If the function doesn't use all the parameters, or uses them out of
order, then the DWARF would produce them in that order, producing a
parameter order that doesn't match the source.

This fix causes us to always keep the arg variables at the start of the
variable list & in the original order from the source.

llvm-svn: 183297
2013-06-05 05:39:59 +00:00
Tom Stellard aad5376fb6 R600: Make sure to schedule AR register uses and defs in the same clause
Reviewed-by: vljn at ovi.com
llvm-svn: 183294
2013-06-05 03:43:06 +00:00
Rafael Espindola 0fd21ca699 Don't print default values for NumberOfAuxSymbols and AuxiliaryData.
llvm-svn: 183293
2013-06-05 03:20:13 +00:00
Rafael Espindola 7595447b15 Handle (at least don't crash on) relocations with no symbols.
Should fix the MCJIT tests on PPC.

llvm-svn: 183288
2013-06-05 02:55:01 +00:00
Rafael Espindola 8e71301637 Move BinaryRef to a new include/llvm/Object/YAML.h file.
It will be used for ELF dumping too.

llvm-svn: 183287
2013-06-05 02:32:26 +00:00
Rafael Espindola beef23fe21 Revert "R600: Add a pass that merge Vector Register"
This reverts commit r183279. CodeGen/R600/texture-input-merge.ll was failing.

llvm-svn: 183286
2013-06-05 01:48:30 +00:00
Rafael Espindola 806f006490 Handle relocations that don't point to symbols.
In ELF (as in MachO), not all relocations point to symbols. Represent this
properly by using a symbol_iterator instead of a SymbolRef. Update llvm-readobj
ELF's dumper to handle relocatios without symbols.

llvm-svn: 183284
2013-06-05 01:33:53 +00:00
Sean Silva 0d65a762ac [docs] Replace non-existent LLVM_YAML_UNIQUE_TYPE() macro
LLVM_YAML_STRONG_TYPEDEF() is the correct macro to perform this function.

llvm-svn: 183280
2013-06-04 23:36:41 +00:00
Vincent Lejeune a45aafabfe R600: Add a pass that merge Vector Register
llvm-svn: 183279
2013-06-04 23:17:26 +00:00
Vincent Lejeune c689679173 R600: Const/Neg/Abs can be folded to dot4
llvm-svn: 183278
2013-06-04 23:17:15 +00:00
Evan Cheng 4ec309700b Cortex-R5 can issue Thumb2 integer division instructions.
llvm-svn: 183275
2013-06-04 22:52:09 +00:00
Arnold Schwaighofer 2a70c69d31 Revert series of sched model patches until I figure out what is going on.
llvm-svn: 183273
2013-06-04 22:35:17 +00:00
Arnold Schwaighofer 0024b8bd73 ARM sched model: Add VFP div instruction on Swift
llvm-svn: 183271
2013-06-04 22:16:08 +00:00
Arnold Schwaighofer 89901730b1 ARM sched model: Add SIMD/VFP load/store instructions on Swift
llvm-svn: 183270
2013-06-04 22:16:07 +00:00
Arnold Schwaighofer bc61f0912c ARM sched model: Add integer VFP/SIMD instructions on Swift
llvm-svn: 183269
2013-06-04 22:16:05 +00:00
Arnold Schwaighofer 83a4197085 ARM sched model: Add integer load/store instructions on Swift
llvm-svn: 183268
2013-06-04 22:16:04 +00:00
Arnold Schwaighofer f77ea45488 ARM sched model: Add integer arithmetic instructions on Swift
llvm-svn: 183267
2013-06-04 22:16:02 +00:00
Arnold Schwaighofer be3a06c85f ARM sched model: Cortex A9 - More InstRW sched resources
Add more InstRW mappings.

llvm-svn: 183266
2013-06-04 22:16:00 +00:00
Arnold Schwaighofer 76e2394799 ARM sched model: Add branch thumb instructions
llvm-svn: 183265
2013-06-04 22:15:59 +00:00
Arnold Schwaighofer 17359d9ba2 ARM sched model: Add branch thumb2 instructions
llvm-svn: 183264
2013-06-04 22:15:57 +00:00
Arnold Schwaighofer bdb5687468 ARM sched model: Add branch instructions
llvm-svn: 183263
2013-06-04 22:15:56 +00:00
Arnold Schwaighofer e971b08765 ARM sched model: Add preload thumb2 instructions
llvm-svn: 183262
2013-06-04 22:15:54 +00:00
Arnold Schwaighofer ab88312f51 ARM sched model: Add preload instructions
llvm-svn: 183261
2013-06-04 22:15:52 +00:00
Arnold Schwaighofer 83fa45629e ARM sched model: Add more ALU and CMP thumb instructions
llvm-svn: 183260
2013-06-04 22:15:51 +00:00
Arnold Schwaighofer 529c2be334 ARM sched model: Add more ALU and CMP thumb2 instructions
llvm-svn: 183259
2013-06-04 22:15:49 +00:00
Arnold Schwaighofer b6843f17eb ARM sched model: Add more ALU and CMP instructions
llvm-svn: 183258
2013-06-04 22:15:47 +00:00