Commit Graph

145752 Commits

Author SHA1 Message Date
Chad Rosier 5b0e91a700 Dead code.
llvm-svn: 177450
2013-03-19 22:12:47 +00:00
Jordan Rose 15a185f1e0 [analyzer] Add a test case for diagnostic suppression on a graph with cycles.
(see previous commit)

llvm-svn: 177449
2013-03-19 22:10:44 +00:00
Jordan Rose 431e4e4d0e Revert "[analyzer] Do part of the work to find shortest bug paths up front."
The whole reason we were doing a BFS in the first place is because an
ExplodedGraph can have cycles. Unfortunately, my removeErrorNode "update"
doesn't work at all if there are cycles.

I'd still like to be able to avoid doing the BFS every time, but I'll come
back to it later.

This reverts r177353 / 481fa5071c203bc8ba4f88d929780f8d0f8837ba.

llvm-svn: 177448
2013-03-19 22:10:35 +00:00
Matt Kopec 9502ac6112 Mark TestChangeValueAPI.py as expected fail with gcc as it still reproduces.
llvm-svn: 177447
2013-03-19 22:00:10 +00:00
Chad Rosier f3c04f6a9f [ms-inline asm] Move the immediate asm rewrite into the target specific
logic as a QOI cleanup.  No functional change.  Tests already in place.
rdar://13456414

llvm-svn: 177446
2013-03-19 21:58:18 +00:00
Quentin Colombet 2393cb92b8 Update global merge pass according to Duncan's advices:
- Remove useless includes
- Change misleading comments
- Move code into doFinalization

llvm-svn: 177445
2013-03-19 21:46:49 +00:00
Tobias Grosser 84b81dee55 ScopDetect: Remove some redundant semicolons
llvm-svn: 177444
2013-03-19 21:44:07 +00:00
Howard Hinnant 591ebe3cbb This is an optimization which produces improved launching time. There should be no functionality change. Clients should see no ABI differences.
llvm-svn: 177443
2013-03-19 21:34:48 +00:00
Jakob Stoklund Olesen 9bd6b8bd96 Annotate X86InstrCompiler.td with SchedRW lists.
Add a new WriteZero SchedWrite type for the common dependency-breaking
instructions that clear a register.

llvm-svn: 177442
2013-03-19 21:16:56 +00:00
Chad Rosier 993bd120bc Test case for r177439 and r177440.
llvm-svn: 177441
2013-03-19 21:12:57 +00:00
Chad Rosier 17d3799352 [ms-inline asm] Remove the brackets from X86Operand in the IR. These will be
added back in by X86AsmPrinter::printIntelMemReference() during codegen.
Previously, this following example

  void t() {
    int i;
    __asm mov eax, [i]
  }

would generate the below assembly

  mov eax, dword ptr [[eax]]

which resulted in a fatal error when compiling.  Test case coming on the
clang side.
rdar://13444264

llvm-svn: 177440
2013-03-19 21:12:14 +00:00
Chad Rosier 7ca135b25f [ms-inline asm] Create a helper function, CreateMemForInlineAsm, that creates
an X86Operand, but also performs a Sema lookup and adds the sizing directive
when appropriate.  Use this when parsing a bracketed statement.  This is
necessary to get the instruction matching correct as well.  Test case coming
on clang side.
rdar://13455408

llvm-svn: 177439
2013-03-19 21:11:56 +00:00
Tobias Grosser d2fbbf0f74 IndependentBlocks: Add a couple of test cases.
llvm-svn: 177438
2013-03-19 21:11:25 +00:00
Bill Wendling 04d57c7b2c Register the GCOV writeout functions so that they're emitted serially.
We don't want to write out >1000 files at the same time. That could make things
prohibitively expensive. Instead, register the "writeout" function so that it's
emitted serially.
<rdar://problem/12439551>

llvm-svn: 177437
2013-03-19 21:03:22 +00:00
Bill Wendling e647659d58 Add a way to register and execute "writeout" functions.
It may be prohibitively expensive to write out >1000 files at the same time. So
we would rather emit them serially. These functions allow the GCOV
implementation to register the functions that writeout the GCOV information per
compile unit. At exit, they are written.
<rdar://problem/12439551>

llvm-svn: 177436
2013-03-19 21:01:19 +00:00
Fariborz Jahanian 1c5d4c54a9 Objective-C [qoi]: Provide improved parse diagnostics when
closing rbrace is missing in an ObjC class declaration.
Can do beter than this, but it involves addition of
overhead which will be present in correct code.
// rdar://6854840

llvm-svn: 177435
2013-03-19 20:27:40 +00:00
Hal Finkel 559754a482 Add a comment to the CodeGen/PowerPC/asym-regclass-copy.ll test
llvm-svn: 177434
2013-03-19 20:22:32 +00:00
Tobias Grosser d4ff632fa9 ScopDetection: Add a couple of test cases
llvm-svn: 177433
2013-03-19 20:15:19 +00:00
Arnaud A. de Grandmaison 87c473f0d1 IndVarSimplify: do not recompute an IV value outside of the loop if :
- it is trivially known to be used inside the loop in a way that can not be optimized away
- there is no use outside of the loop which can take advantage of the computation hoisting

llvm-svn: 177432
2013-03-19 20:00:22 +00:00
Ulrich Weigand 01dd4c1a12 Add missing mayLoad flag to LHAUX8 and LWAUX.
All pre-increment load patterns need to set the mayLoad flag (since
they don't provide a DAG pattern).

This was missing for LHAUX8 and LWAUX, which is added by this patch.

llvm-svn: 177431
2013-03-19 19:53:27 +00:00
Ulrich Weigand f8030096b1 Rewrite LHAU8 pattern to use standard memory operand.
As opposed to to pre-increment store patterns, the pre-increment
load patterns were already using standard memory operands, with
the sole exception of LHAU8.

As there's no real reason why LHAU8 should be different here,
this patch simply rewrites the pattern to also use a memri
operand, just like all the other patterns.

llvm-svn: 177430
2013-03-19 19:52:30 +00:00
Ulrich Weigand d850167a19 Rewrite pre-increment store patterns to use standard memory operands.
Currently, pre-increment store patterns are written to use two separate
operands to represent address base and displacement:

  stwu $rS, $ptroff($ptrreg)

This causes problems when implementing the assembler parser, so this
commit changes the patterns to use standard (complex) memory operands
like in all other memory access instruction patterns:

  stwu $rS, $dst

To still match those instructions against the appropriate pre_store
SelectionDAG nodes, the patch uses the new feature that allows a Pat
to match multiple DAG operands against a single (complex) instruction
operand.

Approved by Hal Finkel.

llvm-svn: 177429
2013-03-19 19:52:04 +00:00
Ulrich Weigand e618abd6e0 Extend TableGen instruction selection matcher to improve handling
of complex instruction operands (e.g. address modes).

Currently, if a Pat pattern creates an instruction that has a complex
operand (i.e. one that consists of multiple sub-operands at the MI
level), this operand must match a ComplexPattern DAG pattern with the
correct number of output operands.

This commit extends TableGen to alternatively allow match a complex
operands against multiple separate operands at the DAG level.

This allows using Pat patterns to match pre-increment nodes like
pre_store (which must have separate operands at the DAG level) onto
an instruction pattern that uses a multi-operand memory operand,
like the following example on PowerPC (will be committed as a
follow-on patch):

  def STWU  : DForm_1<37, (outs ptr_rc:$ea_res), (ins GPRC:$rS, memri:$dst),
                    "stwu $rS, $dst", LdStStoreUpd, []>,
                    RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;

  def : Pat<(pre_store GPRC:$rS, ptr_rc:$ptrreg, iaddroff:$ptroff),
            (STWU GPRC:$rS, iaddroff:$ptroff, ptr_rc:$ptrreg)>;

Here, the pair of "ptroff" and "ptrreg" operands is matched onto the
complex operand "dst" of class "memri" in the "STWU" instruction.

Approved by Jakob Stoklund Olesen.

llvm-svn: 177428
2013-03-19 19:51:09 +00:00
Ulrich Weigand fd24544ff8 Fix sub-operand size mismatch in tocentry operands.
The tocentry operand class refers to 64-bit values (it is only used in 64-bit,
where iPTR is a 64-bit type), but its sole suboperand is designated as 32-bit
type.  This causes a mismatch to be detected at compile-time with the TableGen
patch I'll check in shortly.

To fix this, this commit changes the suboperand to a 64-bit type as well.

llvm-svn: 177427
2013-03-19 19:50:30 +00:00
Ulrich Weigand 80d9ad398d Remove an invalid and unnecessary Pat pattern from the X86 backend:
def : Pat<(load (i64 (X86Wrapper tglobaltlsaddr :$dst))),
            (MOV64rm tglobaltlsaddr :$dst)>;

This pattern is invalid because the MOV64rm instruction expects a
source operand of type "i64mem", which is a subclass of X86MemOperand
and thus actually consists of five MI operands, but the Pat provides
only a single MI operand ("tglobaltlsaddr" matches an SDnode of
type ISD::TargetGlobalTLSAddress and provides a single output).

Thus, if the pattern were ever matched, subsequent uses of the MOV64rm
instruction pattern would access uninitialized memory.  In addition,
with the TableGen patch I'm about to check in, this would actually be
reported as a build-time error.

Fortunately, the pattern does in fact never match, for at least two
independent reasons.

First, the code generator actually never generates a pattern of the
form (load (X86Wrapper (tglobaltlsaddr))).  For most combinations of
TLS and code models, (tglobaltlsaddr) represents just an offset that
needs to be added to some base register, so it is never directly
dereferenced.  The only exception is the initial-exec model, where
(tglobaltlsaddr) refers to the (pc-relative) address of a GOT slot,
which *is* in fact directly dereferenced: but in that case, the
X86WrapperRIP node is used, not X86Wrapper, so the Pat doesn't match.

Second, even if some patterns along those lines *were* ever generated,
we should not need an extra Pat pattern to match it.  Instead, the
original MOV64rm instruction pattern ought to match directly, since
it uses an "addr" operand, which is implemented via the SelectAddr
C++ routine; this routine is supposed to accept the full range of
input DAGs that may be implemented by a single mov instruction,
including those cases involving ISD::TargetGlobalTLSAddress (and
actually does so e.g. in the initial-exec case as above).

To avoid build breaks (due to the above-mentioned error) after the
TableGen patch is checked in, I'm removing this Pat here.

llvm-svn: 177426
2013-03-19 19:49:52 +00:00
Greg Clayton 1080fafb69 Update Sketch test case to capture this and use accessors for debugger, target, process and thread.
llvm-svn: 177425
2013-03-19 19:30:33 +00:00
Andy Gibbs 1fb8ce4002 Fix "control reaches end of non-void function" compiling lld on gcc.
llvm-svn: 177424
2013-03-19 19:13:36 +00:00
Hal Finkel 638a9fa43e Prepare to make r0 an allocatable register on PPC
Currently the PPC r0 register is unconditionally reserved. There are two reasons
for this:

 1. r0 is treated specially (as the constant 0) by certain instructions, and so
    cannot be used with those instructions as a regular register.

 2. r0 is used as a temporary register in the CR-register spilling process
    (where, under some circumstances, we require two GPRs).

This change addresses the first reason by introducing a restricted register
class (without r0) for use by those instructions that treat r0 specially. These
register classes have a new pseudo-register, ZERO, which represents the r0-as-0
use. This has the side benefit of making the existing target code simpler (and
easier to understand), and will make it clear to the register allocator that
uses of r0 as 0 don't conflict will real uses of the r0 register.

Once the CR spilling code is improved, we'll be able to allocate r0.

Adding these extra register classes, for some reason unclear to me, causes
requests to the target to copy 32-bit registers to 64-bit registers. The
resulting code seems correct (and causes no test-suite failures), and the new
test case covers this new kind of asymmetric copy.

As r0 is still reserved, no functionality change intended.

llvm-svn: 177423
2013-03-19 18:51:05 +00:00
Edwin Vane c383960be9 Don't replace macro usage if macro body has NULL
In case of macro body expansion, check to see if the macro is named NULL and
don't replace inside the macro body. This fixes the case when NULL appears
inside the macro body and the transform replaces the usage of the macro with
nullptr. This is an easy fix for the problem for now and we should analyze the
macro body to see if it expands to only NullToPointer in the future for a more
robust solution that takes care of user defined macros that behaves like NULL.

Other changes:
- Moved complex macro tests to macros.cpp
- Added new test cases.
- Added checks to make sure that the macro bodies are not modified by the tool.

Fixes: PR15396

Author: Tareq A Siraj <tareq.a.siraj@intel.com>
llvm-svn: 177422
2013-03-19 18:47:03 +00:00
Nadav Rotem 0f1bc60d51 Optimize sext <4 x i8> and <4 x i16> to <4 x i64>.
Patch by Ahmad, Muhammad T <muhammad.t.ahmad@intel.com>

llvm-svn: 177421
2013-03-19 18:38:27 +00:00
Daniel Jasper 2bd32ca92a Fix indentation for case: // comment.
Before:
switch (x) {
case 1:
    // Do amazing stuff
    {
  g();
  f();
}
}

After:
switch (x) {
case 1:
  // Do amazing stuff
  {
    g();
    f();
  }
}

llvm-svn: 177420
2013-03-19 18:33:58 +00:00
Adrian Prantl 6a38438e55 Relax test to allow for attributes on other architectures. Caught by powerpc64-unknown-linux-gnu buildbot.
llvm-svn: 177419
2013-03-19 18:20:35 +00:00
Jakob Stoklund Olesen af39940bad Annotate X86InstrExtension.td with SchedRW lists.
llvm-svn: 177418
2013-03-19 18:03:58 +00:00
Jakob Stoklund Olesen caf3d89ff5 Annotate a lot of X86InstrInfo.td with SchedRW lists.
llvm-svn: 177417
2013-03-19 18:03:55 +00:00
Greg Clayton 53c5ddf0d7 Fixed incorrect python that was trying to validate that we got a valid lldb.SBThread object by checking to see if it is equal to "None".
This test is incorrect as functions that return lldb.SBThread objects never return None, they just return lldb.SBThread objects that contain invalid opaque classes. 

llvm-svn: 177416
2013-03-19 17:59:30 +00:00
Alexander Kornienko afcef33de7 Split long lines in multi-line comments.
Summary: This is implementation for /* */ comments only.

Reviewers: djasper, klimek

Reviewed By: djasper

CC: cfe-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D547

llvm-svn: 177415
2013-03-19 17:41:36 +00:00
Chad Rosier 4f667e88d0 Update test for r177413.
llvm-svn: 177414
2013-03-19 17:32:36 +00:00
Chad Rosier 120eefd104 [ms-inline asm] Move the size directive asm rewrite into the target specific
logic as a QOI cleanup.
rdar://13445327

llvm-svn: 177413
2013-03-19 17:32:17 +00:00
Eli Bendersky f78a9786ee Update documentation of llvm-link to reflect recent cleanups.
llvm-svn: 177411
2013-03-19 16:04:19 +00:00
Eli Bendersky 138b684882 Remove stale comment
llvm-svn: 177410
2013-03-19 16:04:02 +00:00
Alexey Samsonov dd71c5b84a Fix for r177390: map values are pointers, use DeleteContainerSeconds() instead of .clear()
llvm-svn: 177409
2013-03-19 15:33:18 +00:00
Tobias Grosser 14a2d7b9f0 cindex.py: Handle NULL pointers when parsing translation units
The code inside cindex.py was comparing NULL pointer returned by
clang_parseTranslationUnit and clang_createTranslationUnit with None.
However, as illustrated by the two tests I've added, those conditions
were ineffective which resulted in assert triggering later on.

Instead, a pointer is now treated as a boolean value, a NULL pointer being
False.

Contributed-by: Xavier Deguillard <deguilx@gmail.com>
llvm-svn: 177408
2013-03-19 15:30:48 +00:00
Evgeniy Stepanov 9a8f0f55d5 [asan] s/ASAN_POSIX/SANITIZER_POSIX/
llvm-svn: 177407
2013-03-19 15:26:41 +00:00
Eli Bendersky 0f7fd36f86 The Linker interface has some dead code after the cleanup in r172749
(and possibly others). The attached patch removes it, and tries to
update comments accordingly.

llvm-svn: 177406
2013-03-19 15:26:24 +00:00
Hal Finkel 6681486375 Cleanup PPC64 unaligned i64 load/store
Remove an accidentally-added instruction definition and add a comment in the
test case. This is in response to a post-commit review by Bill Schmidt.

No functionality change intended.

llvm-svn: 177404
2013-03-19 15:23:39 +00:00
Sean Silva 8eaf3ca770 [docs] Remove incorrect information about lit.
Lit does support redirects in the 2>&1 style.

llvm-svn: 177403
2013-03-19 15:22:02 +00:00
Rafael Espindola 513499d0ad Don't try to set attributes in alias, they have none.
llvm-svn: 177402
2013-03-19 15:03:47 +00:00
Evgeniy Stepanov 95eaa21637 [sanitizer] More renamed macros.
llvm-svn: 177401
2013-03-19 14:54:17 +00:00
Evgeniy Stepanov 0af672326a [sanitizer] Replace more platform checks with SANITIZER_ constants.
llvm-svn: 177400
2013-03-19 14:33:38 +00:00
Rafael Espindola a0851a2cb0 Revert r177329.
If this should not happen, we should have an assert.
If it should happen, we should have a test and remove the comment.

In no case should we have this self inconsistent code.

llvm-svn: 177399
2013-03-19 14:32:23 +00:00