Commit Graph

157432 Commits

Author SHA1 Message Date
Dan Gohman 32ce5ca07c [WebAssembly] Make stack-pointer imports mutable.
This is not currently valid by the wasm spec, however:
 - It replaces doing set_global on an immutable global, which is also
   not valid.
 - It's expected be valid in the near future:
   https://github.com/WebAssembly/threads/blob/master/proposals/threads/Globals.md
 - This only occurs before linking, so a fully linked object will be
   valid.

llvm-svn: 319810
2017-12-05 18:29:48 +00:00
Rafael Espindola 74de7e0791 Simplify test.
It can use attrib instead of icacls.

llvm-svn: 319809
2017-12-05 18:26:23 +00:00
Matt Arsenault 7f0a527300 AMDGPU: Fix infinite loop with dbg_value
Surprisingly SIOptimizeExecMaskingPreRA can infinite loop
in some case with DBG_VALUE. Most tests using dbg_value are
run at -O0, so don't run this pass. This seems to only
happen when the value argument is undef.

llvm-svn: 319808
2017-12-05 18:23:17 +00:00
Joel Galenson ea0bafda8a [CVP] Remove some {s|u}sub.with.overflow checks.
This uses ConstantRange::makeGuaranteedNoWrapRegion's newly-added handling for subtraction to allow CVP to remove some subtraction overflow checks.

Differential Revision: https://reviews.llvm.org/D40039

llvm-svn: 319807
2017-12-05 18:14:24 +00:00
Joel Galenson c32b0fc249 [ConstantRange] Support subtraction in makeGuaranteedNoWrapRegion.
Previously ConstantRange::makeGuaranteedNoWrapRegion only handled addition.  This adds support for subtraction.

Differential Revision: https://reviews.llvm.org/D40036

llvm-svn: 319806
2017-12-05 18:14:23 +00:00
Simon Pilgrim 65f805fe30 [X86][X87] Tag FCMOV instruction scheduler classes
llvm-svn: 319804
2017-12-05 18:01:26 +00:00
Joel Galenson d9500bc533 Test commit.
I removed a space at the end of a comment.  NFC.

llvm-svn: 319803
2017-12-05 17:59:07 +00:00
Craig Topper 8adcbe8c9f [SelectionDAG] Remove the code that handles SETCC with a scalar result type from vector widening.
There's no such thing as a setcc with vector operands and scalar result. And if we're trying to widen the result we would have to already be looking at a vector result type.

So this patch renames the VSETCC function as the SETCC function and delete the original SETCC function.

llvm-svn: 319799
2017-12-05 17:37:19 +00:00
Craig Topper 558cc48b44 [SelectionDAG] Remove unused method declaration.
The method implementation was removed in r318982.

llvm-svn: 319798
2017-12-05 17:37:17 +00:00
Dan Gohman c2c997718d [WebAssembly] Implement WASM_STACK_POINTER.
Use the .stack_pointer directive to implement WASM_STACK_POINTER for
specifying a global variable to be the stack pointer.

llvm-svn: 319797
2017-12-05 17:23:43 +00:00
Dan Gohman f7172f4ab0 [WebAssembly] Don't emit .import_global for the wasm target.
.import_global is used by the ELF-based target and not needed by the wasm
target.

llvm-svn: 319796
2017-12-05 17:21:57 +00:00
Xinliang David Li cc35bc9efc [PGO] detect infinite loop and form MST properly
Differential Revision: http://reviews.llvm.org/D40702

llvm-svn: 319794
2017-12-05 17:19:41 +00:00
Rafael Espindola 20569e96e9 Delete temp file if rename fails.
Without this when lld failed to replace the output file it would leave
the temporary behind. The problem is that the existing logic is

- cancel the delete flag
- rename

We have to cancel first to avoid renaming and then crashing and
deleting the old version. What is missing then is deleting the
temporary file if the rename fails.

This can be an issue on both unix and windows, but I am not sure how
to cause the rename to fail reliably on unix. I think it can be done
on ZFS since it has an ACL system similar to what windows uses, but
adding support for checking that in llvm-lit is probably not worth it.

llvm-svn: 319786
2017-12-05 16:40:56 +00:00
Simon Pilgrim d9f1ae3266 [X86][AVX512] Tag VNNIW instruction scheduler classes
llvm-svn: 319784
2017-12-05 16:17:21 +00:00
Alexey Bataev d4683e6ef1 [InstCombine] Additional test for PR35354, NFC.
llvm-svn: 319783
2017-12-05 16:15:55 +00:00
Simon Pilgrim 4a9b1e1273 [X86][AVX512] Drop some default NoItinerary arguments that aren't needed any more
llvm-svn: 319782
2017-12-05 16:10:57 +00:00
Jina Nahias 51c1a627c2 [x86][AVX512] Lowering kunpack intrinsics to LLVM IR
This patch, together with a matching clang patch (https://reviews.llvm.org/D39719), implements the lowering of X86 kunpack intrinsics to IR.

Differential Revision: https://reviews.llvm.org/D39720

Change-Id: I4088d9428478f9457f6afddc90bd3d66b3daf0a1
llvm-svn: 319778
2017-12-05 15:42:56 +00:00
Bjorn Pettersson 5abbad7999 Add REQUIRES asserts in combine_loads_from_build_pair.ll
A fixup of r319771, that was causing buildbot failures.

llvm-svn: 319775
2017-12-05 15:26:01 +00:00
Sam Parker 0a436a9d62 [DAGCombine] Move AND nodes to multiple load leaves
Search from AND nodes to find whether they can be propagated back to
loads, so that the AND and load can be combined into a narrow load.
We search through OR, XOR and other AND nodes and all bar one of the
leaves are required to be loads or constants. The exception node then
needs to be masked off meaning that the 'and' isn't removed, but the
loads(s) are narrowed still.

Differential Revision: https://reviews.llvm.org/D39604

llvm-svn: 319773
2017-12-05 15:13:47 +00:00
Simon Pilgrim 4d08aedba3 [X86][AVX512] Tag VPMADD52/VPSADBW instruction scheduler classes
llvm-svn: 319772
2017-12-05 14:59:40 +00:00
Bjorn Pettersson 823b299fbc [DAGCombine] Handle big endian correctly in CombineConsecutiveLoads
Summary:
Found out, at code inspection, that there was a fault in
DAGCombiner::CombineConsecutiveLoads for big-endian targets.

A BUILD_PAIR is always having the least significant bits of
the composite value in element 0. So when we are doing the checks
for consecutive loads, for big endian targets, we should check
if the load to elt 1 is at the lower address and the load
to elt 0 is at the higher address.

Normally this bug only resulted in missed oppurtunities for
doing the load combine. I guess that in some rare situation it
could lead to faulty combines, but I've not seen that happen.

Note that this patch actually will trigger load combine for
some big endian regression tests.
One example is test/CodeGen/PowerPC/anon_aggr.ll where we now get
  t76: i64,ch = load<LD8[FixedStack-9]
instead of
  t37: i32,ch = load<LD4[FixedStack-10]>
  t35: i32,ch = load<LD4[FixedStack-9]>
  t41: i64 = build_pair t37, t35
before legalization. Then the legalization will split the LD8
into two loads, so the end result is the same. That should
verify that the transfomation is correct now.

Reviewers: niravd, hfinkel

Reviewed By: niravd

Subscribers: nemanjai, llvm-commits

Differential Revision: https://reviews.llvm.org/D40444

llvm-svn: 319771
2017-12-05 14:50:05 +00:00
Simon Pilgrim 71660c61e6 [X86][AVX512] Add missing scalar CMPSS/CMPSD logic scheduler classes
llvm-svn: 319770
2017-12-05 14:34:42 +00:00
Mikael Holmen 0a3e98062f Bail out of a SimplifyCFG switch table opt at undef values.
Summary:
A true or false result is expected from a comparison, but it seems the possibility of undef was overlooked, which could lead to a failed assert. This is fixed by this patch by bailing out if we encounter undef.

The bug is old and the assert has been there since the end of 2014, so it seems this is unusual enough to forego optimization.

Patch by JesperAntonsson.

Reviewers: spatel, eeckstein, hans

Reviewed By: hans

Subscribers: uabelho, llvm-commits

Differential Revision: https://reviews.llvm.org/D40639

llvm-svn: 319768
2017-12-05 14:14:00 +00:00
Simon Pilgrim b9b46394e3 [X86][AVX512] Cleanup bit logic scheduler classes
llvm-svn: 319767
2017-12-05 14:04:23 +00:00
Sam Parker 8b73630c32 [DAGCombine] isLegalNarrowLoad function (NFC)
Pull the checks upon the load out from ReduceLoadWidth into their own
function.

Differential Revision: https://reviews.llvm.org/D40833

llvm-svn: 319766
2017-12-05 14:03:51 +00:00
Simon Pilgrim fd3a2632e5 [X86][AVX512] Tag scalar CVT and CMP instruction scheduler classes
llvm-svn: 319765
2017-12-05 13:49:44 +00:00
Dean Michael Berris bf77c23576 [XRay][docs] Document xray_mode and log registration API.
This marks certain flags in XRay as deprecated (in particular,
`xray_naive_log=` and `xray_fdr_log=`), and recommends the use of the
`xray_mode=` flag.

llvm-svn: 319763
2017-12-05 12:43:12 +00:00
Igor Laevsky cec8f47e77 [InstCombine] Don't crash on out of bounds shifts
Differential Revision: https://reviews.llvm.org/D40649

llvm-svn: 319761
2017-12-05 12:18:15 +00:00
Simon Pilgrim aa91155960 [X86][AVX512] Tag VPCMP/VPCMPU instruction scheduler classes
Move hardcoded itinerary out to the instruction declarations. Not sure that IIC_SSE_ALU_F32P is the best schedule for integer comparisons, but I'm not going to change it right now.

llvm-svn: 319760
2017-12-05 12:14:36 +00:00
Simon Pilgrim a2b5862641 [X86][AVX512] Cleanup VPCMP scheduler classes
Move hardcoded itinerary out to the instruction declarations. Not sure that IIC_SSE_ALU_F32P is the best schedule for integer comparisons, but I'm not going to change it right now.

llvm-svn: 319758
2017-12-05 12:02:22 +00:00
Simon Pilgrim 54b8aa2bb2 [X86][AVX512] Tag VFIXUPIMM instructions scheduler classes
llvm-svn: 319757
2017-12-05 11:46:57 +00:00
Jonas Paulsson b5b91cd402 [SystemZ] set 'guessInstructionProperties = 0' and set flags as needed.
This has proven a healthy exercise, as many cases of incorrect instruction
flags were corrected in the process. As part of this, IntrWriteMem was added
to several SystemZ instrinsics.

Furthermore, a bug was exposed in TwoAddress with this change (as incorrect
hasSideEffects flags were removed and instructions could now be sunk), and
the test case for that bugfix (r319646) is included here as
test/CodeGen/SystemZ/twoaddr-sink.ll.

One temporary test regression (one extra copy) which will hopefully go away
in upcoming patches for similar cases:
test/CodeGen/SystemZ/vec-trunc-to-i1.ll

Review: Ulrich Weigand.
https://reviews.llvm.org/D40437

llvm-svn: 319756
2017-12-05 11:24:39 +00:00
Jonas Paulsson 86c40db49d [Regalloc] Generate and store multiple regalloc hints.
MachineRegisterInfo used to allow just one regalloc hint per virtual
register. This patch extends this to a vector of regalloc hints, which is
filled in by common code with sorted copy hints. Such hints will make for
more ID copies that can be removed.

NB! This improvement is currently (and hopefully temporarily) *disabled* by
default, except for SystemZ. The only reason for this is the big impact this
has on tests, which has unfortunately proven unmanageable. It was a long
while since all the tests were updated and just waiting for review (which
didn't happen), but now targets have to enable this themselves
instead. Several targets could get a head-start by downloading the tests
updates from the Phabricator review. Thanks to those who helped, and sorry
you now have to do this step yourselves.

This should be an improvement generally for any target!

The target may still create its own hint, in which case this has highest
priority and is stored first in the vector. If it has target-type, it will
not be recomputed, as per the previous behaviour.

The temporary hook enableMultipleCopyHints() will be removed as soon as all
targets return true.

Review: Quentin Colombet, Ulrich Weigand.
https://reviews.llvm.org/D38128

llvm-svn: 319754
2017-12-05 10:52:24 +00:00
George Rimar 08f5986e4d Fix build bot after r319750 "[Support/TarWriter] - Don't allow TarWriter to add the same file more than once."
Error was:
error: comparison of integers of different signs: 'const unsigned long' and 'const int' [-Werror,-Wsign-compare]

http://lab.llvm.org:8011/builders/ubuntu-gcc7.1-werror/builds/3469/steps/build-unified-tree/logs/stdio
http://lab.llvm.org:8011/builders/clang-with-thin-lto-ubuntu/builds/7118/steps/build-stage2-compiler/logs/stdio

llvm-svn: 319752
2017-12-05 10:35:11 +00:00
Pavel Labath 2da3397cdf Re-commit "[cmake] Enable zlib support on windows"
This recommits r319533 which was broken llvm-config --system-libs
output.  The reason was that I used find_libraries for searching for the
z library.  This returns absolute paths, and when these paths made it
into llvm-config, it made it produce nonsensical flags.  To fix this, I
hand-roll a search for the library in the same way that we search for
the terminfo library a couple of lines below.

This is a bit less flexible than the find_library option, as it does not
allow the user to specify the path to the library at configure time
(which is important on windows, as zlib is unlikely to be found in any
of the standard places cmake searches), but I was able to guide the
build to find it with appropriate values of LIB and INCLUDE environment
variables.

Reviewers: compnerd, rnk, beanz, rafael

Subscribers: llvm-commits, mgorny

Differential Revision: https://reviews.llvm.org/D40779

llvm-svn: 319751
2017-12-05 10:24:15 +00:00
George Rimar f91f0b0af7 [Support/TarWriter] - Don't allow TarWriter to add the same file more than once.
This is for PR35460.

Currently when LLD adds files to TarWriter it may pass the same file
multiple times. For example it happens for clang reproduce file which specifies
archive (.a) files more than once in command line. 
Patch makes TarWriter to ignore files with the same path, so it will
add only the first one to archive.

Differential revision: https://reviews.llvm.org/D40606

llvm-svn: 319750
2017-12-05 10:09:59 +00:00
Guy Blank f3cefdd350 [X86] Fix a bug in handling GRXX subclasses in Domain Reassignment pass
When trying to determine the correct Mask register class corresponding
to a GPR register class, not all register classes were handled.
This caused an assertion to be raised on some scenarios.

Differential Revision:
https://reviews.llvm.org/D40290

llvm-svn: 319745
2017-12-05 09:08:24 +00:00
Craig Topper 98495291a7 [SelectionDAG] Use WidenTargetBoolean in WidenVecRes_MLOAD and WidenVecOp_MSTORE instead of implementing it manually and incorrectly.
The CONCAT_VECTORS operand get its type from getSetCCResultType, but if the mask type and the setcc have different scalar sizes this creates an illegal CONCAT_VECTORS operation. The concat type should be 2x the mask type, and then an extend should be added if needed.

llvm-svn: 319744
2017-12-05 08:15:03 +00:00
Michael Trent 1854eccaf6 Test commit, as per the LLVM Developer Policy.
Commit message, as per the same policy. I added a blank space to the end
of the file. Excelsior.

llvm-svn: 319743
2017-12-05 07:50:00 +00:00
Craig Topper a404ce955a [X86] Use vector widening to support sign extend from i1 when the dest type is not 512-bits and vlx is not enabled.
Previously we used a wider element type and truncated. But its more efficient to keep the element type and drop unused elements.

If BWI isn't supported and we have a i16 or i8 type, we'll extend it to be i32 and still use a truncate.

llvm-svn: 319740
2017-12-05 06:37:21 +00:00
Daniel Sanders 3c1c4c0ee0 Revert r319691: [globalisel][tablegen] Split atomic load/store into separate opcode and enable for AArch64.
Some concerns were raised with the direction. Revert while we discuss it and look into an alternative

llvm-svn: 319739
2017-12-05 05:52:07 +00:00
Kuba Mracek 04013b704c Disable detect_leaks in the ASanified build of LLVM when using Apple LLVM. The released Apple LLVM versions don't support LSan.
llvm-svn: 319738
2017-12-05 05:22:02 +00:00
Craig Topper e1ba2450c2 [X86] Fix a crash if avx512bw and xop are both enabled when the IR contrains a v32i8 bitreverse.
llvm-svn: 319737
2017-12-05 04:47:12 +00:00
Matt Arsenault e42b08d96d AMDGPU: Fix missing subtarget feature initializer
llvm-svn: 319733
2017-12-05 03:15:44 +00:00
Matt Arsenault 9a60c3ea36 AMDGPU: Fix crash when scheduling DBG_VALUE
This calls handleMove with a DBG_VALUE instruction,
which isn't tracked by LiveIntervals. I'm not sure
this is the correct place to fix this. The generic
scheduler seems to have more deliberate region
selection that skips dbg_value.

The test is also really hard to reduce. I haven't been able
to figure out what exactly causes this particular case to
try moving the dbg_value.

llvm-svn: 319732
2017-12-05 03:09:23 +00:00
Craig Topper 276c770e57 [X86] Use vector widening to support zero extend from i1 when the dest type is not 512-bits and vlx is not enabled.
Previously we used a wider element type and truncated. But its more efficient to keep the element type and drop unused elements.

If BWI isn't supported and we have a i16 or i8 type, we'll extend it to be i32 and still use a truncate.

llvm-svn: 319728
2017-12-05 01:45:46 +00:00
Craig Topper 913b42b0e1 [X86] Don't use kunpck for vXi1 concat_vectors if the upper bits are undef.
This can be efficiently selected by a COPY_TO_REGCLASS without the need for an extra instruction.

llvm-svn: 319726
2017-12-05 01:28:06 +00:00
Craig Topper 6302012442 [X86] Use getZeroVector and remove an unnecessary creation of an APInt before calling getConstant. NFCI
The getConstant function can take care of creating the APInt internally.

getZeroVector will take care of using the correct type for the build vector to avoid re-lowering.

The test change here is because execution domain constraints apparently pass through undef inputs of a zeroing xor. So the different ordering of register allocation here caused the dependency to change.

llvm-svn: 319725
2017-12-05 01:28:04 +00:00
Craig Topper adadaae586 [X86] Rearrange some of the code around AVX512 sign/zero extends. NFCI
Move the AVX512 code out of LowerAVXExtend. LowerAVXExtend has two callers but one of them pre-checks for AVX-512 so the code is only live from the other caller. So move the AVX-512 checks up to that caller for symmetry.

Move all of the i1 input type code in Lower_AVX512ZeroExend together.

llvm-svn: 319724
2017-12-05 01:28:00 +00:00
Shoaib Meenai 3f2ce4bbed [cmake] Modernize some conditionals. NFC
The "x${...}" form was a workaround for CMake versions prior to 3.1,
where the if command would interpret arguments as variables even when
quoted [1]. We can drop the workaround now that our minimum CMake
version is 3.4.

[1] https://cmake.org/cmake/help/v3.1/policy/CMP0054.html

Differential Revision: https://reviews.llvm.org/D40744

llvm-svn: 319723
2017-12-05 01:19:48 +00:00