Commit Graph

80683 Commits

Author SHA1 Message Date
Rafael Espindola 4223a1f811 Cleanup the constructor of BitcodeReader. NFC.
Use the same argument names as the members.
Use default member initializes.

Extracted from a patch by Karl Schimpf.

llvm-svn: 239749
2015-06-15 20:08:17 +00:00
Sanjoy Das baeb678a91 Unbreak the build from r239740.
Do not re-use an enum name as a field name.  Some bots don't like this.

llvm-svn: 239746
2015-06-15 19:29:44 +00:00
Colin LeMahieu 56efafc056 [Hexagon] Moving pass declarations out of header and in to implementation files. Removing unused function getSubtargetInfo from HexagonMCCodeEmitter.cpp Removing deletion of copy construction and assignment operator since parent already deletes it.
llvm-svn: 239744
2015-06-15 19:05:35 +00:00
Sanjoy Das 69fad0799e [CodeGen] Add a pass to fold null checks into nearby memory operations.
Summary:
This change adds an "ImplicitNullChecks" target dependent pass.  This
pass folds null checks into memory operation using the FAULTING_LOAD
pseudo-op introduced in previous patches.

Depends on D10197
Depends on D10199
Depends on D10200

Reviewers: reames, rnk, pgavlin, JosephTremoulet, atrick

Reviewed By: atrick

Subscribers: ab, JosephTremoulet, llvm-commits

Differential Revision: http://reviews.llvm.org/D10201

llvm-svn: 239743
2015-06-15 18:44:27 +00:00
Sanjoy Das 6b34a46298 [TargetInstrInfo] Add new hook: AnalyzeBranchPredicate.
Summary:
NFC: no one uses AnalyzeBranchPredicate yet.

Add TargetInstrInfo::AnalyzeBranchPredicate and implement for x86.  A
later change adding support for page-fault based implicit null checks
depends on this.

Reviewers: reames, ab, atrick

Reviewed By: atrick

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10200

llvm-svn: 239742
2015-06-15 18:44:21 +00:00
Sanjoy Das b666ea369c [TargetInstrInfo] Rename getLdStBaseRegImmOfs and implement for x86.
Summary:

TargetInstrInfo::getLdStBaseRegImmOfs to
TargetInstrInfo::getMemOpBaseRegImmOfs and implement for x86.  The
implementation only handles a few easy cases now and will be made more
sophisticated in the future.

This is NFCI: the only user of `getLdStBaseRegImmOfs` (now
`getmemOpBaseRegImmOfs`) is `LoadClusterMotion` and `LoadClusterMotion`
is disabled for x86.

Reviewers: reames, ab, MatzeB, atrick

Reviewed By: MatzeB, atrick

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10199

llvm-svn: 239741
2015-06-15 18:44:14 +00:00
Sanjoy Das c63244daa1 [CodeGen] Introduce a FAULTING_LOAD_OP pseudo-op.
Summary:
This instruction encodes a loading operation that may fault, and a label
to branch to if the load page-faults.  The locations of potentially
faulting loads and their "handler" destinations are recorded in a
FaultMap section, meant to be consumed by LLVM's clients.

Nothing generates FAULTING_LOAD_OP instructions yet, but they will be
used in a future change.

The documentation (FaultMaps.rst) needs improvement and I will update
this diff with a more expanded version shortly.

Depends on D10196

Reviewers: rnk, reames, AndyAyers, ab, atrick, pgavlin

Reviewed By: atrick, pgavlin

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10197

llvm-svn: 239740
2015-06-15 18:44:08 +00:00
Sanjoy Das 2d869b230b [NFC] Extract X86MCInstLower::LowerMachineOperand.
Summary: Refactoring-only change that will be used later.

Reviewers: reames, atrick

Reviewed By: atrick

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10196

llvm-svn: 239739
2015-06-15 18:44:01 +00:00
Yaron Keren 43b4d38944 De-duplicate common expression, NFC.
llvm-svn: 239736
2015-06-15 17:03:35 +00:00
Yaron Keren 3bf3f1f5b9 Rangify several for loops, NFC.
llvm-svn: 239733
2015-06-15 16:20:16 +00:00
Evgeny Astigeevich ff1f4be4c7 On behalf of Alexandros Lamprineas:
LLVM targeting aarch64 doesn't correctly produce aligned accesses for non-aligned
data at -O0/fast-isel (-mno-unaligned-access).
The root cause seems to be in fast-isel not producing unaligned access correctly
for -mno-unaligned-access.

The patch just aborts fast-isel for loads and stores when -mno-unaligned-access is
present. 
The regression test is updated to check this new test case (-mno-unaligned-access 
together with fast-isel).

Differential Revision: http://reviews.llvm.org/D10360

llvm-svn: 239732
2015-06-15 15:48:44 +00:00
Daniel Sanders fa555dc7f8 Revert r239721 - Replace string GNU Triples with llvm::Triple in InitMCObjectFileInfo. NFC.
It appears to cause sparc-little-endian.s to assert on Windows and Darwin.

llvm-svn: 239724
2015-06-15 10:34:38 +00:00
Daniel Sanders d6d12a1192 Replace string GNU Triples with llvm::Triple in InitMCObjectFileInfo. NFC.
Summary:
This affects other tools so the previous C++ API has been retained as a
deprecated function for the moment. Clang has been updated with a trivial
patch (not covered by the pre-commit review) to avoid breaking -Werror builds.
Other in-tree tools will be fixed with similar trivial patches.

This continues the patch series to eliminate StringRef forms of GNU triples
from the internals of LLVM that began in r239036.

Reviewers: rengolin

Reviewed By: rengolin

Subscribers: llvm-commits, rengolin

Differential Revision: http://reviews.llvm.org/D10366

llvm-svn: 239721
2015-06-15 09:19:41 +00:00
Arnaud A. de Grandmaison d8673edc2d [MachineSink] Improve runtime performance. NFC.
This patch fixes a compilation time issue, when MachineSink faces PHIs
with a huge number of operands. This can happen for example in goto table
based interpreters, where some basic blocks can have several of those PHIs,
each one with several hundreds operands. MachineSink was spending a
significant time re-building and re-sorting the list of successors of
the current MachineBasicBlock. The computing and sorting of the current
MachineBasicBlock successors is now cached.

llvm-svn: 239720
2015-06-15 09:09:06 +00:00
Jingyue Wu 12b0c2835e [ValueTracking] do not overwrite analysis results already computed
Summary:
ValueTracking used to overwrite the analysis results computed from
assumes and dominating conditions. This patch fixes this issue.

Test Plan: test/Analysis/ValueTracking/assume.ll

Reviewers: hfinkel, majnemer

Reviewed By: majnemer

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10283

llvm-svn: 239718
2015-06-15 05:46:29 +00:00
Hao Liu 1c2e89a57a [AArch64] Delete two empty files, which should be removed by r239713.
llvm-svn: 239715
2015-06-15 02:56:40 +00:00
Hao Liu d0ca8d7edd [AArch64] Revert r239711 again. We need to discuss how to share code between AArch64 and ARM backend.
llvm-svn: 239713
2015-06-15 01:56:40 +00:00
Hao Liu cb070e3833 [AArch64] Match interleaved memory accesses into ldN/stN instructions.
Re-commit after adding "-aarch64-neon-syntax=generic" to fix the failure on OS X.
This patch was firstly committed in r239514, then reverted in r239544 because of a syntax incompatible failure on OS X.

llvm-svn: 239711
2015-06-15 01:35:49 +00:00
Benjamin Kramer 228680ded8 [InstSimplify] fsub nnan x, x -> 0.0 is valid without ninf
Both inf - inf and (-inf) - (-inf) are NaN, so it's already covered by
nnan.

llvm-svn: 239702
2015-06-14 21:01:20 +00:00
Benjamin Kramer 4f0524614e [InstSimplify] Add self-fdiv identities for -ffinite-math-only.
When NaNs and Infs are ignored we can fold
 X /  X -> 1.0
-X /  X -> -1.0
 X / -X -> -1.0

llvm-svn: 239701
2015-06-14 18:53:58 +00:00
Igor Breger 5e49697138 AVX-512: Implemented DAG lowering for shuff62x2/shufi62x2 instuctions ( Shuffle Packed Values at 128-bit Granularity )
Tests added , vector-shuffle-512-v8.ll test re-generated.

Differential Revision: http://reviews.llvm.org/D10300

llvm-svn: 239697
2015-06-14 13:07:47 +00:00
Michael Kuperstein e3de07a529 Add support for parsing the XOR operator in Intel syntax inline assembly.
Differential Revision: http://reviews.llvm.org/D10385
Patch by marina.yatsina@intel.com

llvm-svn: 239695
2015-06-14 12:59:45 +00:00
Igor Breger abe4a79b75 AVX-512: Implemented cvtsi2ss/d cvtusi2ss/d instructions with round control for KNL.
Added intrinsics for cvtsi2ss/d instructions.
Added tests for intrinsics and encoding.

Differential Revision: http://reviews.llvm.org/D10430

llvm-svn: 239694
2015-06-14 12:44:55 +00:00
NAKAMURA Takumi a6a250a211 AsmPrinter.cpp: Avoid crashes for targeting like "arm-mingw32". CurrentFnSym might not be <MCSymbolELF> here.
llvm-svn: 239692
2015-06-14 00:23:40 +00:00
NAKAMURA Takumi bf6ad02906 Reformat.
llvm-svn: 239691
2015-06-14 00:23:33 +00:00
Benjamin Kramer 258ea0dbdf [Statepoints] Skip a vector copy when uniquing values.
No functionality change intended.

llvm-svn: 239688
2015-06-13 19:50:38 +00:00
Benjamin Kramer bd7b1c89fc [ExecutionEngine] ArrayRefize argument passing.
No functionality change intended.

llvm-svn: 239687
2015-06-13 19:50:29 +00:00
Yaron Keren f3cf9d1f6e C++11 Rangify loops in AssemblyWriter::printModule, NFC.
llvm-svn: 239686
2015-06-13 17:50:47 +00:00
Rafael Espindola 74f293249d Don't use std::errc.
As noted on Errc.h:

// * std::errc is just marked with is_error_condition_enum. This means that
//   common patters like AnErrorCode == errc::no_such_file_or_directory take
//   4 virtual calls instead of two comparisons.

And on some libstdc++ those virtual functions conclude that

------------------------
int main() {
  std::error_code foo = std::make_error_code(std::errc::no_such_file_or_directory);
  return foo == std::errc::no_such_file_or_directory;
}
-------------------------

should exit with 0.

llvm-svn: 239683
2015-06-13 17:23:04 +00:00
Simon Pilgrim d3f6427446 [DAGCombiner] Added BSWAP(BSWAP(x)) -> x combine pattern.
llvm-svn: 239682
2015-06-13 16:25:12 +00:00
Sanjay Patel 5714998484 hoist loop-invariant; NFCI
llvm-svn: 239681
2015-06-13 15:33:15 +00:00
Sanjay Patel 41044f8859 remove function names from comments and clean up; NFC
llvm-svn: 239680
2015-06-13 15:32:45 +00:00
Simon Pilgrim 2c35e7a264 [SelectionDAG] Added assertions + UNDEF handling for BSWAP node creation.
llvm-svn: 239679
2015-06-13 15:23:58 +00:00
Sanjay Patel 85924e5bf3 remove unnecessary casts; NFCI
llvm-svn: 239678
2015-06-13 15:06:33 +00:00
Simon Pilgrim 011381d48b [DAGCombiner] Added BSWAP vector constant folding support.
llvm-svn: 239675
2015-06-13 14:08:15 +00:00
Simon Pilgrim 096cccd01a Stripped trailing whitespace. NFC.
llvm-svn: 239674
2015-06-13 12:57:36 +00:00
Simon Pilgrim a6f44a18f8 Stripped trailing whitespace. NFC.
llvm-svn: 239672
2015-06-13 12:51:39 +00:00
Rafael Espindola 454adf6454 Bring in a BumpPtrStringSaver from lld and simplify the interface.
StringSaver now always saves to a BumpPtrAllocator.

The only reason for having the virtual saveImpl is so lld can have a
thread safe version.

The reason for the distinct BumpPtrStringSaver class is to avoid the
virtual destructor.

llvm-svn: 239669
2015-06-13 12:49:52 +00:00
Tom Stellard 104ad064df AMDGPU: s/R600/AMDGPU/ in the Makefiles
Now the library names in the Makefiles match the library names in
LLVMBuild.txt.

This should hopefully fix the remaining bot failures.

llvm-svn: 239661
2015-06-13 05:11:14 +00:00
Matthias Braun 39a2afc941 Rename TargetSubtargetInfo::enablePostMachineScheduler() to enablePostRAScheduler()
r213101 changed the behaviour of this method to not only affect the
PostMachineScheduler scheduler but also the PostRAScheduler scheduler,
renaming should make this fact clear. Also document that the preferred
way is to specify this in the scheduling model instead of overriding
this method.

Differential Revision: http://reviews.llvm.org/D10427

llvm-svn: 239659
2015-06-13 03:42:16 +00:00
Matthias Braun 88e213159a MachineLICM: Use TargetSchedModel instead of just itineraries
This will use Itinieraries if available, but will also work if just a
MCSchedModel is available.

Differential Revision: http://reviews.llvm.org/D10428

llvm-svn: 239658
2015-06-13 03:42:11 +00:00
Tom Stellard 45bb48ea19 R600 -> AMDGPU rename
llvm-svn: 239657
2015-06-13 03:28:10 +00:00
Matt Wala bfb5368cc7 Revert 239644.
llvm-svn: 239650
2015-06-13 01:08:00 +00:00
Tim Northover 02cfdbb7f1 AArch64: map bare-metal arm64-macho triple to MachO MC layer.
Far better than an assertion about expecting ELF.

llvm-svn: 239647
2015-06-12 23:37:11 +00:00
Eli Bendersky ff715e2d5e Fix returning error message in LLVMLinkModules
On error, the temporary output stream wouldn't be flushed and therefore the
caller would see an empty error message.

Patch by Antoine Pitrou

Differential Revision: http://reviews.llvm.org/D10241 

llvm-svn: 239646
2015-06-12 23:26:42 +00:00
Matt Wala 1f48192d7c [Scalarizer] Fix potential for stale data in Scattered across invocations
Summary:
Scalarizer has two data structures that hold information about changes
to the function, Gathered and Scattered. These are cleared in finish()
at the end of runOnFunction() if finish() detects any changes to the
function. 

However, finish() was checking for changes by only checking if
Gathered was non-empty. The function visitStore() only modifies
Scattered without touching Gathered. As a result, Scattered could have
ended up having stale data if Scalarizer only scalarized store
instructions. Since the data in Scattered is used during the execution
of the pass, this introduced dangling pointer errors. 

The fix is to check whether both Scattered and Gathered are empty
before deciding what to do in finish().

Reviewers: srhines

Reviewed By: srhines

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10422

llvm-svn: 239644
2015-06-12 22:49:11 +00:00
Lang Hames 2e36ddf671 [Orc] Fix a bug in the CompileOnDemand layer where stub decls were not cloned
into partitions. Also, add an option to clone stub definitions (not just decls)
into partitions: these definitions could be inlined in some places to avoid the
overhead of calling via the stub.

Found by inspection - no test case yet, although I plan to add a unit test for
this once the CompileOnDemand layer refactoring settles down.

llvm-svn: 239640
2015-06-12 21:31:15 +00:00
Tom Stellard 12a1910e87 R600/SI: Add assembler support for FLAT instructions
- Add glc, slc, and tfe operands to flat instructions
- Add missing flat instructions
- Fix the encoding of flat_load_dwordx3 and flat_store_dwordx3.

llvm-svn: 239637
2015-06-12 20:47:06 +00:00
Yaron Keren 4c20debe3c Rangify several for loops in ValueEnumerator constructor.
llvm-svn: 239636
2015-06-12 20:18:20 +00:00
Colin LeMahieu 79ec06525e [Hexagon] Making intrinsic tests agnostic to register allocation. Narrowing intrinsic parameters to appropriate width.
llvm-svn: 239634
2015-06-12 19:57:32 +00:00
Douglas Katzman 8f01f1cfc3 Wrap some long lines in LLVMBuild files. NFC
As suggested by jroelofs in a prior review (D9752),
it makes sense to generally prefer multi-line format.

llvm-svn: 239632
2015-06-12 18:44:57 +00:00
Douglas Katzman 1b5767f72b Add 'shave' processor name to Triple
Based on ArchType, Clang's driver can select a non-Clang compiler.
String parsing in Clang would have sufficed if it were only that,
however this change anticipates true llvm support.

Differential Revision: http://reviews.llvm.org/D10413

llvm-svn: 239631
2015-06-12 18:31:38 +00:00
David Blaikie 473b943ea8 Refix a use of explicit pointer types in GEP constant folding
In the glorious future of opaque pointer types, it won't be possible to
retrieve the pointee type of a pointer type which is what's being done
in this GEP loop - but the first iteration is always a pointer type and
the loop doesn't care about that case, except whether or not the index
is a constant.

So pull that special case out before the loop and start at the second
iteration (index 1) instead.

Originally committed in r236670 and reverted with a test case in
r239015. This change keeps the test case working while also avoiding
depending on pointee types.

llvm-svn: 239629
2015-06-12 18:22:03 +00:00
Matt Wala a4afccd8a8 Fix a typo in a comment in MemCpyOpt (test commit)
llvm-svn: 239628
2015-06-12 18:16:51 +00:00
Yaron Keren ef5e7addb3 Rangify two for loops in BitcodeReader.cpp.
llvm-svn: 239627
2015-06-12 18:13:20 +00:00
Pete Cooper b676b01b84 Move OperandList to be allocated prior to User for hung off subclasses.
For hung off uses, we need a Use* to tell use where the operands are.
This was User::OperandList but we want to remove that to save space
of all subclasses which aren't making use of 'hung off uses'.

Hung off uses now allocate their own 'OperandList' Use* in the
User::new which they call.

getOperandList() now uses the hung off uses bit to work out where the
Use* for the OperandList lives.  If a User has hung off uses, then this
bit tells them to go back a single Use* from the User* and use that
value as the OperandList.

If a User has no hung off uses, then we get the first operand by
subtracting (NumOperands * sizeof(Use)) from the User this pointer.

This saves a pointer from User and all subclasses.  Given the average
size of a subclass of User is 112 or 128 bytes, this saves around 7% of space
With malloc tending to align to 16-bytes the real saving is typically more like 3.5%.

On 'opt -O2 verify-uselistorder.lto.bc', peak memory usage prior to this change
is 149MB and after is 143MB so the savings are around 2.5% of peak.

Looking at some passes which allocate many Instructions and Values, parseIR drops
from 54.25MB to 52.21MB while the Inliner calls to Instruction::clone() drops
from 28.20MB to 27.05MB.

Reviewed by Duncan Exon Smith.

llvm-svn: 239623
2015-06-12 17:48:18 +00:00
Pete Cooper c91fda3b10 Added a version of User::new for hung off uses.
There are now 2 versions of User::new.  The first takes a size_t and is the current
implementation for subclasses which need 0 or more Use's allocated for their operands.

The new version takes no extra arguments to say that this subclass needs 'hung off uses'.
The HungOffUses bool is now set in this version of User::new and we can assert in
allocHungOffUses that we are allowed to have hung off uses.
This ensures we call the correct version of User::new for subclasses which need hung off uses.

A future commit will then allocate space for a single Use* which will be used
in place of User::OperandList once that field has been removed.

Reviewed by Duncan Exon Smith.

llvm-svn: 239622
2015-06-12 17:48:14 +00:00
Pete Cooper b4eede2c07 Rename NumOperands to make it clear its managed by the User. NFC.
This is to try make it very clear that subclasses shouldn't be changing
the value directly.  Now that OperandList for normal instructions is computed
using the NumOperands, its critical that the NumOperands is accurate or we
could compute the wrong offset to the first operand.

I looked over all places which update NumOperands and they are all safe.
Hung off use User's don't use NumOperands to compute the OperandList so they
are safe to continue to manipulate it.  The only other User which changed it
was GlobalVariable which has an optional init list but always allocated space
for a single Use.  It was correctly setting NumOperands to 1 before setting an
initializer, and setting it to 0 after clearing the init list, so the order was safe.

Added some comments to that code to make sure that this isn't changed in future
without being aware of this constraint.

Reviewed by Duncan Exon Smith.

llvm-svn: 239621
2015-06-12 17:48:10 +00:00
Pete Cooper 74510a409d Replace all accesses to User::OperandList with getter and setter methods. NFC.
We don't want anyone to access OperandList directly as its going to be removed
and computed instead.  This uses getter's and setter's instead in which we
can later change the underlying implementation of OperandList.

Reviewed by Duncan Exon Smith.

llvm-svn: 239620
2015-06-12 17:48:05 +00:00
Pete Cooper 3664253c52 Don't create instructions from ConstantExpr's in CFLAliasAnalysis.
The CFLAA code currently calls ConstantExpr::getAsInstruction which creates an instruction from a constant expr.

We then pass that instruction to the InstVisitor to analyze it.

Its not necessary to create these instructions as we can just cast from Constant to Operator in the visitor.  This is how other InstVisitor’s such as SelectionDAGBuilder handle ConstantExpr.

llvm-svn: 239616
2015-06-12 16:13:54 +00:00
Rafael Espindola 0b9319edb0 Remove a hack that tries to align '*'.
The alignment is not required, so we can just remove it for now.

The old code is a hack as it depends on the buffer management to find
the current column.

If the alignment is really desirable, the proper way to do it is
to pass in a formatted_raw_stream that knows the current column.

llvm-svn: 239603
2015-06-12 12:42:13 +00:00
Alexander Potapenko f90556efb8 [ASan] format AddressSanitizer.cpp with `clang-format -style=Google`, NFC
llvm-svn: 239601
2015-06-12 11:27:06 +00:00
John Brawn d9e39d53b6 [ARM] Disabling vfp4 should disable fp16
ARMTargetParser::getFPUFeatures should disable fp16 whenever it
disables vfp4, as otherwise something like -mcpu=cortex-a7 -mfpu=none
leaves us with fp16 enabled (though the only effect that will have is
a wrong build attribute).

Differential Revision: http://reviews.llvm.org/D10397

llvm-svn: 239599
2015-06-12 09:38:51 +00:00
Yaron Keren 26ceb0845b Rangify for loops, NFC.
llvm-svn: 239596
2015-06-12 05:15:27 +00:00
Peter Collingbourne 005354b1f4 LowerBitSets: Give names to aliases of unnamed bitset element objects.
It is valid for globals to be unnamed, but aliases must have a name. To avoid
creating invalid IR, we need to assign names to any aliases we create that
point to unnamed objects that have been moved into combined globals.

llvm-svn: 239590
2015-06-12 03:25:05 +00:00
Teresa Johnson 43a65d9529 Revert commit r239480 as it causes https://code.google.com/p/chromium/issues/detail?id=499508#c3.
llvm-svn: 239589
2015-06-12 03:12:00 +00:00
Alexey Samsonov 201733b7f0 [SanitizerCoverage] Use llvm::getDISubprogram() to get location of the entry basic block.
DebugLoc::getFnDebugLoc() should soon be removed. Also,
getDISubprogram() might become more effective soon and wouldn't need to
scan debug locations at all, if function-level metadata would be emitted
by Clang.

llvm-svn: 239586
2015-06-12 01:48:47 +00:00
Alexey Samsonov 9947e48cd1 [GVN] Use a simpler form of IRBuilder constructor.
Summary:
A side effect of this change is that it IRBuilder now automatically
created debug info locations for new instructions, which is the
same as debug location of insertion point. This is fine for the
functions in questions (GetStoreValueForLoad and
GetMemInstValueForLoad), as they are used in two situations:
  * GVN::processLoad, which tries to eliminate a load. In this case
    new instructions would have the same debug location as the load they
    eventually replace;
  * MaterializeAdjustedValue, which adds new instructions to the end
    of the basic blocks, which could later be used to replace the load
    definition. In this case we don't yet know the way the load would
    be eventually replaced (either by assembling the precomputed values
    via PHI, or by using them directly), so just using the basic block
    strategy seems to be reasonable. There is also a special case
    in the code that *would* adjust the location of the last
    instruction replacing the load definition to the location of the
    load.

Test Plan: regression test suite

Reviewers: echristo, dberlin, dblaikie

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10405

llvm-svn: 239585
2015-06-12 01:39:48 +00:00
Alexey Samsonov ff449802c2 [GVN] Use IRBuilder more actively instead of creating instructions manually.
llvm-svn: 239584
2015-06-12 01:39:45 +00:00
Reid Kleckner 81d1cc00b7 [WinEH] Put finally pointers in the handler scope table field
We were putting them in the filter field, which is correct for 64-bit
but wrong for 32-bit.

Also switch the order of scope table entry emission so outermost entries
are emitted first, and fix an obvious state assignment bug.

llvm-svn: 239574
2015-06-11 23:37:18 +00:00
Juergen Ributzka 03cb0d8b46 [Stackmaps][X86] Remove EFLAGS and IP registers from the live-out mask.
Remove the EFLAGS from the stackmap live-out mask. The EFLAGS register is not
supposed to be part of that set, because the X86 calling conventions mark the
register as NOT preserved.

Also remove the IP registers, since spilling and restoring those doesn't really
make any sense.

Related to rdar://problem/21019635.

llvm-svn: 239568
2015-06-11 22:40:04 +00:00
Reid Kleckner a9d6253572 [WinEH] Create an llvm.x86.seh.exceptioninfo intrinsic
This intrinsic is like framerecover plus a load. It recovers the EH
registration stack allocation from the parent frame and loads the
exception information field out of it, giving back a pointer to an
EXCEPTION_POINTERS struct. It's designed for clang to use in SEH filter
expressions instead of accessing the EXCEPTION_POINTERS parameter that
is available on x64.

This required a minor change to MC to allow defining a label variable to
another absolute framerecover label variable.

llvm-svn: 239567
2015-06-11 22:32:23 +00:00
Reid Kleckner 6bb26dafa4 [Support] Fix a race initializing a static local in MSVC
static local initialization isn't thread safe with MSVC and a race was
reported in PR23817. We can't use std::atomic because it's not trivially
constructible, so instead do some lame volatile global integer
manipulation.

llvm-svn: 239566
2015-06-11 22:22:45 +00:00
Michael Zolotukhin c4e4f33e29 Update stale comment before analyzeLoopUnrollCost. NFC.
llvm-svn: 239565
2015-06-11 22:17:39 +00:00
Peter Collingbourne 82e657b509 Object: Prepend __imp_ when mangling a dllimport symbol in IRObjectFile.
We cannot prepend __imp_ in the IR mangler because a function reference may
be emitted unmangled in a constant initializer. The linker is expected to
resolve such references to thunks. This is covered by the new test case.

Strictly speaking we ought to emit two undefined symbols, one with __imp_ and
one without, as we cannot know which symbol the final object file will refer
to. However, this would require rather intrusive changes to IRObjectFile,
and lld works fine without it for now.

This reimplements r239437, which was reverted in r239502.

Differential Revision: http://reviews.llvm.org/D10400

llvm-svn: 239560
2015-06-11 21:42:18 +00:00
Peter Collingbourne 485ad4860e LTO: expose LTO_SYMBOL_COMDAT flag, which indicates that the definition is part of a comdat group.
Reviewers: rafael

Subscribers: llvm-commits, ruiu

Differential Revision: http://reviews.llvm.org/D10330

llvm-svn: 239559
2015-06-11 21:41:27 +00:00
Daniel Sanders 3e5de88dac Replace string GNU Triples with llvm::Triple in TargetMachine. NFC.
Summary:
For the moment, TargetMachine::getTargetTriple() still returns a StringRef.

This continues the patch series to eliminate StringRef forms of GNU triples
from the internals of LLVM that began in r239036.

Reviewers: rengolin

Reviewed By: rengolin

Subscribers: ted, llvm-commits, rengolin, jholewinski

Differential Revision: http://reviews.llvm.org/D10362

llvm-svn: 239554
2015-06-11 19:41:26 +00:00
Ahmed Bougacha c88bf54366 [CodeGen] ArrayRef'ize cond/pred in various TII APIs. NFC.
llvm-svn: 239553
2015-06-11 19:30:37 +00:00
Rafael Espindola 7c6e6e49cc Generalize emitAbsoluteSymbolDiff.
This makes emitAbsoluteSymbolDiff always succeed and moves logic from the asm
printer to it.

The object one now also works on ELF. If two symbols are in the same fragment,
we will never move them apart.

llvm-svn: 239552
2015-06-11 18:58:08 +00:00
Alexey Samsonov 770f65ca6a Set proper debug location for branch added in BasicBlock::splitBasicBlock().
This improves debug locations in passes that do a lot of basic block
transformations. Important case is LoopUnroll pass, the test for correct
debug locations accompanies this change.

Test Plan: regression test suite

Reviewers: dblaikie, sanjoy

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10367

llvm-svn: 239551
2015-06-11 18:25:54 +00:00
Alexey Samsonov ea20199b48 [LoopUnroll] Use IRBuilder to create branch instructions.
Use IRBuilder::Create(Cond)?Br instead of constructing instructions
manually with BranchInst::Create(). It's consistent with other
uses of IRBuilder in this pass, and has an additional important
benefit:

Using IRBuilder will ensure that new branch instruction will get
the same debug location as original terminator instruction it will
eventually replace.

For now I'm not adding a testcase, as currently original terminator
instruction also lack debug location due to missing debug location
propagation in BasicBlock::splitBasicBlock. That is, the testcase
will accompany the fix for the latter I'm going to mail soon.

llvm-svn: 239550
2015-06-11 18:25:44 +00:00
Benjamin Kramer 2d221406fa Replace an instance of custom atomics with standard ones.
Eventually I want to get rid of them entirely, but Statistic.h is still blocked
on MSVC bugs. No functionality change.

llvm-svn: 239545
2015-06-11 17:30:34 +00:00
Rafael Espindola 65d37e64a9 This reverts commit r239529 and r239514.
Revert "[AArch64] Match interleaved memory accesses into ldN/stN instructions."
Revert "Fixing MSVC 2013 build error."

The  test/CodeGen/AArch64/aarch64-interleaved-accesses.ll test was failing on OS X.

llvm-svn: 239544
2015-06-11 17:30:33 +00:00
Reid Kleckner 2691c59e97 Revert "Fix merges of non-zero vector stores"
This reverts commit r239539.

It was causing SDAG assertions while building freetype.

llvm-svn: 239543
2015-06-11 17:25:24 +00:00
Matt Arsenault 91f90e694f SLSR: Pass address space to isLegalAddressingMode
This only updates one of the uses. The other is used in cases
that may never touch memory, so I'm not sure why this is even
calling it. Perhaps there should be a new, similar hook for such
cases or pass -1 for unknown address space.

llvm-svn: 239540
2015-06-11 16:13:39 +00:00
Matt Arsenault e23a063dc3 Fix merges of non-zero vector stores
Now actually stores the non-zero constant instead of 0.
I somehow forgot to include this part of r238108.

The test change was just an independent instruction order swap,
so just add another check line to satisfy CHECK-NEXT.

llvm-svn: 239539
2015-06-11 16:03:52 +00:00
Daniel Sanders ed64d62c70 Replace string GNU Triples with llvm::Triple in computeDataLayout(). NFC.
Summary:
This continues the patch series to eliminate StringRef forms of GNU triples
from the internals of LLVM that began in r239036.

Reviewers: rengolin

Reviewed By: rengolin

Subscribers: llvm-commits, jfb, rengolin

Differential Revision: http://reviews.llvm.org/D10361

llvm-svn: 239538
2015-06-11 15:34:59 +00:00
Tom Stellard 076ac95e79 R600/SI: Define latency for flat instructions
llvm-svn: 239535
2015-06-11 14:51:50 +00:00
Tom Stellard 731c927839 R600/SI: Move flat instruction defs to CIInstructions.td
llvm-svn: 239534
2015-06-11 14:51:49 +00:00
Sanjay Patel 8b2150efdb remove function names from comments; NFC
llvm-svn: 239532
2015-06-11 14:26:49 +00:00
Aaron Ballman b6b58b3152 Fixing MSVC 2013 build error.
llvm-svn: 239529
2015-06-11 13:06:02 +00:00
Toma Tabacu e1e460dbc5 Recommit "[mips] [IAS] Add support for BNE and BEQ with an immediate operand." (r239396).
Apparently, Arcanist didn't include some of my local changes in my previous
commit attempt.

llvm-svn: 239523
2015-06-11 10:36:10 +00:00
Zoran Jovanovic cdfcbe41f2 [mips][microMIPS] Implement ERET and ERETNC instructions
http://reviews.llvm.org/D10091

llvm-svn: 239522
2015-06-11 10:22:46 +00:00
Zoran Jovanovic 6b0dcd7b8c [mips] Change existing uimm10 operand to restrict the accepted immediates
http://reviews.llvm.org/D10312

llvm-svn: 239520
2015-06-11 09:51:58 +00:00
Hao Liu 405f1d1651 [LoopVectorize] Revert the enabling of interleaved memory access in Loop Vectorizor, which was wrongly committed in r239514.
llvm-svn: 239515
2015-06-11 09:18:07 +00:00
Hao Liu 4566d18e89 [AArch64] Match interleaved memory accesses into ldN/stN instructions.
Add a pass AArch64InterleavedAccess to identify and match interleaved memory accesses. This pass transforms an interleaved load/store into ldN/stN intrinsic. As Loop Vectorizor disables optimization on interleaved accesses by default, this optimization is also disabled by default. To enable it by "-aarch64-interleaved-access-opt=true"

E.g. Transform an interleaved load (Factor = 2):
       %wide.vec = load <8 x i32>, <8 x i32>* %ptr
       %v0 = shuffle %wide.vec, undef, <0, 2, 4, 6>  ; Extract even elements
       %v1 = shuffle %wide.vec, undef, <1, 3, 5, 7>  ; Extract odd elements
     Into:
       %ld2 = { <4 x i32>, <4 x i32> } call aarch64.neon.ld2(%ptr)
       %v0 = extractelement { <4 x i32>, <4 x i32> } %ld2, i32 0
       %v1 = extractelement { <4 x i32>, <4 x i32> } %ld2, i32 1

E.g. Transform an interleaved store (Factor = 2):
       %i.vec = shuffle %v0, %v1, <0, 4, 1, 5, 2, 6, 3, 7>  ; Interleaved vec
       store <8 x i32> %i.vec, <8 x i32>* %ptr
     Into:
       %v0 = shuffle %i.vec, undef, <0, 1, 2, 3>
       %v1 = shuffle %i.vec, undef, <4, 5, 6, 7>
       call void aarch64.neon.st2(%v0, %v1, %ptr)

llvm-svn: 239514
2015-06-11 09:05:02 +00:00
Arnaud A. de Grandmaison af37ad19a9 [LiveVariables] Improve isLiveOut runtime performances. NFC.
On large goto table based interpreters, where phi nodes can have (very) large
fan-ins, isLiveOut exhibited poor performances: about 40% of the full
codegen time was spent in PHIElim, sorting MachineBasicBlock addresses.

This patch improve the performances for such cases, and does not show
compile time regressions on the LNT, at bootstrap (llvm+clang+lldb) or
any other benchmarks we have in-house.

llvm-svn: 239510
2015-06-11 07:50:21 +00:00
Simon Pilgrim 5965680d53 [X86][SSE] Vectorized i8 and i16 shift operators
This patch ensures that SHL/SRL/SRA shifts for i8 and i16 vectors avoid scalarization. It builds on the existing i8 SHL vectorized implementation of moving the shift bits up to the sign bit position and separating the 4, 2 & 1 bit shifts with several improvements:

1 - SSE41 targets can use (v)pblendvb directly with the sign bit instead of performing a comparison to feed into a VSELECT node.
2 - pre-SSE41 targets were masking + comparing with an 0x80 constant - we avoid this by using the fact that a set sign bit means a negative integer which can be compared against zero to then feed into VSELECT, avoiding the need for a constant mask (zero generation is much cheaper).
3 - SRA i8 needs to be unpacked to the upper byte of a i16 so that the i16 psraw instruction can be correctly used for sign extension - we have to do more work than for SHL/SRL but perf tests indicate that this is still beneficial.

The i16 implementation is similar but simpler than for i8 - we have to do 8, 4, 2 & 1 bit shifts but less shift masking is involved. SSE41 use of (v)pblendvb requires that the i16 shift amount is splatted to both bytes however.

Tested on SSE2, SSE41 and AVX machines.

Differential Revision: http://reviews.llvm.org/D9474

llvm-svn: 239509
2015-06-11 07:46:37 +00:00
Arnaud A. de Grandmaison 2e8ffa3b44 [PHIElim] Use ranges and const-ify, NFC.
llvm-svn: 239508
2015-06-11 07:45:05 +00:00
Nemanja Ivanovic ea1db8a697 LLVM support for vector quad bit permute and gather instructions through builtins
This patch corresponds to review:
http://reviews.llvm.org/D10096

This is the back end portion of the patch related to D10095.
The patch adds the instructions and back end intrinsics for:
vbpermq
vgbbd

llvm-svn: 239505
2015-06-11 06:21:25 +00:00
Reid Kleckner c35e7f52ba Revert "Move dllimport name mangling to IR mangler."
This reverts commit r239437.

This broke clang-cl self-hosts. We'd end up calling the __imp_ symbol
directly instead of using it to do an indirect function call.

llvm-svn: 239502
2015-06-11 01:31:48 +00:00
Pete Cooper 7cbe58d3c5 Remove MachineModuleInfo::UsedFunctions as it has no users.
It hasn't been used since r130964.

This also removes MachineModuleInfo::isUsedFunction and
MachineModuleInfo::AnalyzeModule, both of which were only
there to support UsedFunctions.

llvm-svn: 239501
2015-06-11 01:04:56 +00:00
Sanjay Patel 1275a3c913 change assert that will never fire to llvm_unreachable
llvm-svn: 239497
2015-06-10 23:27:33 +00:00
Pete Cooper 3fc3040860 Stop returning a Use* from allocHungOffUses.
This always just set the User::OperandList which is now set
in that method instead of being returned.

Reviewed by Duncan Exon Smith.

llvm-svn: 239493
2015-06-10 22:38:46 +00:00
Pete Cooper 93f9ff5781 Add User::growHungoffUses and use it to grow the hung off uses. NFC.
PhiNode, SwitchInst, LandingPad and IndirectBr all had virtually identical
logic for growing the hung off uses.
Move it to User so that they can all call a single shared implementation.

Their destructors were all empty after this change and were deleted.  They all
have virtual clone_impl methods which can be used as vtable anchors.

Reviewed by Duncan Exon Smith.

llvm-svn: 239492
2015-06-10 22:38:41 +00:00
Pete Cooper 178dcc2938 Delete User::dropHungOffUses and move it in to ~User which is the only caller. NFC.
Now that the subclasses which care about hung off uses let ~User clean it up,
there's no need for a separate method.  Just inline it to ~User and delete it.

Reviewed by Duncan Exon Smith.

llvm-svn: 239491
2015-06-10 22:38:38 +00:00
Pete Cooper c6c0439d2a Make User track whether a class has 'hung off uses' and delete them in its destructor.
Currently all of the logic for deleting hung off uses, which PHI/switch/etc use,
is in their classes.

This adds a bit to Value which tracks whether that user had hung off uses,
then User can be responsible for clearing them instead of the sub classes.

Note, the bit used here was taken from NumOperands which was 30-bits.
Given the reduction to 29 bits, and the average User being just over 100 bytes,
a single User with 29-bits of num operands would need 50GB of RAM for itself
so its reasonable to assume that 29-bits is enough for now.

This is a step towards hiding all the hung off uses logic in the User.

Reviewed by Duncan Exon Smith.

llvm-svn: 239490
2015-06-10 22:38:34 +00:00
Pete Cooper 87b925b064 Move the special Phi logic for hung off uses in to User::allocHungOffUses. NFC.
PhiNode's need to allocate space for an array of Use[N] and then BasicBlock*[N].

They had their own allocHungOffUses to handle all of this.  This moves the logic
in to User::allocHungOffUses and PhiNode passes in a bool to say to allocate
the BB* space too.

Reviewed by Duncan Exon Smith.

llvm-svn: 239489
2015-06-10 22:38:30 +00:00
Peter Collingbourne 115fe37621 ArgumentPromotion: Drop sret attribute on functions that are only called directly.
If the first argument to a function is a 'this' argument and the second
has the sret attribute, the ArgumentPromotion pass may promote the 'this'
argument to more than one argument, violating the IR constraint that 'sret'
may only be applied to the first or second argument.

Although this IR constraint is arguably unnecessary, it highlighted the fact
that ArgPromotion does not need to preserve this attribute. Dropping the
attribute reduces register pressure in the backend by avoiding the register
copy required by sret. Because sret implies noalias, we also replace the
former with the latter.

Differential Revision: http://reviews.llvm.org/D10353

llvm-svn: 239488
2015-06-10 21:14:34 +00:00
Sanjay Patel 08829bac81 [x86] Add a reassociation optimization to increase ILP via the MachineCombiner pass
This is a reimplementation of D9780 at the machine instruction level rather than the DAG.

Use the MachineCombiner pass to reassociate scalar single-precision AVX additions (just a
starting point; see the TODO comments) to increase ILP when it's safe to do so.

The code is closely based on the existing MachineCombiner optimization that is implemented
for AArch64.

This patch should not cause the kind of spilling tragedy that led to the reversion of r236031.

Differential Revision: http://reviews.llvm.org/D10321

llvm-svn: 239486
2015-06-10 20:32:21 +00:00
Sanjay Patel ccb8d5cc57 punctuation policing; NFC
llvm-svn: 239484
2015-06-10 19:52:58 +00:00
Reid Kleckner c87a6faba1 [WinEH] _except_handlerN uses 0 instead of 1 to indicate catch-all
Our usage of 1 was a holdover from __C_specific_handler.

llvm-svn: 239482
2015-06-10 18:14:07 +00:00
Teresa Johnson 232fa9af3b Add new EliminateAvailableExternally module pass, which is performed in
O2 compiles just before GlobalDCE, unless we are preparing for LTO.

This pass eliminates available externally globals (turning them into
declarations), regardless of whether they are dead/unreferenced, since
we are guaranteed to have a copy available elsewhere at link time.
This enables additional opportunities for GlobalDCE.

If we are preparing for LTO (e.g. a -flto -c compile), the pass is not
included as we want to preserve available externally functions for possible
link time inlining. The FE indicates whether we are doing an -flto compile
via the new PrepareForLTO flag on the PassManagerBuilder.

llvm-svn: 239480
2015-06-10 17:49:28 +00:00
Alexey Samsonov 89645dfa4d [GVN] Set proper debug locations for some instructions created by GVN.
Determining proper debug locations for instructions created in
PHITransAddr is tricky. We use a simple approach here and simply copy
debug locations from instructions computing load address to
"corresponding" instructions re-creating the address computation
in predecessor basic blocks.

This may not always be correct, given all the rearrangement and
simplification going on, and debug locations may jump around a lot,
as the basic blocks we copy locations between may be very far from
each other.

Still, this would work good in most simple cases (e.g. when chain
of address computing instruction is short, or our mapping turns out
to be 1-to-1), and we desire to have *some* reasonable debug locations
associated with newly inserted instructions.

See http://reviews.llvm.org/D10351 review thread for more details.

Test Plan: regression test suite

Reviewers: spatel, dblaikie

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10351

llvm-svn: 239479
2015-06-10 17:37:38 +00:00
Sanjay Patel a32fadd14a fix typo in comment; NFC
llvm-svn: 239478
2015-06-10 17:08:12 +00:00
Colin LeMahieu 1e9d1d768c [Hexagon] Adding decoders for signed operands and ensuring all signed operand types disassemble correctly.
llvm-svn: 239477
2015-06-10 16:52:32 +00:00
Benjamin Kramer feacdd39d5 [Hexagon] Make global arrays 'static const'. NFC.
llvm-svn: 239475
2015-06-10 14:43:59 +00:00
Igor Laevsky 346ff628f7 [StatepointLowering] Reuse stack slots across basic blocks
During statepoint lowering we can sometimes avoid spilling of the value if we know that it was already spilled for previous statepoint.
We were doing this by checking if incoming statepoint value was lowered into load from stack slot. This was working only in boundaries of one basic block.

But instead of looking at the lowered node we can look directly at the llvm-ir value and if it was gc.relocate (or some simple modification of it) look up stack slot for it's derived pointer and reuse stack slot from it. This allows us to look across basic block boundaries.

Differential Revision: http://reviews.llvm.org/D10251

llvm-svn: 239472
2015-06-10 12:31:53 +00:00
Daniel Sanders a73f1fdb19 Replace string GNU Triples with llvm::Triple in MCSubtargetInfo and create*MCSubtargetInfo(). NFC.
Summary:
This continues the patch series to eliminate StringRef forms of GNU triples
from the internals of LLVM that began in r239036.

Reviewers: rafael

Reviewed By: rafael

Subscribers: rafael, ted, jfb, llvm-commits, rengolin, jholewinski

Differential Revision: http://reviews.llvm.org/D10311

llvm-svn: 239467
2015-06-10 12:11:26 +00:00
Daniel Sanders 9aa7e38bf8 Replace string GNU Triples with llvm::Triple in create*MCRelocationInfo(). NFC.
Summary:
This continues the patch series to eliminate StringRef forms of GNU triples
from the internals of LLVM that began in r239036.

Reviewers: rafael

Reviewed By: rafael

Subscribers: rafael, llvm-commits, rengolin

Differential Revision: http://reviews.llvm.org/D10307

llvm-svn: 239465
2015-06-10 10:54:40 +00:00
Daniel Sanders 418caf5002 Replace string GNU Triples with llvm::Triple in MCAsmBackend subclasses and create*AsmBackend(). NFC.
Summary:
This continues the patch series to eliminate StringRef forms of GNU triples
from the internals of LLVM that began in r239036.

Reviewers: echristo, rafael

Reviewed By: rafael

Subscribers: rafael, llvm-commits, rengolin

Differential Revision: http://reviews.llvm.org/D10243

llvm-svn: 239464
2015-06-10 10:35:34 +00:00
Elena Demikhovsky 00c9ad5ec2 AVX-512: Fixed a bug in comparison of i1 vectors.
cmp eq should give kxnor instruction
cmp neq should give kxor 

https://llvm.org/bugs/show_bug.cgi?id=23631

llvm-svn: 239460
2015-06-10 06:49:28 +00:00
Alexei Starovoitov a38e198222 fix crash
fix segfault by checking for UnknownArch, since
getArchTypePrefix() will return nullptr for UnknownArch.

This fixes regression caused by r238424.

llvm-svn: 239456
2015-06-10 03:06:06 +00:00
Craig Topper 8e29d71623 Remove unnecessary conversion from StringRef to std::string and back to StringRef. NFC.
llvm-svn: 239455
2015-06-10 02:07:37 +00:00
Reid Kleckner 673de15af9 [WinEH] Call llvm.stackrestore in __except blocks
We have to do this manually, the runtime only sets up ebp. Fixes a crash
when returning after catching an exception.

llvm-svn: 239451
2015-06-10 01:34:54 +00:00
Reid Kleckner ca6ef66e4c Remove safeseh debug print and remove extra braces
llvm-svn: 239449
2015-06-10 01:13:44 +00:00
Reid Kleckner 2bc93ca846 [WinEH] Emit .safeseh directives for all 32-bit exception handlers
Use a "safeseh" string attribute to do this. You would think we chould
just accumulate the set of personalities like we do on dwarf, but this
fails to account for the LSDA-loading thunks we use for
__CxxFrameHandler3. Each of those needs to make it into .sxdata as well.
The string attribute seemed like the most straightforward approach.

llvm-svn: 239448
2015-06-10 01:02:30 +00:00
Reid Kleckner 7912d9b899 Fix -Wsign-compare warning in WinException.cpp
llvm-svn: 239445
2015-06-10 00:04:53 +00:00
Pete Cooper 17d6359488 Fix warning of comparing different enums. NFC
llvm-svn: 239443
2015-06-09 23:33:35 +00:00
Pete Cooper 4750efad9a Revert "Move MCSymbol Value in to the union of Offset and CommonSize."
This reverts commit 2e449ec5bcdf67b52b315b16c2128aaf25d5b73c.

This was svn r239440.  Its currently failing an ARM test so reverting while I work out
what to do next.

llvm-svn: 239441
2015-06-09 22:35:55 +00:00
Pete Cooper 6109b51ef1 Move MCSymbol Value in to the union of Offset and CommonSize.
It wasn't possible to have a variable Symbol with offset or 'isCommon' so
this just enables better packing of the MCSymbol class.

Reviewed by Rafael Espindola.

llvm-svn: 239440
2015-06-09 22:21:37 +00:00
Tobias Edler von Koch d5289d9724 [RegisterScavenger] Fix handling of predicated instructions
Summary:
The RegisterScavenger explicitly ignores <kill> flags on operands of
predicated instructions and therefore assumes that such registers remain
live. When it then scavenges such a register, it inserts a spill of this
(killed) register. This is invalid code and gets flagged up by the 
verifier.

Nowadays kill flags are set correctly on predicated instructions. This
patch makes the Scavenger respect them.

The bug has so far only been triggered by an internal pass, so I don't
have a test case unfortunately.

Fixes PR23119.

Reviewers: hfinkel, tobiasvk_caf

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9039

llvm-svn: 239439
2015-06-09 22:10:58 +00:00
Alexey Samsonov b7f02d371f [BasicBlockUtils] Set debug locations for instructions created in SplitBlockPredecessors.
Test Plan: regression test suite

Reviewers: eugenis, dblaikie

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10343

llvm-svn: 239438
2015-06-09 22:10:29 +00:00
Peter Collingbourne 9fe51fdf18 Move dllimport name mangling to IR mangler.
This ensures that LTO clients see the correct external symbol name.

Differential Revision: http://reviews.llvm.org/D10318

llvm-svn: 239437
2015-06-09 22:09:53 +00:00
Jingyue Wu 75589ffcc2 [NVPTX] fix a crash bug in NVPTXFavorNonGenericAddrSpaces
Summary:
We used to assume V->RAUW only modifies the operand list of V's user.
However, if V and V's user are Constants, RAUW may replace and invalidate V's
user entirely.

This patch fixes the above issue by letting the caller replace the
operand instead of calling RAUW on Constants.

Test Plan: @nested_const_expr and @rauw in access-non-generic.ll

Reviewers: broune, jholewinski

Reviewed By: broune, jholewinski

Subscribers: jholewinski, llvm-commits

Differential Revision: http://reviews.llvm.org/D10345

llvm-svn: 239435
2015-06-09 21:50:32 +00:00
Peter Collingbourne bc05163f15 LibDriver, llvm-lib: introduce.
llvm-lib is intended to be a lib.exe compatible utility that also
understands bitcode. The implementation lives in a library so that
lld can use it to implement /lib.

Differential Revision: http://reviews.llvm.org/D10297

llvm-svn: 239434
2015-06-09 21:50:22 +00:00
Reid Kleckner f12c030f48 [WinEH] Add 32-bit SEH state table emission prototype
This gets all the handler info through to the asm printer and we can
look at the .xdata tables now. I've convinced one small catch-all test
case to work, but other than that, it would be a stretch to say this is
functional.

The state numbering algorithm avoids doing any scope reconstruction as
we do for C++ to simplify the implementation.

llvm-svn: 239433
2015-06-09 21:42:19 +00:00
Chad Rosier cf90acc104 [AArch64] Remove an overly conservative check when generating store pairs.
Store instructions do not modify register values and therefore it's safe
to form a store pair even if the source register has been read in between
the two store instructions.

Previously, the read of w1 (see below) prevented the formation of a stp.

        str      w0, [x2]
        ldr     w8, [x2, #8]
        add      w0, w8, w1
        str     w1, [x2, #4]
        ret

We now generate the following code.

        stp      w0, w1, [x2]
        ldr     w8, [x2, #8]
        add      w0, w8, w1
        ret

All correctness tests with -Ofast on A57 with Spec200x and EEMBC pass.
Performance results for SPEC2K were within noise.

llvm-svn: 239432
2015-06-09 20:59:41 +00:00
Pete Cooper 8ae395de66 Use AlignOf traits to enable static_assert.
This is better than runtime asserts.  Thanks to David Blaikie for the help here.

llvm-svn: 239431
2015-06-09 20:58:03 +00:00
Benjamin Kramer c1c3c84bb4 Replace loop with std::equal. NFC intended.
llvm-svn: 239430
2015-06-09 20:41:21 +00:00
Pete Cooper 6d17edc534 Reduce duplication in MCSymbol Name handling. NFC>
Based on feedback to r239428 by David Blaikie, use const_cast to reduce
duplication of the const and non-const versions of getNameEntryPtr.

Also have that method return the pointer to the name directly instead
of users having to then get the name from the union.

Finally, add a FIXME that we should use a static_assert once available in
the new operator.

llvm-svn: 239429
2015-06-09 20:41:08 +00:00
Pete Cooper a9ecddbbe5 Make MCSymbol::Name be a union of uint64_t and a pointer.
This should hopefully fix the 32-bit bots which were allocating space for a pointer
but needed to be aligned to 64-bits.

Now we allocate enough space for a uint64_t and a pointer and cast to the appropriate storage

llvm-svn: 239428
2015-06-09 19:56:05 +00:00
Akira Hatanaka d9699bc7bd Remove DisableTailCalls from TargetOptions and the code in resetTargetOptions
that was resetting it.

Remove the uses of DisableTailCalls in subclasses of TargetLowering and use
the value of function attribute "disable-tail-calls" instead. Also,
unconditionally add pass TailCallElim to the pipeline and check the function
attribute at the start of runOnFunction to disable the pass on a per-function
basis. 
 
This is part of the work to remove TargetMachine::resetTargetOptions, and since
DisableTailCalls was the last non-fast-math option that was being reset in that
function, we should be able to remove the function entirely after the work to
propagate IR-level fast-math flags to DAG nodes is completed.

Out-of-tree users should remove the uses of DisableTailCalls and make changes
to attach attribute "disable-tail-calls"="true" or "false" to the functions in
the IR.

rdar://problem/13752163

Differential Revision: http://reviews.llvm.org/D10099

llvm-svn: 239427
2015-06-09 19:07:19 +00:00
Pete Cooper 5615c6613a Change from alignof to llvm::alignOf to appease Visual Studio
llvm-svn: 239424
2015-06-09 18:50:18 +00:00
Pete Cooper 234b875690 Allocate space for MCSymbol::Name only if required.
Similarly to User which allocates a number of Use's prior to the this pointer,
allocate space for the Name* for MCSymbol only when we need a name.

Given that an MCSymbol is 48-bytes on 64-bit systems, this saves a decent % of space.

Given the verify_uselistorder test case with debug info and llc, 50k symbols have names
out of 700k so this optimises for the common case of temporary unnamed symbols.

Reviewed by David Blaikie.

llvm-svn: 239423
2015-06-09 18:36:13 +00:00
Arnold Schwaighofer 7e226271a1 MergeFunctions: Don't replace a weak function use by another equivalent weak function
We don't know whether the weak functions definition is the definitive definition.

rdar://21303727

llvm-svn: 239422
2015-06-09 18:19:17 +00:00
David Blaikie 0ebe35b278 Revert "[DWARF] Fix a few corner cases in expression emission"
This reverts commit r239380 due to apparently GDB regressions:
http://lab.llvm.org:8011/builders/clang-x86_64-ubuntu-gdb-75/builds/22562

llvm-svn: 239420
2015-06-09 18:01:51 +00:00
Samuel Antao cd50135a29 The constant initialization for globals in NVPTX is generated as an
array of bytes. The generation of this byte arrays was expecting 
the host to be little endian, which prevents big endian hosts to be 
used in the generation of the PTX code. This patch fixes the 
problem by changing the way the bytes are extracted so that it 
works for either little and big endian.

llvm-svn: 239412
2015-06-09 16:29:34 +00:00
Eli Bendersky af79f3dbd3 Add more wrappers for symbol APIs to the C API.
This represents some of the functionality we expose in the llvmlite Python
binding.

Patch by Antoine Pitrou

Differential Revision: http://reviews.llvm.org/D10222

llvm-svn: 239411
2015-06-09 15:57:30 +00:00
Rui Ueyama 7d09919534 Remove object_error::success and use std::error_code() instead
make_error_code(object_error) is slow because object::object_category()
uses a ManagedStatic variable. But the real problem is that the function is
called too frequently. This patch uses std::error_code() instead of
object_error::success. In most cases, we return "success", so this patch
reduces number of function calls to that function.

http://reviews.llvm.org/D10333

llvm-svn: 239409
2015-06-09 15:20:42 +00:00
Toma Tabacu 465acfd13c Recommit "[mips] [IAS] Restore STI.FeatureBits in .set pop." (r239144).
Specified the llvm namespace for the 2 calls to make_unique() which caused
compilation errors in Visual Studio 2013.

llvm-svn: 239405
2015-06-09 13:33:26 +00:00
Elena Demikhovsky 6b62b659cb X86-MPX: Implemented encoding for MPX instructions.
Added encoding tests.

llvm-svn: 239403
2015-06-09 13:02:10 +00:00
Aaron Ballman 3182ee92ba Removing spurious semi colons; NFC.
llvm-svn: 239399
2015-06-09 12:03:46 +00:00
Toma Tabacu 7977cfd52a Revert "[mips] [IAS] Add support for BNE and BEQ with an immediate operand." (r239396).
It was breaking buildbots.

llvm-svn: 239397
2015-06-09 10:43:49 +00:00
Toma Tabacu 5fa8fb5762 [mips] [IAS] Add support for BNE and BEQ with an immediate operand.
Summary:
For some branches, GAS accepts an immediate instead of the 2nd register operand.
We only implement this for BNE and BEQ for now. Other branch instructions can be added later, if needed.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: seanbruno, emaste, llvm-commits

Differential Revision: http://reviews.llvm.org/D9666

llvm-svn: 239396
2015-06-09 10:34:31 +00:00
Daniel Sanders 329fc9b68a [nvptx] Only support the 'm' inline assembly memory constraint. NFC.
Summary:
NVPTX doesn't seem to support any additional constraints. Therefore remove
the target hook.

No functional change intended.

Reviewers: jholewinski

Reviewed By: jholewinski

Subscribers: jholewinski, llvm-commits

Differential Revision: http://reviews.llvm.org/D8209

llvm-svn: 239395
2015-06-09 10:34:05 +00:00
Daniel Sanders 0389d66b0c [ADT] Assert that SmallVectorBase::grow_pod() successfully reallocates memory.
Summary:
If malloc/realloc fails then the SmallVector becomes unusable since begin() and
end() will return NULL. This is unlikely to occur but was the cause of recent
bugpoint test failures on my machine.

It is not clear whether not checking for malloc/realloc failure is a deliberate
decision and adding checks has the potential to impact compiler performance.
Therefore, this patch only adds the check to builds with assertions enabled for
the moment.

Reviewers: bkramer

Reviewed By: bkramer

Subscribers: bkramer, llvm-commits

Differential Revision: http://reviews.llvm.org/D9520

llvm-svn: 239392
2015-06-09 09:47:46 +00:00
Denis Protivensky c09e376d8e MergeFunctions: Fix gcc warning in condition
llvm-svn: 239391
2015-06-09 09:28:37 +00:00
Keno Fischer e34147ce2f [DWARF] Fix a few corner cases in expression emission
Summary: I noticed an object file with `DW_OP_reg4 DW_OP_breg4 0` as a DWARF expression,
which I traced to a missing break (and `++I`) in this code snippet.
While I was at it, I also added support for a few other corner cases
along the same lines that I could think of.

Test Plan: Hand-crafted test case to exercises these cases is included.

Reviewers: echristo, dblaikie, aprantl

Reviewed By: aprantl

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10302

llvm-svn: 239380
2015-06-09 01:53:59 +00:00
Anna Zaks 119046098a [asan] Prevent __attribute__((annotate)) triggering errors on Darwin
The following code triggers a fatal error in the compiler instrumentation
of ASan on Darwin because we place the attribute into llvm.metadata section,
which does not have the proper MachO section name.

void foo() __attribute__((annotate("custom")));
void foo() {;}

This commit reorders the checks so that we skip everything in llvm.metadata
first. It also removes the hard failure in case the section name does not
parse. That check will be done lower in the compilation pipeline anyway.

(Reviewed in http://reviews.llvm.org/D9093.)

llvm-svn: 239379
2015-06-09 00:58:08 +00:00
Matt Arsenault 705eb8f6b1 Implement computeKnownBits for min/max nodes
llvm-svn: 239378
2015-06-09 00:52:41 +00:00
Matt Arsenault 5881f4e1e4 R600: Switch to using generic min / max nodes.
llvm-svn: 239377
2015-06-09 00:52:37 +00:00
Matt Arsenault 8b643559d4 MC: Add target hook to control symbol quoting
llvm-svn: 239370
2015-06-09 00:31:39 +00:00
Arnold Schwaighofer 003c2e937b Fix unused variable warning
llvm-svn: 239369
2015-06-09 00:17:40 +00:00
Jingyue Wu 2e4d1dd0ed [NVPTX] run SROA after NVPTXFavorNonGenericAddrSpaces
Summary:
This cleans up most allocas NVPTXLowerKernelArgs emits for byval
parameters.

Test Plan: makes bug21465.ll more stronger to verify no redundant local load/store.

Reviewers: eliben, jholewinski

Reviewed By: eliben, jholewinski

Subscribers: jholewinski, llvm-commits

Differential Revision: http://reviews.llvm.org/D10322

llvm-svn: 239368
2015-06-09 00:05:56 +00:00
Arnold Schwaighofer 0302da614a MergeFunctions: Impose a total order on the replacement of functions
We don't want to replace function A by Function B in one module and Function B
by Function A in another module.

If these functions are marked with linkonce_odr we would end up with a function
stub calling B in one module and a function stub calling A in another module. If
the linker decides to pick these two we will have two stubs calling each other.

rdar://21265586

llvm-svn: 239367
2015-06-09 00:03:29 +00:00
Reid Kleckner b7403336ce [WinEH] Cache declarations of frame intrinsics
llvm-svn: 239361
2015-06-08 22:43:32 +00:00
Reid Kleckner 218a9593db Fix clang-cl self-host -Wc++11-narrowing bug
Use unsigned as the underlying storage type of the AMDGPU address space
enum.

llvm-svn: 239355
2015-06-08 21:57:57 +00:00
Ranjeet Singh 10511a493e [AArch64] AsmParser should be case insensitive about accepting vector register names.
Differential Revision: http://reviews.llvm.org/D10320

llvm-svn: 239353
2015-06-08 21:32:16 +00:00
Keno Fischer e70b31fc1b [InstrInfo] Refactor foldOperandImpl to thread through InsertPt. NFC
Summary:
This was a longstanding FIXME and is a necessary precursor to cases
where foldOperandImpl may have to create more than one instruction
(e.g. to constrain a register class). This is the split out NFC changes from
D6262.

Reviewers: pete, ributzka, uweigand, mcrosier

Reviewed By: mcrosier

Subscribers: mcrosier, ted, llvm-commits

Differential Revision: http://reviews.llvm.org/D10174

llvm-svn: 239336
2015-06-08 20:09:58 +00:00
Benjamin Kramer f1cfc4244c Prefer copy init over direct init. NFC.
llvm-svn: 239327
2015-06-08 18:58:57 +00:00
Akira Hatanaka 4a61619ff5 [ARM] Pass a callback to FunctionPass constructors to enable skipping execution
on a per-function basis.

Previously some of the passes were conditionally added to ARM's pass pipeline
based on the target machine's subtarget. This patch makes changes to add those
passes unconditionally and execute them conditonally based on the predicate
functor passed to the pass constructors. This enables running different sets of
passes for different functions in the module.

rdar://problem/20542263

Differential Revision: http://reviews.llvm.org/D8717

llvm-svn: 239325
2015-06-08 18:50:43 +00:00
Pete Cooper 11472c0a38 Use a PointerUnion in MCSymbol for Section and Fragment. NFC.
The Fragment and Section, and a bool for HasFragment were all used to create
a PointerUnion.  Just use a pointer union instead.

llvm-svn: 239324
2015-06-08 18:41:57 +00:00
Pete Cooper 4915dd076f Remove includes of MCMachOSymbolFlags.h after it was deleted
llvm-svn: 239318
2015-06-08 17:25:57 +00:00
Pete Cooper 916f79ef7b Move all flags logic to MCSymbolMachO.
Also delete the now unused MCMachOSymbolFlags.h header as the only enum in there was moved to MCSymbolMachO.

Similarly to ELF and COFF, manipulating the flags is now done via helpers instead of spread
throughout the codebase.

Reviewed by Rafael Espíndola.

llvm-svn: 239316
2015-06-08 17:17:28 +00:00
Pete Cooper eb012fa761 Add MCSymbolMachO which will be used to hide the MCSymbolMachO flags.
Reviewed by Rafael Espíndola.

llvm-svn: 239315
2015-06-08 17:17:23 +00:00
Pete Cooper 6bf1f3008c Move all of the MCSymbol COFF flags logic in to MCSymbolCOFF.
All flags setting/getting is now done in the class with helper methods instead
of users having to get the bits in the correct order.

Reviewed by Rafael Espíndola.

llvm-svn: 239314
2015-06-08 17:17:19 +00:00
Pete Cooper ad9f9c3517 Add MCSymbolCOFF class and use it to get and set the COFF type field.
Reviewed by Rafael Espíndola.

llvm-svn: 239312
2015-06-08 17:17:12 +00:00
Pete Cooper a3ab3841c0 Change MCSymbol IsELF to an enum to support future MCSymbolCOFF and MCSymbolMachO.
Reviewed by Rafael Espíndola.

llvm-svn: 239311
2015-06-08 17:17:09 +00:00
Matthias Braun 6f8db0e1a7 X86: Reject register operands with obvious type mismatches.
While we have some code to transform specification like {ax} into
{eax}/{rax} if the operand type isn't 16bit, we should reject cases
where there is no sane way to do this, like the i128 type in the
example.

Related to rdar://21042280

Differential Revision: http://reviews.llvm.org/D10260

llvm-svn: 239309
2015-06-08 16:56:23 +00:00
Oliver Stannard 8379e298b3 Fix assertion failure in global-merge with unused ConstantExpr
The global-merge pass was crashing because it assumes that all ConstantExprs
(reached via the global variables that they use) have at least one user.

I haven't worked out a way to test this, as an unused ConstantExpr cannot be
represented by serialised IR, and global-merge can only be run in llc, which
does not run any passes which can make a ConstantExpr dead.

This (reduced to the point of silliness) C code triggers this bug when compiled
for arm-none-eabi at -O1:

  static a = 7;
  static volatile b[10] = {&a};

  c;
  main() {
    c = 0;
    for (; c < 10;)
      printf(b[c]);
  }

Differential Revision: http://reviews.llvm.org/D10314

llvm-svn: 239308
2015-06-08 16:55:31 +00:00
Colin LeMahieu 6aca6f0be5 [Hexagon] Adding functionality for searching for compound instruction pairs. Compound instructions reduce slot resource requirements freeing those packet slots up for more instructions.
llvm-svn: 239307
2015-06-08 16:34:47 +00:00
Simon Pilgrim 4791f6d89b [DAGCombiner] Added CTLZ vector constant folding support.
llvm-svn: 239305
2015-06-08 16:19:00 +00:00
Javed Absar e1c7dc3ee2 ARM]: Add support for MMFR4_EL1 in assembler
This patch adds support for system register MMFR4_EL1 (memory model feature register) in the assembler.
This register provides information about the implemented memory model and memory management support.

llvm-svn: 239302
2015-06-08 15:01:11 +00:00
Petar Jovanovic cf197f0bde [Mips64][mcjit] Add R_MIPS_PC32 relocation
This patch adds R_MIPS_PC32 relocation for Mips64.

Patch by Vladimir Radosavljevic.

Differential Revision: http://reviews.llvm.org/D10235

llvm-svn: 239301
2015-06-08 14:10:23 +00:00
Igor Breger 00d9f8457b AVX-512: Implemented 256/128bit VALIGND/Q instructions for SKX and KNL
Implemented DAG lowering for all these forms.
Added tests for DAG lowering and encoding.

Differential Revision: http://reviews.llvm.org/D10310

llvm-svn: 239300
2015-06-08 14:03:17 +00:00
Artur Pilipenko 7fad7e57e8 Minor refactoring of GEP handling in isDereferenceablePointer
For GEP instructions isDereferenceablePointer checks that all indices are constant and within bounds. Replace this index calculation logic to a call to accumulateConstantOffset. Separated from the http://reviews.llvm.org/D9791

Reviewed By: sanjoy

Differential Revision: http://reviews.llvm.org/D9874

llvm-svn: 239299
2015-06-08 11:58:13 +00:00
Silviu Baranga 98a137196a [LAA] Fix estimation of number of memchecks
Summary:
We need to add a runtime memcheck for pair of accesses (x,y) where at least one of x and y
are writes.
 
Assuming we have w writes and r reads, currently this number is  estimated as being
w* (w+r-1). This estimation will count (write,write) pairs twice and will overestimate
the number of checks required.

This change adds a getNumberOfChecks method to RuntimePointerCheck, which
will count the number of runtime checks needed (similar in implementation to
needsAnyChecking) and uses it to produce the correct number of runtime checks.

Test Plan:
llvm test suite
spec2k
spec2k6

Performance results: no changes observed (not surprising since the formula for 1 writer is basically the same, which would covers most cases - at least with the current check limit).

Reviewers: anemet

Reviewed By: anemet

Subscribers: mzolotukhin, llvm-commits

Differential Revision: http://reviews.llvm.org/D10217

llvm-svn: 239295
2015-06-08 10:27:06 +00:00
Simon Pilgrim c789e1d57b [DAGCombiner] Added CTTZ vector constant folding support.
llvm-svn: 239293
2015-06-08 09:57:09 +00:00
Hao Liu 32c0539691 [LoopVectorize] Teach Loop Vectorizor about interleaved memory accesses.
Interleaved memory accesses are grouped and vectorized into vector load/store and shufflevector.
E.g. for (i = 0; i < N; i+=2) {
       a = A[i];         // load of even element
       b = A[i+1];       // load of odd element
       ...               // operations on a, b, c, d
       A[i] = c;         // store of even element
       A[i+1] = d;       // store of odd element
     }

  The loads of even and odd elements are identified as an interleave load group, which will be transfered into vectorized IRs like:
     %wide.vec = load <8 x i32>, <8 x i32>* %ptr
     %vec.even = shufflevector <8 x i32> %wide.vec, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
     %vec.odd = shufflevector <8 x i32> %wide.vec, <8 x i32> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>

  The stores of even and odd elements are identified as an interleave store group, which will be transfered into vectorized IRs like:
     %interleaved.vec = shufflevector <4 x i32> %vec.even, %vec.odd, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7> 
     store <8 x i32> %interleaved.vec, <8 x i32>* %ptr

This optimization is currently disabled by defaut. To try it by adding '-enable-interleaved-mem-accesses=true'. 

llvm-svn: 239291
2015-06-08 06:39:56 +00:00
Hao Liu 751004a67d [LoopAccessAnalysis] Teach LAA to check the memory dependence between strided accesses.
Differential Revision: http://reviews.llvm.org/D9368

llvm-svn: 239285
2015-06-08 04:48:37 +00:00
Michael Zolotukhin a60bdb5639 Remove SCEVCache and FindConstantPointers from complete loop unrolling heuristic.
Summary:
Using some SCEV functionality helped to entirely remove SCEVCache class and FindConstantPointers SCEV visitor.
Also, this makes the code more universal - I'll take advandate of it in next patches where I start handling additional types of instructions.

Test Plan: Tests would be submitted in subsequent patches.

Reviewers: atrick, chandlerc

Reviewed By: atrick, chandlerc

Subscribers: atrick, llvm-commits

Differential Revision: http://reviews.llvm.org/D10205

llvm-svn: 239282
2015-06-08 03:28:06 +00:00
Peter Collingbourne 7ab1a3b5cf Fix Windows build.
llvm-svn: 239279
2015-06-08 02:43:32 +00:00
Peter Collingbourne fd66a48a75 llvm-ar: Move archive writer to Object.
No functional change intended, other than some minor changes to certain
diagnostics.

Differential Revision: http://reviews.llvm.org/D10296

llvm-svn: 239278
2015-06-08 02:32:01 +00:00
Matt Arsenault e81944fd5e SeparateConstOffsetFromGEP: Pass address space to isLegalAddressingMode
llvm-svn: 239262
2015-06-07 20:17:44 +00:00
Matt Arsenault fb88aca348 Make NaryReassociate pass the address space to isLegalAddressingMode
No test since the kinds of transforms this prevents seem to not really
be relevant for SI's different addressing modes.

llvm-svn: 239261
2015-06-07 20:17:42 +00:00
Matt Arsenault e83379e8e4 Add isLegalAddressingMode address space argument to TTI
Update to match the TLI version, and remove the TLI version's
default argument.

llvm-svn: 239260
2015-06-07 20:12:03 +00:00
Simon Pilgrim 3a7718038d [X86] Added BitScanForward/BitScanReverse memory folding + tests
llvm-svn: 239257
2015-06-07 18:34:25 +00:00
Benjamin Kramer 82f865277e Remove global std::string. NFC.
llvm-svn: 239254
2015-06-07 16:36:28 +00:00
Simon Pilgrim 68cd237f57 [DAGCombiner] Added CTPOP vector constant folding support.
Added tests to the existing SSE/AVX test files.

llvm-svn: 239252
2015-06-07 15:37:14 +00:00
Benjamin Kramer bbd05a2470 [AsmWriter] Rewrite module asm printing using StringRef::split.
No change in output intended.

llvm-svn: 239251
2015-06-07 13:59:33 +00:00
Filipe Cabecinhas a0cb17c379 Fix doxygen comments. NFC
llvm-svn: 239250
2015-06-07 06:40:24 +00:00
David Majnemer 3f0fb98d01 [InstCombine, InstSimplify] Move xforms from Combine to Simplify
There were several SelectInst combines that always returned an existing
instruction instead of modifying an old one or creating a new one.
These are prime candidates for moving to InstSimplify.

llvm-svn: 239229
2015-06-06 22:40:21 +00:00
Filipe Cabecinhas a911af0e8c Use early return idiom. NFC
llvm-svn: 239228
2015-06-06 20:44:53 +00:00
Colin LeMahieu 1c8c213529 [MC] Common symbols weren't being checked for redeclaration which allowed an assembly file to generate an assertion in setCommon(): !isCommon(). This change allows redeclaration as long as the size and alignment match exactly, otherwise report a fatal error.
llvm-svn: 239227
2015-06-06 20:12:40 +00:00
Sanjoy Das ad714b1af3 [LoopUnroll] Fix truncation bug in canUnrollCompletely.
Summary:
canUnrollCompletely takes `unsigned` values for `UnrolledCost` and
`RolledDynamicCost` but is passed in `uint64_t`s that are silently
truncated.  Because of this, when `UnrolledSize` is a large integer
that has a small remainder with UINT32_MAX, LLVM tries to completely
unroll loops with high trip counts.

Reviewers: mzolotukhin, chandlerc

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10293

llvm-svn: 239218
2015-06-06 05:24:10 +00:00
David Majnemer 1c297e66fb [CVP] Don't assume Constants of type i1 can be known to be true or false
CVP wants to analyze the condition operand of a select along an edge.
It succeeds in getting back a Constant but not a ConstantInt.  Instead,
it gets a ConstantExpr.  It then assumes that the Constant must be equal
to false because it isn't equal to true.

Instead, perform an additional comparison.

This fixes PR23752.

llvm-svn: 239217
2015-06-06 04:56:51 +00:00
David Majnemer 468f670021 [InstCombine] Don't miscompile select to poison
If we have (select a, b, c), it is sometimes valid to simplify this to a
single select operand.  However, doing so is only valid if the
computation doesn't inject poison into the computation.

It might be helpful to consider the following example:
  (select (icmp ne %i, INT_MAX), (add nsw %i, 1), INT_MIN)

The select is equivalent to (add %i, 1) but not (add nsw %i, 1).

Self hosting on x86_64 revealed that this occurs very, very rarely so
bailing out is hopefully pretty reasonable.

llvm-svn: 239215
2015-06-06 02:30:43 +00:00
Rafael Espindola f3d49b30b5 Handle 16 bit PC relative relocations.
Fixes pr23771.

llvm-svn: 239214
2015-06-06 02:29:56 +00:00
NAKAMURA Takumi 1781a687e7 TargetParser: Fix comments in enum(s) introduced in r239150. [-Wdocumentation]
llvm-svn: 239211
2015-06-06 01:41:35 +00:00
Craig Topper f4b449cec2 [TableGen] Change OpInit::getNumOperands and getOperand to use unsigned integers. NFC
llvm-svn: 239210
2015-06-06 01:34:04 +00:00
Craig Topper 1af1566ce6 [TableGen] Remove trailing whitespace, add space between 'if' and paren, other formatting fixes. NFC
llvm-svn: 239209
2015-06-06 01:34:01 +00:00
Craig Topper 5a2dfdcd20 [TableGen] Remove unnecessary temporary. NFC
llvm-svn: 239208
2015-06-06 01:34:00 +00:00
Craig Topper 5904beb666 [TableGen] Fold variable declaration/initialization into if condition for a couple short lived variables. NFC
llvm-svn: 239207
2015-06-06 01:33:58 +00:00
Craig Topper daf263de84 [TableGen] Remove unnecessary outer 'if' and merge it's conditions into the inner 'if's. NFC
llvm-svn: 239206
2015-06-06 01:33:55 +00:00
Craig Topper 25a849ca02 [TableGen] Fold variable declarations with their assignments. NFC
llvm-svn: 239205
2015-06-06 00:44:45 +00:00
Akira Hatanaka c100c56a20 Move the code in TargetPassConfig::addPass that inserts machine printer pass to
the overloaded version of addPass which takes Pass*.

This change enables inserting the machine printer pass when the overloaded
version of addPass that takes Pass* is called to add a pass, instead of the
one which takes AnalysisID. I need this to prevent make-check tests from
failing when I commit another patch later.

llvm-svn: 239192
2015-06-05 21:58:14 +00:00
Renato Golin 3dabb23384 Revert "[InstCombine] Rephrase fix to SimplifyWithOpReplaced"
This reverts commit r239141. This commit was an attempt to reintroduce
a previous patch that broke many self-hosting bots with clang timeouts,
but it still has slowdown issues, at least  on ARM, increasing the
compilation time (stage 2, clang's) by 5x.

llvm-svn: 239175
2015-06-05 18:24:12 +00:00
Rafael Espindola b20fbb8b15 Refactor padding writing into a helper function.
llvm-svn: 239174
2015-06-05 18:21:00 +00:00
Sanjoy Das c80dad6f18 [InstCombine][NFC] Add a ``break;`` statement.
This change is NFC because both the ``break;`` and the fall through end
up returning immediately. However, this helps clarify intent and also
ensures correctness in case more ``case`` blocks are added later.

llvm-svn: 239172
2015-06-05 18:04:46 +00:00
Sanjoy Das 72cb5e1087 [InstCombine] Fix PR23751.
PR23751 was caused by a missing ``break;`` in r234388.

llvm-svn: 239171
2015-06-05 18:04:42 +00:00
Peter Collingbourne 6679fc1a79 Revert r238473, "Thumb2: Modify codegen for memcpy intrinsic to prefer LDM/STM."
as it caused miscompilations and assertion failures (PR23768,
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20150601/280380.html).

llvm-svn: 239169
2015-06-05 18:01:28 +00:00
Rafael Espindola 7830fc83be Save a map lookup. NFC.
llvm-svn: 239168
2015-06-05 17:54:25 +00:00
Fiona Glaser 666e352440 DAGCombiner: don't duplicate (fmul x, c) in visitFNEG if fneg is free
For targets with a free fneg, this fold is always a net loss if it
ends up duplicating the multiply, so definitely avoid it.

This might be true for some targets without a free fneg too, but
I'll leave that for future investigation.

llvm-svn: 239167
2015-06-05 17:52:34 +00:00
Yaron Keren 4849aa35b7 Rangify more for loops in LegacyPassManager.cpp.
llvm-svn: 239166
2015-06-05 17:48:47 +00:00
Chandler Carruth 9dabd14d59 [Unroll] Rework the naming and structure of the new unroll heuristics.
The new naming is (to me) much easier to understand. Here is a summary
of the new state of the world:

- '*Threshold' is the threshold for full unrolling. It is measured
  against the estimated unrolled cost as computed by getUserCost in TTI
  (or CodeMetrics, etc). We will exceed this threshold when unrolling
  loops where unrolling exposes a significant degree of simplification
  of the logic within the loop.
- '*PercentDynamicCostSavedThreshold' is the percentage of the loop's
  estimated dynamic execution cost which needs to be saved by unrolling
  to apply a discount to the estimated unrolled cost.
- '*DynamicCostSavingsDiscount' is the discount applied to the estimated
  unrolling cost when the dynamic savings are expected to be high.

When actually analyzing the loop, we now produce both an estimated
unrolled cost, and an estimated rolled cost. The rolled cost is notably
a dynamic estimate based on our analysis of the expected execution of
each iteration.

While we're still working to build up the infrastructure for making
these estimates, to me it is much more clear *how* to make them better
when they have reasonably descriptive names. For example, we may want to
apply estimated (from heuristics or profiles) dynamic execution weights
to the *dynamic* cost estimates. If we start doing that, we would also
need to track the static unrolled cost and the dynamic unrolled cost, as
only the latter could reasonably be weighted by profile information.

This patch is sadly not without functionality change for the new unroll
analysis logic. Buried in the heuristic management were several things
that surprised me. For example, we never subtracted the optimized
instruction count off when comparing against the unroll heursistics!
I don't know if this just got lost somewhere along the way or what, but
with the new accounting of things, this is much easier to keep track of
and we use the post-simplification cost estimate to compare to the
thresholds, and use the dynamic cost reduction ratio to select whether
we can exceed the baseline threshold.

The old values of these flags also don't necessarily make sense. My
impression is that none of these thresholds or discounts have been tuned
yet, and so they're just arbitrary placehold numbers. As such, I've not
bothered to adjust for the fact that this is now a discount and not
a tow-tier threshold model. We need to tune all these values once the
logic is ready to be enabled.

Differential Revision: http://reviews.llvm.org/D9966

llvm-svn: 239164
2015-06-05 17:01:43 +00:00
Alexei Starovoitov 8cf9a4c472 [bpf] rename triple names bpf_be -> bpfeb
llvm-svn: 239162
2015-06-05 16:11:14 +00:00
Colin LeMahieu be8c453d58 [Hexagon] Reapply r239097 with tests corrected for shuffling and duplexing.
llvm-svn: 239161
2015-06-05 16:00:11 +00:00
Benjamin Kramer f2d06a574a [TargetParser] Properly attach functions of ARMTargetParser to the class
llvm-svn: 239158
2015-06-05 14:33:02 +00:00
Benjamin Kramer 113b2a943f [ARM] Make helper function static.
This one had a declaration but it differed from the definition so the
declaration was actually dead.

llvm-svn: 239157
2015-06-05 14:32:54 +00:00
Yaron Keren 3b1e24be56 Rangify for loops in LegacyPassManager.cpp.
llvm-svn: 239155
2015-06-05 14:15:07 +00:00
John Brawn 985c04e8fa [ARM] Add support for -sp- FPUs and FPU none to TargetParser
These are added mainly for the benefit of clang, but this also means that they
are now allowed in .fpu directives and we emit the correct .fpu directive when
single-precision-only is used.

Differential Revision: http://reviews.llvm.org/D10238

llvm-svn: 239151
2015-06-05 13:31:19 +00:00
John Brawn d03d22922d [ARM] Add knowledge of FPU subtarget features to TargetParser
Add getFPUFeatures to TargetParser, which gets the list of subtarget features
that are enabled/disabled for each FPU, and use it when handling the .fpu
directive.

No functional change in this commit, though clang will start behaving
differently once it starts using this.

Differential Revision: http://reviews.llvm.org/D10237

llvm-svn: 239150
2015-06-05 13:29:24 +00:00
Artyom Skrobov acd1cd66c1 [ARMTargetParser] Follow-up for r239099: one case was missed
llvm-svn: 239147
2015-06-05 12:39:28 +00:00
Toma Tabacu 399a56d771 Revert "[mips] [IAS] Restore STI.FeatureBits in .set pop." (r239144).
This is breaking the Windows buildbots.

llvm-svn: 239145
2015-06-05 12:19:27 +00:00
Toma Tabacu 89ebf88ff3 [mips] [IAS] Restore STI.FeatureBits in .set pop.
Summary:
Only restoring AvailableFeatures is not enough and will lead to buggy behaviour.
For example, if we have a feature enabled and we ".set pop", the next time we try
to ".set" that feature nothing will happen because the "!(STI.getFeatureBits()[Feature])"
check will be false, because we didn't restore STI.FeatureBits.

In order to fix this, we need to make MipsAssemblerOptions remember the STI.FeatureBits
instead of the AvailableFeatures and then regenerate AvailableFeatures each time we ".set pop".
This is because, AFAIK, there is no way to convert from AvailableFeatures back to STI.FeatureBits,
but the reverse is possible by using ComputeAvailableFeatures(STI.FeatureBits).

I also moved the updating of AssemblerOptions inside the "if" statement in
setFeatureBits() and clearFeatureBits(), as there is no reason to update if
nothing changes.

Reviewers: dsanders, mkuper

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9156

llvm-svn: 239144
2015-06-05 11:48:54 +00:00
David Majnemer b58f32f7a8 [LoopVectorize] Don't crash on zero-sized types in isInductionPHI
isInductionPHI wants to calculate the stride based on the pointee size.
However, this is not possible when the pointee is zero sized.

This fixes PR23763.

llvm-svn: 239143
2015-06-05 10:52:40 +00:00
Andrea Di Biagio eb33134ce7 Simplify code; NFC.
Also, moved test cases from CodeGen/X86/fold-buildvector-bug.ll into
CodeGen/X86/buildvec-insertvec.ll and regenerated CHECK lines using
update_llc_test_checks.py.

llvm-svn: 239142
2015-06-05 10:29:55 +00:00
David Majnemer 6d8081835d [InstCombine] Rephrase fix to SimplifyWithOpReplaced
I don't have the IR which is causing the build bot breakage but I can
postulate as to why they are timing out:
1. SimplifyWithOpReplaced was stripping flags from the simplified value.
2. visitSelectInstWithICmp was overriding SimplifyWithOpReplaced because
   it's simplification wasn't correct.
3. InstCombine would revisit the add instruction and note that it can
   rederive the flags.
4. By modifying the value, we chose to revisit instructions which reuse
   the value.  One of the instructions is the original select, causing
   LLVM to never reach fixpoint.

Instead, strip the flags only when we are sure we are going to perform
the simplification.

llvm-svn: 239141
2015-06-05 09:57:57 +00:00
Daniel Jasper 917fa5ee66 Revert "[InstCombine] Don't miscompile safe increment idiom"
This is breaking a lot of build bots and is causing very long-running
compiles (infinite loops)?

Likely, we shouldn't return nullptr?

llvm-svn: 239139
2015-06-05 09:31:20 +00:00
Justin Bogner d49d8eec12 InstrProf: Fix reading of consecutive 32 bit coverage maps
When we generate coverage data, we explicitly set each coverage map's
alignment to 8 (See InstrProfiling::lowerCoverageData), but when we
read the coverage data, we assume consecutive maps are exactly
adjacent. When we're dealing with 32 bit, maps can end on a 4 byte
boundary, causing us to think the padding is part of the next record.

Fix this by adjusting the buffer to an appropriately aligned address
between records.

This is pretty awkward to test, as it requires a binary with multiple
coverage maps to hit, so we'd need to check in multiple source files
and a binary blob as inputs.

llvm-svn: 239129
2015-06-05 01:23:42 +00:00
Jim Grosbach bb2591f5ef MC: Clean up naming in MCObjectFileInfo.h.
Init*() methods to init*().

llvm-svn: 239121
2015-06-04 23:35:03 +00:00
Jim Grosbach 56ed0bb111 MC: Clean up the naming for MCMachObjectWriter. NFC.
s/ExecutePostLayoutBinding/executePostLayoutBinding/
s/ComputeSymbolTable/computeSymbolTable/
s/BindIndirectSymbols/bindIndirectSymbols/
s/RecordTLVPRelocation/recordTLVPRelocation/
s/RecordScatteredRelocation/recordScatteredRelocation/
s/WriteLinkerOptionsLoadCommand/writeLinkerOptionsLoadCommand/
s/WriteLinkeditLoadCommand/writeLinkeditLoadCommand/
s/WriteNlist/writeNlist/
s/WriteDysymtabLoadCommand/writeDysymtabLoadCommand/
s/WriteSymtabLoadCommand/writeSymtabLoadCommand/
s/WriteSection/writeSection/
s/WriteSegmentLoadCommand/writeSegmentLoadCommand/
s/WriteHeader/writeHeader/

llvm-svn: 239119
2015-06-04 23:25:54 +00:00
Alexey Samsonov 49179ddba4 [Object, ELF] Don't assert on invalid magic in createELFObjectFile.
Instead, return a proper error code from factory.

llvm-svn: 239116
2015-06-04 23:14:43 +00:00
David Majnemer 00f7d9ecc8 [InstCombine] Don't miscompile safe increment idiom
We cleverly handle cases where computation done in one argument of a select
instruction is suitable for the other operand, thus obviating the need
of the select and the comparison.  However, the other operand cannot
have flags.

This fixes PR23757.

llvm-svn: 239115
2015-06-04 23:11:30 +00:00
Swaroop Sridhar 70d18df18f Statepoint: Fix handling of Far Immediate calls
gc.statepoint intrinsics with a far immediate call target 
were lowered incorrectly as pc-rel32 calls.

This change fixes the problem, and generates an indirect call 
via a scratch register.

For example: 

Intrinsic:
  %safepoint_token = call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* inttoptr (i64 140727162896504 to void ()*), i32 0, i32 0, i32 0, i32 0)

Old Incorrect Lowering:
  callq 140727162896504

New Correct Lowering:
  movabsq $140727162896504, %rax 
  callq *%rax

In lowerCallFromStatepoint(), the callee-target was modified and 
represented as a "TargetConstant" node, rather than a "Constant" node.
Undoing this modification enabled LowerCall() to generate the 
correct CALL instruction.

llvm-svn: 239114
2015-06-04 23:03:21 +00:00
Alexey Samsonov 18ad2e54ab [Object, ELF] Don't call llvm_unreachable() from createELFObjectFile.
Instead, return a proper error code from factory.

llvm-svn: 239113
2015-06-04 22:58:25 +00:00
Charles Davis da280728b6 [Target/X86] Don't use callee-saved registers in a Win64 tail call on non-Windows.
Summary:
A small bit that I missed when I updated the X86 backend to account for
the Win64 calling convention on non-Windows. Now we don't use dead
non-volatile registers when emitting a Win64 indirect tail call on
non-Windows.

Should fix PR23710.

Test Plan: Added test for the correct behavior based on the case I posted to PR23710.

Reviewers: rnk

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10258

llvm-svn: 239111
2015-06-04 22:50:05 +00:00
Alexey Samsonov fa5edc5a36 [Object, MachO] Fixup for r239075: use union to store mach_header and mach_header_64.
llvm-svn: 239110
2015-06-04 22:49:55 +00:00
Alexey Samsonov f8a7bf8c6e [Object, MachO] Don't crash on incomplete MachO segment load commands.
Report proper error code from MachOObjectFile constructor if we
can't parse another segment load command (we already return a proper
error if segment load command contents is suspicious).

llvm-svn: 239109
2015-06-04 22:26:44 +00:00