Commit Graph

3482 Commits

Author SHA1 Message Date
Evan Cheng 6cc775f905 - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and
sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.

llvm-svn: 134021
2011-06-28 19:10:37 +00:00
Evan Cheng 45a6f21a77 Alternative name enum should go into the enum portion.
llvm-svn: 133979
2011-06-28 01:36:01 +00:00
Jim Grosbach a6f7a1efcc ARM Assembly support for Thumb mov-immediate.
Correctly parse the forms of the Thumb mov-immediate instruction:
  1. 8-bit immediate 0-255.
  2. 12-bit shifted-immediate.

The 16-bit immediate "movw" form is also legal with just a "mov" mnemonic,
but is not yet supported. More parser logic necessary there due to fixups.

llvm-svn: 133966
2011-06-27 23:54:06 +00:00
Evan Cheng 105974d497 Remove RCBarriers from TargetInstrDesc.
llvm-svn: 133964
2011-06-27 23:47:21 +00:00
Owen Anderson a84be6c96b Add support for alternative register names, useful for instructions whose operands are logically equivalent to existing registers, but happen to be printed specially. For example, an instruciton that prints d0[0] instead of s0.
Patch by Jim Grosbach.

llvm-svn: 133940
2011-06-27 21:06:21 +00:00
Evan Cheng 2977f0ade3 More refactoring. MC doesn't need know about subreg indices.
llvm-svn: 133927
2011-06-27 19:24:13 +00:00
Evan Cheng d9997acd14 Merge XXXGenRegisterDesc.inc XXXGenRegisterNames.inc XXXGenRegisterInfo.h.inc
into XXXGenRegisterInfo.inc.

llvm-svn: 133922
2011-06-27 18:32:37 +00:00
Evan Cheng 5f83678222 Remove dead typedefs.
llvm-svn: 133851
2011-06-25 00:27:17 +00:00
Evan Cheng 4ffc43bce0 Rename TargetRegisterDesc to MCRegisterDesc
llvm-svn: 133845
2011-06-24 23:44:48 +00:00
Bob Wilson d2a4a871a9 Revert "Shorten some ARM builtin names by removing unnecessary "neon" prefix."
Sorry, this was a bad idea.  Within clang these builtins are in a separate
"ARM" namespace, but the actual builtin names should clearly distinguish that
they are target specific.

llvm-svn: 133832
2011-06-24 22:13:17 +00:00
Bob Wilson 4f728fd0de Shorten some ARM builtin names by removing unnecessary "neon" prefix.
llvm-svn: 133825
2011-06-24 21:32:40 +00:00
Evan Cheng e862d59eee - Add MCRegisterInfo registration machinery. Also added x86 registration routines.
- Rename TargetRegisterDesc to MCRegisterDesc.

llvm-svn: 133820
2011-06-24 20:42:09 +00:00
Benjamin Kramer bb576b3156 Make the generated InitXXXMCRegisterInfo function "static inline", so it doesn't get emitted into multiple object files.
This caused linker errors when linking both libLLVMX86Desc and libLLVMX86CodeGen
into a single binary (for example when building a monolithic libLLVM shared library).

llvm-svn: 133791
2011-06-24 11:03:31 +00:00
Evan Cheng 247533179a Starting to refactor Target to separate out code that's needed to fully describe
target machine from those that are only needed by codegen. The goal is to
sink the essential target description into MC layer so we can start building
MC based tools without needing to link in the entire codegen.

First step is to refactor TargetRegisterInfo. This patch added a base class
MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to
separate register description from the rest of the stuff.

llvm-svn: 133782
2011-06-24 01:44:41 +00:00
Andrew Trick 67ff0718a4 lit support for REQUIRES: asserts.
Take #2. Don't piggyback on the existing config.build_mode. Instead,
define a new lit feature for each build feature we need (currently
just "asserts"). Teach both autoconf'd and cmake'd Makefiles to define
this feature within test/lit.site.cfg. This doesn't require any lit
harness changes and should be more robust across build systems.

llvm-svn: 133664
2011-06-22 23:23:19 +00:00
Francois Pichet 941424b3ff Unbreak the CMake build
llvm-svn: 133574
2011-06-21 23:19:23 +00:00
Jim Grosbach 797cff0504 Consolidate some TableGen diagnostic helper functions.
TableGen had diagnostic printers sprinkled about in a few places. Pull them
together into a single location in Error.cpp.

llvm-svn: 133568
2011-06-21 22:55:50 +00:00
Jakob Stoklund Olesen d9149a45ea Skip fields that don't exist in the Register class.
llvm-svn: 133470
2011-06-20 20:56:05 +00:00
Jakob Stoklund Olesen 3bd1b65ed3 Add a RegisterTuples class to Target.td and TableGen.
A RegisterTuples instance is used to synthesize super-registers by
zipping together lists of sub-registers. This is useful for generating
pseudo-registers representing register sequence constraints like 'two
consecutive GPRs', or 'an even-odd pair of floating point registers'.

The RegisterTuples def can be used in register set operations when
building register classes. That is the only way of accessing the
synthesized super-registers.

For example, the ARM QQ register class of pseudo-registers could have
been formed like this:

  // Form pairs Q0_Q1, Q2_Q3, ...
  def QQPairs : RegisterTuples<[qsub_0, qsub_1],
                               [(decimate QPR, 2),
                                (decimate (shl QPR, 1), 2)]>;

  def QQ : RegisterClass<..., (add QQPairs)>;

Similarly, pseudo-registers representing '3 consecutive D-regs with
wraparound' look like:

  // Form D0_D1_D2, D1_D2_D3, ..., D30_D31_D0, D31_D0_D1.
  def DSeqTriples : RegisterTuples<[dsub_0, dsub_1, dsub_2],
                                   [(rotl DPR, 0),
                                    (rotl DPR, 1),
                                    (rotl DPR, 2)]>;

TableGen automatically computes aliasing information for the synthesized
registers.

Register tuples are still somewhat experimental. We still need to see
how they interact with MC.

llvm-svn: 133407
2011-06-20 02:50:54 +00:00
Chris Lattner f3f545ea8a fix the varargs version of StructType::get to not require an LLVMContext, making usage
much cleaner.

llvm-svn: 133364
2011-06-18 22:48:56 +00:00
Jakob Stoklund Olesen afef422265 Use the correct comparator to avoid depending on pointer values.
This should fix the Linux buildbots.

llvm-svn: 133334
2011-06-18 05:44:55 +00:00
Jakob Stoklund Olesen 8e188be035 Store CodeGenRegisters as pointers so they won't be reallocated.
Reuse the CodeGenRegBank DenseMap in a few places that would build their
own or use linear search.

llvm-svn: 133333
2011-06-18 04:26:06 +00:00
Jakob Stoklund Olesen d53674aaf1 Remove MethodProtos/MethodBodies and allocation_order_begin/end.
Targets that need to change the default allocation order should use the
AltOrders mechanism instead. See the X86 and ARM targets for examples.

The allocation_order_begin() and allocation_order_end() methods have been
replaced with getRawAllocationOrder(), and there is further support
functions in RegisterClassInfo.

It is no longer possible to insert arbitrary code into generated
register classes. This is a feature.

llvm-svn: 133332
2011-06-18 03:08:20 +00:00
Jakob Stoklund Olesen 35cea3da35 Provide AltOrders for specifying alternative allocation orders.
A register class can define AltOrders and AltOrderSelect instead of
defining method protos and bodies. The AltOrders lists can be defined
with set operations, and TableGen can verify that the alternative
allocation orders only contain valid registers.

This is currently an opt-in feature, and it is still possible to
override allocation_order_begin/end. That will not be true for long.

llvm-svn: 133320
2011-06-18 00:50:49 +00:00
Owen Anderson f5a0ca46b6 Fix formatting.
llvm-svn: 133164
2011-06-16 16:52:24 +00:00
Jakob Stoklund Olesen 72f4b85119 Prempt some obnoxious compiler from complaing about signed/unsigned
compares.

2^30 is actually the limit on the number of physical registers per
TargetRegisterInfo.h.

llvm-svn: 133142
2011-06-16 03:07:40 +00:00
Jakob Stoklund Olesen e3ebb40ff1 Make sure to pass an unsigned to a printf format that is always %u.
This should unbreak the native ARM testers.

llvm-svn: 133141
2011-06-16 02:55:56 +00:00
Andrew Trick 6132fb5127 Add support to lit for build mode requirements. e.g.
REQUIRES: Asserts
REQUIRES: Debug

This required chaining test configuration properties. It seems like a
generally good thing to do.

llvm-svn: 133131
2011-06-16 01:33:35 +00:00
Owen Anderson 96adc4a540 Add a new MVT::untyped. This will be used in future work for modelling ISA features like register pairs and lists with "interesting" constraints (such as ARM NEON contiguous register lists or even-odd paired registers). We need to be able to generate these instructions (often from intrinsics), but don't want to have to assign a legal type to them. Instead, we'll use an "untyped" edge to bypass the type-checking and simply ensure that the register classes match.
llvm-svn: 133106
2011-06-15 23:35:18 +00:00
John McCall 7cfd1cfa86 Update the Clang diagnostic emitter to emit IDs for diagnostic categories.
Patch by Argyrios Kyrtzidis.

llvm-svn: 133093
2011-06-15 21:43:52 +00:00
John McCall 4b7a8d68ae Add a new function attribute, nonlazybind, which inhibits lazy-loading
optimizations when emitting calls to the function;  instead those calls may
use faster relocations which require the function to be immediately resolved
upon loading the dynamic object featuring the call.  This is useful when it
is known that the function will be called frequently and pervasively and
therefore there is no merit in delaying binding of the function.

Currently only implemented for x86-64, where it turns into a call through
the global offset table.

Patch by Dan Gohman, who assures me that he's going to add LangRef documentation
for this once it's committed.

llvm-svn: 133080
2011-06-15 20:36:13 +00:00
Owen Anderson 86fd3c0058 Replace the statically generated hashtables for checking register relationships with just scanning the (typically tiny) static lists.
At the time I wrote this code (circa 2007), TargetRegisterInfo was using a std::set to perform these queries.  Switching to the static hashtables was an obvious improvement, but in reality there's no reason to do anything other than scan.
With this change, total LLC time on a whole-program 403.gcc is reduced by approximately 1.5%, almost all of which comes from a 15% reduction in LiveVariables time.  It also reduces the binary size of LLC by 86KB, thanks to eliminating a bunch of very large static tables.

llvm-svn: 133051
2011-06-15 06:53:50 +00:00
Jakob Stoklund Olesen 5ee87726dd Use a SetTheory instance to expand register lists in register classes.
This prepares tablegen to compute register lists from set theoretic dag
expressions. This doesn't really make any difference as long as
Target.td still declares RegisterClass::MemberList as [Register].

llvm-svn: 133043
2011-06-15 05:09:20 +00:00
Jakob Stoklund Olesen d7bc5c26ab Give CodeGenRegisterClass a real sorted member set.
Make the Elements vector private and expose an ArrayRef through
getOrder() instead. getOrder will eventually provide multiple
user-specified allocation orders.

Use the sorted member set for member and subclass tests. Clean up a lot
of ad hoc searches.

llvm-svn: 133040
2011-06-15 04:50:36 +00:00
Bill Wendling 36c0c6db3f Improve the heuristic to emit the alias if the number of hard-coded registers
are also greater than the alias.

llvm-svn: 133038
2011-06-15 04:31:19 +00:00
Jakob Stoklund Olesen 22ea424d43 Move the list of register classes into CodeGenRegBank as well.
No functional change intended.

llvm-svn: 133029
2011-06-15 00:20:40 +00:00
Jakob Stoklund Olesen 01eada6e5c Fix a compile time regression caused by too small hash tables.
Measure the worst case number of probes for a miss instead of the less
conservative number of probes required for an insertion.

Lower the limit to < 6 probes worst case.

This doubles the size of the ARM and X86 hash tables, other targets are
unaffected. LiveVariables runs 12% faster with this change.

<rdar://problem/9598545>

llvm-svn: 132999
2011-06-14 16:58:16 +00:00
Bill Wendling e712449688 Heuristic: If the number of operands in the alias are more than the number of
operands in the aliasee, don't print the alias.

llvm-svn: 132963
2011-06-14 03:17:20 +00:00
Jakob Stoklund Olesen b707659519 Tweak hash function and compress hash tables.
Make the hash tables as small as possible while ensuring that all
lookups can be done in less than 8 probes.

Cut the aliases hash table in half by only storing a < b pairs - it
is a symmetric relation.

Use larger multipliers on the initial hash function to ensure that it
properly covers the whole table, and to resolve some clustering in the
very regular ARM register bank.

This reduces the size of most of these tables by 4x - 8x. For instance,
the ARM tables shrink from 48 KB to 8 KB.

llvm-svn: 132888
2011-06-12 07:04:32 +00:00
Jakob Stoklund Olesen f0528dae27 Remove now dead code.
These computations have been moved to CodeGenRegisters.cpp.

llvm-svn: 132887
2011-06-12 07:04:28 +00:00
Jakob Stoklund Olesen 9184edd230 Extract the generateHashTable function.
The constant hash tables for sub-registers and overlaps are generated
the same way, so extract a function to generate and print the hash
table.

Also use the information computed by CodeGenRegisters.cpp instead of the
locally data.

llvm-svn: 132886
2011-06-12 07:04:26 +00:00
Jakob Stoklund Olesen d2b4713e53 Compute lists of sub-regs, super-regs, and overlapping regs.
Besides moving structural computations to CodeGenRegisters.cpp, this
also well-defines the order of these lists:

- Sub-register lists come from a pre-order traversal of the graph
  defined by the SubRegs lists in the .td files.

- Super-register lists are topologically ordered so no register comes
  before any of its sub-registers. When the sub-register graph is not a
  tree, independent super-registers appear in numerical order.

- Lists of overlapping registers are ordered according to register
  number.

This reverses the order of the super-regs lists, but nobody was
depending on that. The previous order of the overlaps lists was odd, and
it may have depended on the precise behavior of std::stable_sort.

The old computations are still there, but will be removed shortly.

llvm-svn: 132881
2011-06-12 03:05:52 +00:00
Jakob Stoklund Olesen 84bd44eb8f Move the list of registers into CodeGenRegBank.
Also move the sub-register index computations from RegisterInfoEmitter
into CodeGenRegBank.

llvm-svn: 132865
2011-06-11 00:28:06 +00:00
Jakob Stoklund Olesen 76a5a71ec3 Move some sub-register index calculations to CodeGenRegisters.cpp
Create a new CodeGenRegBank class that will eventually hold all the code
that computes the register structure from Records.

llvm-svn: 132849
2011-06-10 18:40:00 +00:00
Jakob Stoklund Olesen 68d6d8ab87 Move TableGen's register bank classes to their own source file.
I'll be moving some more code there to gather all of the
register-specific stuff in one place. Currently it is shared between
CodeGenTarget and RegisterInfoEmitter.

The plan is that CodeGenRegisters can compute the full register bank
structure while RegisterInfoEmitter only will handle the printing part.

llvm-svn: 132788
2011-06-09 18:42:07 +00:00
Bob Wilson 6b03ec7581 Add special-case range checking for VCVT_N intrinsic immediate operands.
Radar 9558930.

llvm-svn: 132782
2011-06-09 16:57:29 +00:00
Chad Rosier d0445fd5a5 Fixed a few illegal paths with llvm_unreachable. Patch by Cameron McInally.
llvm-svn: 132732
2011-06-07 20:41:31 +00:00
Jakob Stoklund Olesen 25b753bb3f Drop a RecordKeeper reference that wasn't necessary.
llvm-svn: 132636
2011-06-04 07:49:55 +00:00
Jakob Stoklund Olesen a4615a6f94 Silence compiler warnings.
llvm-svn: 132624
2011-06-04 05:09:36 +00:00
Jakob Stoklund Olesen fc205a5694 Teach TableGen to evaluate DAG expressions as set operations.
A TableGen backend can define how certain classes can be expanded into
ordered sets of defs, typically by evaluating a specific field in the
record. The SetTheory class can then evaluate DAG expressions that refer
to these named sets.

A number of standard set and list operations are predefined, and the
backend can add more specialized operators if needed. The -print-sets
backend is used by SetTheory.td to provide examples.

This is intended to simplify how register classes are defined:

  def GR32_NOSP : RegisterClass<"X86", [i32], 32, (sub GR32, ESP)>;

llvm-svn: 132621
2011-06-04 04:11:37 +00:00
Nick Lewycky 79286bf251 Rework the logic to not rely on undefined behaviour (1LL << 64). Also simplify.
llvm-svn: 132537
2011-06-03 08:25:39 +00:00
Jakob Stoklund Olesen 75703ca76f Make it possible to have unallocatable register classes.
Some register classes are only used for instruction operand constraints.
They should never be used for virtual registers. Previously, those
register classes were given an empty allocation order, but now you can
say 'let isAllocatable=0' in the register class definition.

TableGen calculates if a register is part of any allocatable register
class, and makes that information available in TargetRegisterDesc::inAllocatableClass.

The goal here is to eliminate use cases for overriding allocation_order_*
methods.

llvm-svn: 132508
2011-06-02 23:07:20 +00:00
Joerg Sonnenberger af5f23ee07 Add new -d option to tblgen. It writes a make(1)-style dependency file.
llvm-svn: 132395
2011-06-01 13:10:15 +00:00
Bruno Cardoso Lopes 394f516d16 Fix ssat and ssat16 encodings for ARM and Thumb. The bit position value
must be encoded decremented by one. Only add encoding tests for ssat16
because ssat can't be parsed yet.

llvm-svn: 132324
2011-05-31 03:33:27 +00:00
Rafael Espindola 08600bcf65 Use the dwarf->llvm mapping to print register names in the cfi
directives.

Fixes PR9826.

llvm-svn: 132317
2011-05-30 20:20:15 +00:00
Rafael Espindola ddffa0e160 Introduce the DwarfRegAlias class for declaring that two registers have the
same dwarf number. This will be used for creating a dwarf number to register
mapping.

The only case that needs this so far is the XMM/YMM registers that unfortunately
do have the same numbers.

llvm-svn: 132314
2011-05-30 17:49:59 +00:00
John McCall 375dcc9ec9 Change how tblgen generates attributes for intrinsics to use a single
switch.  With this newfound organization, teach tblgen how not to give
all intrinsics the 'nounwind' attribute.  Introduce a new intrinsic,
llvm.eh.resume, which does not have this attribute.  Documentation and uses
to follow.

llvm-svn: 132252
2011-05-28 06:31:34 +00:00
Rafael Espindola 836f7db2cc Fix the root cause of the bootstrap failure:
There was no way to check if a given register/mode pair was valid. We now return
an error code (-2) instead of asserting. If anyone thinks that an assert
at this point  is really needed, we can autogen a hasValidDwarfRegNum instead.

llvm-svn: 132236
2011-05-28 00:13:01 +00:00
Argyrios Kyrtzidis 0246d63715 [tablegen] A couple of changes to ClangDiagnosticEmmitter.
-Emit an empty warning option as string ("") instead of 0.
-For diagnostic names also emit the size of the string.

llvm-svn: 132046
2011-05-25 05:04:22 +00:00
Bill Wendling f5199debc0 Use a more efficient data structure for the "operand map". The number of
operands to an instruction aren't great, so an iterative search is fairly quick
and doesn't have the overhead of std::map.

llvm-svn: 131886
2011-05-23 00:18:33 +00:00
Cameron Zwarich 8b76e01c4b Fix PR9947 by placing OPFL_MemRefs on the node using memory operands rather than
the root if there is only one such node. This leaves only 2 verifier failures in
the entire test suite when running "make check".

llvm-svn: 131677
2011-05-19 21:13:30 +00:00
Tanya Lattner 48b182c3a4 In r131488 I misunderstood how VREV works. It splits the vector in half and splits each half. Therefore, the real problem was that we were using a VREV64 for a 4xi16, when we should have been using a VREV32.
Updated test case and reverted change to the PerfectShuffle Table.

llvm-svn: 131529
2011-05-18 06:42:21 +00:00
Tanya Lattner c7e291b354 vrev is incorrectly defined in the perfect shuffle table. The ordering is backwards (should be 0x3210 versus 0x1032) which exposed a bug when doing a shuffle on a 4xi16. I've attached a test case.
llvm-svn: 131488
2011-05-17 20:48:40 +00:00
Jakob Stoklund Olesen 4028ccdbe3 Downgrade a tablegen warning to an error.
Ambiguous sub-register index compositions are OK as long as the backend writer
knows what he is doing.

llvm-svn: 131134
2011-05-10 17:52:59 +00:00
Mon P Wang 92ff16b7bb Fixed MC encoding for index_align for VLD1/VST1 (single element from one lane) for size 32
llvm-svn: 131085
2011-05-09 17:47:27 +00:00
Jakob Stoklund Olesen c8c4ded3c6 Teach TableGen to automatically generate missing SubRegIndex instances.
The RegisterInfo.td file should only specify the indexes that sources need to
refer to. The rest is inferred.

llvm-svn: 131058
2011-05-07 21:22:39 +00:00
Jim Grosbach 59ddb73d47 Improve diagnostics for some parse errors. Not asserting when a user input
error is detected is a good thing.

llvm-svn: 131005
2011-05-06 18:47:45 +00:00
Jim Grosbach 763ac0397e ParseFile() may throw, so extend the try/catch to handle that.
llvm-svn: 131004
2011-05-06 18:39:28 +00:00
Mikhail Glushenkov 67ebd94a5d llvmc: Make it possible to provide an argument to (join).
llvm-svn: 130914
2011-05-05 04:24:58 +00:00
Nick Lewycky 737aac5107 The system suppression file should catch these, but since they *once again* are
not, I'll just add them here and be done with it.

llvm-svn: 130819
2011-05-04 01:03:02 +00:00
Jim Grosbach e6ce2053e7 Tidy up. Add missing newline to generated file.
llvm-svn: 130779
2011-05-03 19:09:56 +00:00
Eli Friedman 3bc13b4feb Filter out pattterns from the FastISel emitter which it doesn't actually know how to handle. No significant functionality change at the moment, but it's necessary for some changes I'm planning.
llvm-svn: 130547
2011-04-29 21:58:31 +00:00
Nick Lewycky 61aed87a49 Rename profile_rt.so to libprofile_rt.so under configure+make (it already was
under cmake).

Add libprofile_rt.a so that we can tell clang to link against it in --coverage
mode. Also turn it on by default in cmake builds.

Oscar, this touches a change you made for EXCLUDE_FROM_ALL support -- I think
I've done the right thing, but please let me know (or fix and commit) if not!

llvm-svn: 130470
2011-04-29 02:12:06 +00:00
Owen Anderson 715973fc6c Fix a bug in tblgen that caused incorrect encodings on instructions that specified operands with "bit" instead of "bits<1>".
Unfortunately, my only testcase for this is fragile, and the ARM AsmParser can't round trip the instruction in question.
<rdar://problem/9345702>

llvm-svn: 130410
2011-04-28 17:51:45 +00:00
Mikhail Glushenkov acb5f8ecf7 Add a TODO.
llvm-svn: 130092
2011-04-24 14:17:41 +00:00
Jay Foad 1a180156b6 Remove unused STL header includes.
llvm-svn: 130068
2011-04-23 19:53:52 +00:00
Johnny Chen 57c892860e Disassembly of A8.6.59 LDR (literal) Encoding T1 (16-bit thumb instruction) should
print out ldr, not ldr.n.

rdar://problem/9267772

llvm-svn: 130008
2011-04-22 19:12:43 +00:00
Bob Wilson 23c28ee17e Define Neon load/store intrinsics for Clang as macros instead of functions.
This is needed so the front-end can see "aligned" attributes on the type
for the pointer arguments.  Radar 9311427.

llvm-svn: 129964
2011-04-22 00:37:01 +00:00
Jakob Stoklund Olesen 6b3396fbd2 Don't allow per-register spill size and alignment.
These values were not used for anything. Spill size and alignment is a property
of the register class, not the register.

llvm-svn: 129906
2011-04-21 03:43:21 +00:00
Jakob Stoklund Olesen 0e34c1dfac Prefer cheap registers for busy live ranges.
On the x86-64 and thumb2 targets, some registers are more expensive to encode
than others in the same register class.

Add a CostPerUse field to the TableGen register description, and make it
available from TRI->getCostPerUse. This represents the cost of a REX prefix or a
32-bit instruction encoding required by choosing a high register.

Teach the greedy register allocator to prefer cheap registers for busy live
ranges (as indicated by spill weight).

llvm-svn: 129864
2011-04-20 18:19:48 +00:00
Eric Christopher 2e3fbaab39 Invert the meaning of printAliasInstr's return value. It now returns
true on success and false on failure. Update callers.

llvm-svn: 129722
2011-04-18 21:28:11 +00:00
Owen Anderson f2e8397b4b Enhance the fixed-length disassembler to support the callbacks necessary for symbolic disassembly.
llvm-svn: 129708
2011-04-18 18:42:26 +00:00
Chris Lattner 80254a53cc Add a new bit that ImmLeaf's can opt into, which allows them to duck out of
the generated FastISel.  X86 doesn't need to generate code to match ADD16ri8 
since ADD16ri will do just fine.  This is a small codesize win in the generated
instruction selector.

llvm-svn: 129692
2011-04-18 06:36:55 +00:00
Chris Lattner 07add49a4b Implement major new fastisel functionality: the matcher can now handle immediates with
value constraints on them (when defined as ImmLeaf's).  This is particularly important
for X86-64, where almost all reg/imm instructions take a i64immSExt32 immediate operand,
which has a value constraint.  Before this patch we ended up iseling the examples into
such amazing code as:

	movabsq	$7, %rax
	imulq	%rax, %rdi
	movq	%rdi, %rax
	ret

now we produce:

	imulq	$7, %rdi, %rax
	ret

This dramatically shrinks the generated code at -O0 on x86-64.

llvm-svn: 129691
2011-04-18 06:22:33 +00:00
Chris Lattner 722f0ccdf9 introduce a new OpKind abstraction which wraps up operand flavors in a tidy little wrapper.
No functionality change.

llvm-svn: 129680
2011-04-17 23:29:05 +00:00
Chris Lattner 9080391b55 change OperandsSignature to use SmallVector<char> instead of std::vector<string>
since the strings are always exactly one character, and there are usually only 2-3 operands.

llvm-svn: 129678
2011-04-17 22:24:13 +00:00
Chris Lattner 0d7a5a7daa since the VT is fixed for a ImmLeaf, there is no reason to expose it to the matching code.
llvm-svn: 129677
2011-04-17 22:17:27 +00:00
Chris Lattner 2ff8c1a25f now that predicates have a decent abstraction layer on them, introduce a new
kind of predicate: one that is specific to imm nodes.  The predicate function
specified here just checks an int64_t directly instead of messing around with
SDNode's.  The virtue of this is that it means that fastisel and other things
can reason about these predicates.

llvm-svn: 129675
2011-04-17 22:05:17 +00:00
Chris Lattner 514e292b72 Rework our internal representation of node predicates to expose more
structure and fix some fixmes.  We now have a TreePredicateFn class
that handles all of the decoding of these things.  This is an internal
cleanup that has no impact on the code generated by tblgen.

llvm-svn: 129670
2011-04-17 21:38:24 +00:00
Chris Lattner 4604bddc07 remove some debugging code I added.
llvm-svn: 129668
2011-04-17 21:36:19 +00:00
Chris Lattner b53ccb8e36 1. merge fast-isel-shift-imm.ll into fast-isel-x86-64.ll
2. implement rdar://9289501 - fast isel should fold trivial multiplies to shifts
3. teach tblgen to handle shift immediates that are different sizes than the 
   shifted operands, eliminating some code from the X86 fast isel backend.
4. Have FastISel::SelectBinaryOp use (the poorly named) FastEmit_ri_ function
   instead of FastEmit_ri to simplify code.

llvm-svn: 129666
2011-04-17 20:23:29 +00:00
Douglas Gregor f29216072e Initial work to improve documentation for Clang's diagnostics, from Matthieu Monrocq
llvm-svn: 129613
2011-04-15 22:04:07 +00:00
Evan Cheng a2e61292f0 Increase SubtargetFeatureKV Value and Implies fields to 64 bits since some targets are getting very close to 32 subtarget features. Also teach tablegen to error when there are more than 64 features to guard against undefined behavior. rdar://9282332
llvm-svn: 129590
2011-04-15 19:35:46 +00:00
Chris Lattner 0ab5e2cded Fix a ton of comment typos found by codespell. Patch by
Luis Felipe Strano Moraes!

llvm-svn: 129558
2011-04-15 05:18:47 +00:00
Bill Wendling 6dd69d9241 Add an option to not print the alias of an instruction. It defaults to "print
the alias".

llvm-svn: 129485
2011-04-13 23:36:21 +00:00
Johnny Chen dc8bf9ec08 Thumb disassembler was erroneously rejecting "blx sp" instruction.
rdar://problem/9267838

llvm-svn: 129320
2011-04-11 23:33:30 +00:00
NAKAMURA Takumi 408c228367 TableGen: Keep the order of DECL_CONTEXT() for DeclNodes.td. RecordVector may be used instead of RecordSet.
The result of DeclNodes.inc was unstable on msys, Windows 7 x64.

llvm-svn: 129317
2011-04-11 23:20:28 +00:00
Daniel Dunbar 0625b1f860 build: Add support for a SHOW_DIAGNOSTICS build variable.
If enabled, this will attempt to use the CC_LOG_DIAGNOSTICS feature I dropped
into Clang to print a log of all the diagnostics generated during an individual
build (from the top-level). Not sure if this will actually be useful, but for
now it is handy for testing the option.

llvm-svn: 129312
2011-04-11 22:37:39 +00:00
Chris Lattner e53c95f180 fix PR9629 - We were lowering regexes like a{{b|c}}d into ab|cd, which
is substantially different than a(b|c)d.  Form the latter regex instead.
This found a few problems in the testsuite, which serves as its test.

llvm-svn: 129196
2011-04-09 06:37:03 +00:00
Chris Lattner 53e0679d6f various cleanups, no functionality change.
llvm-svn: 129192
2011-04-09 06:18:02 +00:00
Bill Wendling 33984c6973 Only emit the AvailableFeatures variable if it's used.
llvm-svn: 129124
2011-04-08 04:08:57 +00:00
Bill Wendling bc3f79044a Replace the old algorithm that emitted the "print the alias for an instruction"
with the newer, cleaner model. It uses the IAPrinter class to hold the
information that is needed to match an instruction with its alias. This also
takes into account the available features of the platform.

There is one bit of ugliness. The way the logic determines if a pattern is
unique is O(N**2), which is gross. But in reality, the number of items it's
checking against isn't large. So while it's N**2, it shouldn't be a massive time
sink.

llvm-svn: 129110
2011-04-07 21:20:06 +00:00
Joerg Sonnenberger fc4789da4a Add support for the VIA PadLock instructions.
llvm-svn: 128826
2011-04-04 16:58:13 +00:00
Joerg Sonnenberger c94780c539 Use array_lengthof
llvm-svn: 128823
2011-04-04 16:25:38 +00:00
Joerg Sonnenberger fb3bce155e Change loops to derive the number of tables automatically
llvm-svn: 128818
2011-04-04 14:42:22 +00:00
Daniel Dunbar 5f74b39764 tlbgen/MC: StringRef's to temporary objects considered harmful.
llvm-svn: 128735
2011-04-01 20:23:52 +00:00
Andrew Trick 8a05f66139 Add annotations to tablegen-generated processor itineraries, or replace them with something meaningful. I want to be able to read and debug the generated tables.
llvm-svn: 128703
2011-04-01 02:22:47 +00:00
Andrew Trick db6ed64529 whitespace
llvm-svn: 128701
2011-04-01 01:56:55 +00:00
Nick Lewycky 41198698aa Fix typo in generated HTML.
llvm-svn: 128594
2011-03-31 00:23:57 +00:00
Bob Wilson 271efda884 Use intrinsics for Neon vmull operations. Radar 9208957.
llvm-svn: 128591
2011-03-31 00:09:35 +00:00
Argyrios Kyrtzidis bcc3388252 ClangSAEmClangSACheckersEmitter, emit info about groups.
llvm-svn: 128515
2011-03-30 00:22:00 +00:00
Matt Beaumont-Gay bceec7f9a8 Quiet a gcc warning about changed name lookup rules
llvm-svn: 128497
2011-03-29 22:25:36 +00:00
Argyrios Kyrtzidis 42d0a6c770 In ClangSACheckersEmitter:
- Also emit a list of packages and groups sorted by name
  - Avoid iterating over DenseSet so that the output of the arrays is deterministic.

llvm-svn: 128489
2011-03-29 21:16:19 +00:00
Argyrios Kyrtzidis 2de9d572e8 For ClangSACheckersEmitter, allow a package to belong to checker group, in which all its checkers will go into the group.
llvm-svn: 128474
2011-03-29 18:53:00 +00:00
Devang Patel 94d1979a95 Remove scripts used by TEST=dbg from here. They now live inside llvm test suite.
llvm-svn: 128425
2011-03-28 20:28:30 +00:00
Duncan Sands d5f631cd2a Partially revert commit 127155: I think it is much more convenient
to have structured log files rather than one big file produced by
piping output.

llvm-svn: 128378
2011-03-27 13:52:32 +00:00
Douglas Gregor fa38bd3dfe Extend Clang's TableGen emitter for attributes to support bool arguments.
llvm-svn: 128330
2011-03-26 03:40:01 +00:00
Duncan Sands 5343a406f8 Useful script for finding regressions in the nightly testsuite.
I think it was written by Pawel Worach.

llvm-svn: 128268
2011-03-25 07:17:44 +00:00
Johnny Chen 72f4a95144 delegate the disassembly of t2ADR to the more generic t2ADDri12/t2SUBri12 instructions, and add a test case for that.
llvm-svn: 128249
2011-03-25 00:17:42 +00:00
Johnny Chen ceef55466a The opcode names ("tLDM", "tLDM_UPD") used for conflict resolution have been stale since
the change to ("tLDMIA", "tLDMIA_UPD").  Update the conflict resolution code and add
test cases for that.

llvm-svn: 128247
2011-03-24 23:42:31 +00:00
Johnny Chen 73193f2475 The ARM disassembler was confused with the 16-bit tSTMIA instruction.
According to A8.6.189 STM/STMIA/STMEA (Encoding T1), there's only tSTMIA_UPD available.
Ignore tSTMIA for the decoder emitter and add a test case for that.

llvm-svn: 128246
2011-03-24 23:21:14 +00:00
Bruno Cardoso Lopes f170f8bff6 Add asm parsing support w/ testcases for strex/ldrex family of instructions
llvm-svn: 128236
2011-03-24 21:04:58 +00:00
Johnny Chen 8bbc12824a ADR was added with the wrong encoding for inst{24-21}, and the ARM decoder was fooled.
Set the encoding bits to {0,?,?,0}, not 0.  Plus delegate the disassembly of ADR to
the more generic ADDri/SUBri instructions, and add a test case for that.

llvm-svn: 128234
2011-03-24 20:42:48 +00:00
Douglas Gregor c5ed638408 Update the Clang attribute emitter to handle attributes of 'version'
kind, and fix serialization/deserialization of IdentifierInfo
attributes. These are requires for the new 'availability' attribute.

llvm-svn: 128130
2011-03-23 01:05:46 +00:00
Bill Wendling 1cd7bd62e4 Call static functions so that they aren't left unused.
llvm-svn: 128020
2011-03-21 21:08:27 +00:00
Bill Wendling 7e570b5ed8 A WIP commit of the InstAlias printing cleanup. This code will soon replace the
code below it. Even though it looks very similar, it will match more precisely
and geneate better functions in the long run.

llvm-svn: 127991
2011-03-21 08:59:17 +00:00
Bill Wendling 5d3174c102 Add the IAPrinter class.
This is a helper class that will make it easier to say which InstAliases can be
printed and which cannot (because of ambiguity).

llvm-svn: 127990
2011-03-21 08:40:31 +00:00
Bill Wendling 7e5771d7ce * Add classes that support the "feature" information.
* Move the code that emits the reg in reg class matching into its own function.

llvm-svn: 127988
2011-03-21 08:31:53 +00:00
Owen Anderson eb4b63d66e Thumb2 PC-relative loads require a fixup rather than just an immediate.
llvm-svn: 127888
2011-03-18 17:42:55 +00:00
NAKAMURA Takumi bac0d769cd raw_ostream: [PR6745] Tweak formatting (double)%e for Windows hosts.
On MSVCRT and compatible, output of %e is incompatible to Posix by default. Number of exponent digits should be at least 2. "%+03d"

FIXME: Implement our formatter in future!
llvm-svn: 127872
2011-03-18 09:30:10 +00:00
NAKAMURA Takumi 920139ca08 lit/ProgressBar.py: [PR7919] Improve line wrap for XN-incapable terminals.
On Win32 console, emitting char to col#79 causes linefeed, and the cursor will not return to col#79 upper line with backspace.

llvm-svn: 127696
2011-03-15 21:07:44 +00:00
Evan Cheng 880e299dcd - Add "Bitcast" target instruction property for instructions which perform
nothing more than a bitcast.
- Teach tablegen to automatically infer "Bitcast" property.

llvm-svn: 127667
2011-03-15 05:09:26 +00:00
Sean Callanan c3fd523731 X86 table-generator and disassembler support for the AVX
instruction set.  This code adds support for the VEX prefix
and for the YMM registers accessible on AVX-enabled
architectures.  Instruction table support that enables AVX
instructions for the disassembler is in an upcoming patch.

llvm-svn: 127644
2011-03-15 01:23:15 +00:00
Owen Anderson 0fabf10388 Ignore isCodeGenOnly instructions when generating diassembly tables.
llvm-svn: 127619
2011-03-14 20:58:49 +00:00
Jim Grosbach 876ee079fc Trailing whitespace.
llvm-svn: 127592
2011-03-14 17:32:49 +00:00
Francois Pichet 0fc06eefad Correct small comment order typo.
llvm-svn: 127575
2011-03-14 02:30:32 +00:00
Jim Grosbach fcc34cacd9 Remove no-longer-correct special case for disasm of ARM BL instructions.
llvm-svn: 127517
2011-03-12 01:05:29 +00:00
Jim Grosbach f026d9ed53 Pseudo-ize the ARM 'B' instruction.
llvm-svn: 127510
2011-03-11 23:24:15 +00:00
Jim Grosbach 2fee5327aa Remove dead code. These ARM instruction definitions no longer exist.
llvm-svn: 127509
2011-03-11 23:15:02 +00:00
Jim Grosbach 376d5e8772 Remove dead code. These ARM instruction definitions no longer exist.
llvm-svn: 127508
2011-03-11 23:11:41 +00:00
Jim Grosbach bb0547d9c4 Pseudo-ize VMOVDcc and VMOVScc.
llvm-svn: 127506
2011-03-11 23:09:50 +00:00
Jim Grosbach 52594d99e4 Remove dead code. These ARM instruction definitions don't exist.
llvm-svn: 127491
2011-03-11 20:51:07 +00:00
Jim Grosbach 59eea670f8 ARM VDUPfd and VDUPfq can just be patterns. The instruction is the same
as for VDUP32d and VDUP32q, respectively.

llvm-svn: 127489
2011-03-11 20:44:08 +00:00
Jim Grosbach 6c609d626f Remove dead code. These ARM instruction definitions don't exist.
llvm-svn: 127488
2011-03-11 20:38:18 +00:00
Jim Grosbach c77dea7f55 ARM VDUPLNfq and VDUPLNfd definitions can just be Pat<>s for VDUPLN32q
and VDUPLN32d, respectively.

llvm-svn: 127486
2011-03-11 20:31:17 +00:00
Jim Grosbach 24fe5e36ea ARM VREV64df and VREV64qf can just be patterns. The instruction is the same
as for VREV64d32 and VREV64q32, respectively.

llvm-svn: 127485
2011-03-11 20:18:05 +00:00
Jim Grosbach 730e1c2c9e Add missing 'return on failure'. Previously we'd crash after emitting
the diagnostic.

llvm-svn: 127480
2011-03-11 19:52:52 +00:00
Jim Grosbach f17b0031f3 Teach TableGen to pre-calculate register enum values when creating the
CodeGenRegister entries. Use this information to more intelligently build
the literal register entires in the DAGISel matcher table. Specifically,
use a single-byte OPC_EmitRegister entry for registers with a value of
less than 256 and OPC_EmitRegister2 entry for registers with a larger value.

rdar://9066491

llvm-svn: 127456
2011-03-11 02:19:02 +00:00
Jim Grosbach eb52c23646 Make the register enum value part of the CodeGenRegister struct.
llvm-svn: 127448
2011-03-11 01:33:54 +00:00
Jim Grosbach f910bf29a9 Trailing whitespace.
llvm-svn: 127447
2011-03-11 01:27:24 +00:00
Jim Grosbach b1ac770fa3 Trailing whitespace.
llvm-svn: 127446
2011-03-11 01:19:05 +00:00
Jim Grosbach d0fc231e13 Tidy up since ARM MOVCCi and MOVCCi16 are now pseudos.
llvm-svn: 127445
2011-03-11 01:16:49 +00:00
Jim Grosbach 62a7b473af Properly pseudo-ize MOVCCr and MOVCCs.
llvm-svn: 127434
2011-03-10 23:56:09 +00:00
Jim Grosbach a186cadcaa Memory barrier instructions don't need special handling in tblgen anymore.
llvm-svn: 127419
2011-03-10 19:05:48 +00:00
Stuart Hastings 8030932290 Stop building PPC parts on OSX. Radar 8637926.
llvm-svn: 127262
2011-03-08 19:28:28 +00:00
NAKAMURA Takumi 8506e4a1d6 Use $(ECHOPATH) to make llvm-lit from llvm-lit.in.
llvm-svn: 127240
2011-03-08 12:25:19 +00:00
Bill Wendling 45f470b86d Don't show commands.
llvm-svn: 127224
2011-03-08 08:34:49 +00:00
Bill Wendling 77ad1dc56d Rename the narrow shift right immediate operands to "shr_imm*" operands. Also
expand the testing of the narrowing shift right instructions.

No functionality change.

llvm-svn: 127193
2011-03-07 23:38:41 +00:00
Bill Wendling e51e464c06 Don't keep the log files around. Just pipe to a log file instead.
llvm-svn: 127155
2011-03-07 07:37:37 +00:00
Jakob Stoklund Olesen 42fc943f21 Revert r127073: "Introduce $(ECHOPATH) to print DOSish path string on MSYS bash for alternative of $(ECHO)."
It broke the llvm-gcc-native-mingw32 buildbot, and we need all of them to be green for the 2.9 branch.

Takumi, please reapply after we branch, preferably with a fix ;-)

llvm-svn: 127107
2011-03-05 18:55:06 +00:00
NAKAMURA Takumi 250c357ce7 utils/lit/lit/TestRunner.py: bash is available with MSYS on Python/W32. Then we can execute "bash tests".
llvm-svn: 127074
2011-03-05 09:46:53 +00:00
NAKAMURA Takumi e9dc4d309a Introduce $(ECHOPATH) to print DOSish path string on MSYS bash for alternative of $(ECHO).
On mingw and python/w32, lit would not be expected to understand MSYS-style path.

llvm-svn: 127073
2011-03-05 09:46:45 +00:00
NAKAMURA Takumi f86dd9e3ec On Windows hosts, Python scripts in test/Scripts did not accept binary files from stdin. The environment variable "PYTHONUNBUFFERED" makes stdin as binary. Thanks to Danil Malyshev!
llvm-svn: 127072
2011-03-05 09:46:36 +00:00
David Greene 9e8963acfd Fix the case where the number of jobs is less than the
number of threads.  In that case make the number of threads
equal to the number of jobs and launch one jobs on each
thread.  This makes things work like make -j.

llvm-svn: 127045
2011-03-04 23:02:52 +00:00
Bob Wilson 6f6d739b6e TableGen should not ignore BX instructions for the ARM disassembler. pr9368.
llvm-svn: 126931
2011-03-03 07:19:52 +00:00
Bob Wilson ec84568904 pr9367: Add missing predicated BLX instructions.
Patch by Jyun-Yan You, with some minor adjustments and a testcase from me.

llvm-svn: 126915
2011-03-03 01:41:01 +00:00
John McCall 8b1ae6417d Teach the clang attribute emitter about InheritableParamAttr.
Intended to be atomic with clang r126828.

llvm-svn: 126827
2011-03-02 04:00:52 +00:00
Oscar Fuentes 98a3c80a3e Fixes warnings emitted by Visual Studio 2010 compiler.
Patch by Erik Olofsson!

llvm-svn: 126796
2011-03-01 23:11:57 +00:00
Jim Grosbach 621818ab1a trailing whitespace.
llvm-svn: 126733
2011-03-01 01:39:05 +00:00
Jim Grosbach 1d479dbc55 Generalize the register matching code in DAGISel a bit.
llvm-svn: 126731
2011-03-01 01:37:19 +00:00
Bill Wendling 3b1459b810 Narrow right shifts need to encode their immediates differently from a normal
shift.

   16-bit: imm6<5:3> = '001', 8 - <imm> is encded in imm6<2:0>
   32-bit: imm6<5:4> = '01',16 - <imm> is encded in imm6<3:0>
   64-bit: imm6<5> = '1', 32 - <imm> is encded in imm6<4:0>

llvm-svn: 126723
2011-03-01 01:00:59 +00:00
NAKAMURA Takumi a14ff2d439 Don't install libUnitTestMain.a. It might be useless without gtest headers.
llvm-svn: 126632
2011-02-28 05:18:07 +00:00
Bill Wendling 31ca7efa04 A new TableGen feature! (Not turned on just yet.)
InstAlias<{alias}, {aliasee}>;

The InstAlias instruction should be able to go from the MCInst to the
{alias}. All of the information is there to match the MCInst with the
{aliasee}. From there, it's a simple matter to emit the {alias}, with the
correct operands from the {aliasee}.

The code this patch generates can be used by the InstPrinter to automatically
print out the alias without having to write special C++ code to handle the
situation.

This is a WIP, and therefore are several limitations. For instance, it cannot
handle AsmOperands at the moment. It also doesn't know what to do when two
{alias}es match the same {aliasee}. (Currently, it just ignores those two cases
and allows the printInstruction method to handle them.)

llvm-svn: 126538
2011-02-26 03:09:12 +00:00
Bob Wilson d2e7b05d8a Removed unnecessary dylibs from Apple builds, with or without "lib" prefix.
Radar 9056686

llvm-svn: 126534
2011-02-26 00:22:17 +00:00
Bob Wilson 15c6f99b02 Add a new "Embedded" makefile target for Apple-style builds.
This one just installs the default build into a different destination directory.

llvm-svn: 126533
2011-02-25 23:42:03 +00:00
Stuart Hastings e6f5613bcc Fix bad comment marker.
llvm-svn: 126525
2011-02-25 22:47:58 +00:00
David Greene c136bc69ce Add some options for building LLVM in different environments:
--force-configure to force running configure before building.

--extra-llvm-config-flags
--extra-llvm-gcc-config-flags
--extra-gcc-config-flags

Pass additional argument to the various configure invocations.

This also eliminates a default build flavor because explicitly
specifying builds could result in build flavors being run repeatedly.

Finally, turn off fortran builds for the moment because install
appears to be broken.

llvm-svn: 126510
2011-02-25 20:51:27 +00:00
Stuart Hastings e167360a45 Omit lto.h from the llvmCore result; henceforth, this will be supplied
by clang.  Radar 9042056.

llvm-svn: 126507
2011-02-25 20:42:39 +00:00
Argyrios Kyrtzidis 28785b6be3 In utils/TableGen/ClangSACheckersEmitter.cpp, set the 'Hidden' bit for checkers.
llvm-svn: 126436
2011-02-24 21:33:49 +00:00
David Greene 5ec8236d9d Fix Builder::execute() to more properly pass the desired environment
to tools.

llvm-svn: 126263
2011-02-22 23:30:45 +00:00
Cameron Zwarich 6785a24c41 Eliminate valgrind warnings from Python on the 32-bit as well.
llvm-svn: 126171
2011-02-22 01:00:10 +00:00
Rafael Espindola e39062199e Implement xgetbv and xsetbv.
Patch by Jai Menon.

llvm-svn: 126165
2011-02-22 00:35:18 +00:00
David Greene 55820a6b7b Add a convenience tool for doing comparison builds of the LLVM
ecosystem.  This is a handy utility for checking changes before
committing them to the repository.

llvm-svn: 126136
2011-02-21 19:23:22 +00:00
Oscar Fuentes 3145e923c1 Put targets on folders, if the IDE supports the feature.
Requires CMake 2.8.3 or newer.

llvm-svn: 126092
2011-02-20 22:06:10 +00:00
Cameron Zwarich 2d43ea968f Try to fix the MC/AsmParser/section.s failure on the llvm-x86_64-linux-vg_leak
bot. I am not sure if this is valid Valgrind exclusion file syntax, but the
Internet seems to think so.

llvm-svn: 126051
2011-02-19 21:44:35 +00:00
Oscar Fuentes 09514f1955 CMake: updated list of tblgen source files.
llvm-svn: 125969
2011-02-18 22:06:23 +00:00
Owen Anderson 4e81890d36 Add FixedLenDecoderEmitter, the skeleton of a new disassembler emitter for fixed-length instruction encodings.
A major part of its (eventual) goal is to support a much cleaner separation between disassembly callbacks
provided by the target and the disassembler emitter itself, i.e. not requiring hardcoding of knowledge in tblgen
like the existing disassembly emitters do.

The hope is that some day this will allow us to replace the existing non-Thumb ARM disassembler and remove
some of the hacks the old one introduced to tblgen.

llvm-svn: 125966
2011-02-18 21:51:29 +00:00
Joerg Sonnenberger 07cbde967f Check that MnemonicAlias doesn't map back to the same string.
llvm-svn: 125792
2011-02-17 23:22:19 +00:00
NAKAMURA Takumi 5850225f52 lit/TestingConfig.py: Add the environment variable PRINTF_EXPONENT_DIGITS as workaround [PR6745] for mingw's tests. Danil Malyshev suggested this.
FIXME: It does not improve MSVC's issue.

[Danil Malyshev] Defining PRINTF_EXPONENT_DIGITS env is the suggested way to make MinGW ANSI/POSIX compatible. This is not only about the case we are discussing, but in general, I'd like to have explicitly defined compatibility mode for all the tests running on MinGW.

llvm-svn: 125725
2011-02-17 05:56:41 +00:00
Alexis Hunt e2d77b8142 Add serialization for Expr* arguments for attributes to clang tablegen files.
Patch thanks to Zach Anderson.

llvm-svn: 125721
2011-02-17 03:30:09 +00:00
Argyrios Kyrtzidis 6254f29d22 When tablegen'ing the clang analyzer checkers:
-Use the tablegen class name for the checker class name.
-Mark checker packages as hidden/not hidden.

llvm-svn: 125558
2011-02-15 07:42:16 +00:00
Argyrios Kyrtzidis 485969638f Add the ClangSACheckersEmitter tablegen backend which will be used for the clang static analyzer.
llvm-svn: 125493
2011-02-14 17:58:52 +00:00
Bruno Cardoso Lopes 90d1dfe4c6 Fix encoding and add parsing support for the arm/thumb CPS instruction:
- Add custom operand matching for imod and iflags.
- Rename SplitMnemonicAndCC to SplitMnemonic since it splits more than CC
  from mnemonic.
- While adding ".w" as an operand, don't change "Head" to avoid passing the
  wrong mnemonic to ParseOperand.
- Add asm parser tests.
- Add disassembler tests just to make sure it can catch all cps versions.

llvm-svn: 125489
2011-02-14 13:09:44 +00:00
Argyrios Kyrtzidis 9f5055f037 Wrap the struct in an anonymous namespace.
llvm-svn: 125452
2011-02-13 07:51:19 +00:00
Jim Grosbach 861e49ce3b AsmMatcher custom operand parser failure enhancements.
Teach the AsmMatcher handling to distinguish between an error custom-parsing
an operand and a failure to match. The former should propogate the error
upwards, while the latter should continue attempting to parse with
alternative matchers.

Update the ARM asm parser accordingly.

llvm-svn: 125426
2011-02-12 01:34:40 +00:00
Jim Grosbach 860a84d65a Tidy out asm matcher .inc output.
llvm-svn: 125408
2011-02-11 21:31:55 +00:00
NAKAMURA Takumi 0117c36184 lit/TestFormats.py: Unittests may be found with suffix .exe also on Cygwin.
llvm-svn: 125273
2011-02-10 09:11:57 +00:00
NAKAMURA Takumi 32e9c83870 lit/Util.py: On Cygwin, 'PATHEXT' may exist but it should not be used.
llvm-svn: 125272
2011-02-10 09:11:48 +00:00
Bill Wendling 5f3a39e79a Don't return before calling the post-processing function(s).
llvm-svn: 125256
2011-02-10 01:28:26 +00:00
Jim Grosbach 6e2e29bd11 Do AsmMatcher operand classification per-opcode.
When matching operands for a candidate opcode match in the auto-generated
AsmMatcher, check each operand against the expected operand match class.
Previously, operands were classified independently of the opcode being
handled, which led to difficulties when operand match classes were
more complicated than simple subclass relationships.

llvm-svn: 125245
2011-02-10 00:08:28 +00:00