Commit Graph

3482 Commits

Author SHA1 Message Date
Jim Grosbach 2392c53e73 Thumb2 assembly parsing and encoding for LDRBT.
llvm-svn: 139267
2011-09-07 23:39:14 +00:00
Jim Grosbach 5bfa8bab06 Thumb2 parsing and encoding for LDR(immediate).
The immediate offset of the non-writeback i8 form (encoding T4) allows
negative offsets only. The positive offset form of the encoding is the
LDRT instruction. Immediate offsets in the range [0,255] use encoding T3
instead.

llvm-svn: 139254
2011-09-07 20:58:57 +00:00
James Molloy 8067df9503 Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler.
llvm-svn: 139250
2011-09-07 19:42:28 +00:00
Joerg Sonnenberger 3d76f312b2 Dependency should be on the output file name, not the dependency file
name.

llvm-svn: 139220
2011-09-07 02:12:03 +00:00
Benjamin Kramer 09ade9bb8b valgrind: Suppress glibc's optiized strcasecmp harder.
llvm-svn: 139084
2011-09-03 17:59:31 +00:00
Andrew Trick 67ba2403e8 Attempt to silence known valgrind errors.
llvm-svn: 139048
2011-09-02 22:59:34 +00:00
David Greene 09d153eb12 Make RecordVal Name an Init
Store a RecordVal's name as an Init to allow class-qualified Record
members to reference Records that have Init names.  We'll use this to
provide more programmability in how we name defs and their associated
members.

llvm-svn: 139031
2011-09-02 20:12:07 +00:00
Kevin Enderby 54e09b4799 Fix the disassembly of the X86 "crc32w %ax, %eax" instruction. Bug 10702.
llvm-svn: 139014
2011-09-02 18:03:03 +00:00
Craig Topper 94ce535647 Make IC_VEX* not inherit from IC_*. Prevents instructions with no VEX form from disassembling to their non-VEX form. Also prevents weak filter collisons that were keeping valid VEX instructions from decoding properly. Make VEX_L* not inherit from VEX_* because the VEX.L bit always important. This stops packed int VEX encodings from being disassembled when specified with VEX.L=1. Fixes PR10831 and PR10806.
llvm-svn: 138997
2011-09-02 04:17:54 +00:00
James Molloy db4ce60328 Fix up r137380 based on post-commit review by Jim Grosbach.
llvm-svn: 138948
2011-09-01 18:02:14 +00:00
NAKAMURA Takumi 93f3082118 lit: Normalize pathsep slashes also on %T.
On Python-w32 with mingw msys bash, %T was replaced to "x:\foo\bar...". msys bash cannot handle DOSish paths.

llvm-svn: 138852
2011-08-31 03:56:17 +00:00
Evan Cheng e6fba77971 Follow up to r138791.
Add a instruction flag: hasPostISelHook which tells the pre-RA scheduler to
call a target hook to adjust the instruction. For ARM, this is used to
adjust instructions which may be setting the 's' flag. ADC, SBC, RSB, and RSC
instructions have implicit def of CPSR (required since it now uses CPSR physical
register dependency rather than "glue"). If the carry flag is used, then the
target hook will *fill in* the optional operand with CPSR. Otherwise, the hook
will remove the CPSR implicit def from the MachineInstr.

llvm-svn: 138810
2011-08-30 19:09:48 +00:00
Andrew Trick d74c19449e Lit option for ignoring stderr output.
This is useful for testing a build a temporarily hand instrumented
build.
Patch by arrowdodger!

llvm-svn: 138804
2011-08-30 17:42:33 +00:00
Craig Topper 4f2fba1108 Add vvvv support to disassembling of instructions with MRMDestMem and MRMDestReg form. Needed to support mem dest form of vmaskmovps/d. Fixes PR10807.
llvm-svn: 138795
2011-08-30 07:09:35 +00:00
Kevin Enderby 7e2489a7c9 Fix the disassembly of the X86 crc32 instruction. Bug 10702 and rdar://8795217
llvm-svn: 138771
2011-08-29 22:06:28 +00:00
Andrew Trick d22f9b395b Reverted r138652, valgrind doesn't understand obj:*/tblgen.
llvm-svn: 138703
2011-08-27 06:17:30 +00:00
Owen Anderson b205c029a4 Improve encoding support for BLX with immediat eoperands, and fix a BLX decoding bug this uncovered.
llvm-svn: 138675
2011-08-26 23:32:08 +00:00
Andrew Trick 28dc5abd05 valgrind: Always suppress tblgen leaks.
I'll clean up the rest of the XFAIL: vg_leak lines if this works.

llvm-svn: 138652
2011-08-26 20:41:20 +00:00
Douglas Gregor 37e94d06ba lit: Add %T as a replacement for the output directory
llvm-svn: 138640
2011-08-26 19:05:18 +00:00
Craig Topper 76e3e0b554 Give ATTR_VEX higher priority when generating the disassembler context table. Fixes disassembling of VEX instructions with 'pp'=00. Fixes subset of PR10678.
llvm-svn: 138552
2011-08-25 07:42:00 +00:00
Jim Grosbach 0a0b3071df Thumb parsing and encoding support for ADD SP instructions.
Fix the test FIXME and add parsing support for the ADD (SP plus immediate)
and ADD (SP plus register) instruction forms.

llvm-svn: 138488
2011-08-24 21:22:15 +00:00
Jim Grosbach 1b8457a84c Thumb1 ADD/SUB SP instructions are predicable in Thumb2 mode.
Add the predicate operand to the instructions. Update the back end
accordingly where the instructions are used. Restrict the SP operands
to actually only be SP, as otherwise these break assembly parsing for the
normal instruction variants.

llvm-svn: 138445
2011-08-24 17:46:13 +00:00
Caitlin Sadowski ffa5a909b4 Thread safety: Adding in an option for variadic expr* array of arguments
llvm-svn: 138351
2011-08-23 18:49:23 +00:00
Eric Christopher c50ea3beaf Fix fpimmm->fpimm typo.
Patch by Micah Villmow!

llvm-svn: 138330
2011-08-23 15:42:35 +00:00
NAKAMURA Takumi 9f1761c3e0 utils/lit/lit/TestingConfig.py: Pass TEMP and TMP to tests on Win32 hosts.
Win32 GetTempPath() tends to pick up %WINDIR% when neither TEMP nor TMP was found. %WINDIR% should not be treated writable on recent Windows OS.

llvm-svn: 138192
2011-08-20 05:44:58 +00:00
NAKAMURA Takumi 9b4ae4bb1c utils/lit/lit/TestingConfig.py: Split out environment vars for Win32.
llvm-svn: 138191
2011-08-20 05:44:52 +00:00
Jim Grosbach a7b2d444b6 Allow non zero_reg explicit values for OptionalDefOperands in aliases.
llvm-svn: 138073
2011-08-19 20:33:06 +00:00
Jim Grosbach b527f4498a Tidy up. Formatting.
llvm-svn: 138067
2011-08-19 19:53:51 +00:00
Owen Anderson a4043c4b32 Allow the MCDisassembler to return a "soft fail" status code, indicating an instruction that is disassemblable, but invalid. Only used for ARM UNPREDICTABLE instructions at the moment.
Patch by James Molloy.

llvm-svn: 137830
2011-08-17 17:44:15 +00:00
Bruno Cardoso Lopes 54cd240d0f Update uwtable vim color!
llvm-svn: 137806
2011-08-17 02:29:07 +00:00
Jim Grosbach d152e2cc00 Prefer diagnostics from target predicate in asm matcher.
llvm-svn: 137742
2011-08-16 20:12:35 +00:00
Bob Wilson aecb7501ad Avoid evaluating Neon macro arguments more than once by disabling type checks.
It turns out that the use of "__extension__" in these macros was disabling
the expected "incompatible pointer" warnings, so these type checks were not
doing anything anyway.  They introduced a serious bug by evaluating some
macro arguments twice, which is a big problem for arguments with side effects.
I'll have to find another way to get the right type checking.  Radar 9947657.

llvm-svn: 137680
2011-08-15 23:22:56 +00:00
Jim Grosbach 120a96a721 MCTargetAsmParser target match predicate support.
Allow a target assembly parser to do context sensitive constraint checking
on a potential instruction match. This will be used, for example, to handle
Thumb2 IT block parsing.

llvm-svn: 137675
2011-08-15 23:03:29 +00:00
Jim Grosbach b59abbd4fd Move MatchResultTy enum into base class definition.
No need for it to be redefined as part of every derived target asm parser
class.

llvm-svn: 137649
2011-08-15 20:53:08 +00:00
David Greene 50c0912492 Make Record Name an Init
Use an Init (ultimately a StringInit) to represent the Record name.
This allows the name to be composed by standard TableGen operators.
This will enable us to get rid of the ugly #NAME# hack processing and
naturally replace it with operators.  It also increases flexibility
and power of the TableGen language by allowing record identifiers to
be computed dynamically.

llvm-svn: 137232
2011-08-10 18:27:46 +00:00
David Greene 4a36d144e2 Add getAsUnquotedString
Add a method to return an Init as an unquoted string.  This primarily
affects StringInit where we return the value without surrounding it
with quotes.

This is in preparation for removing the ugly #NAME# hack and replacing
it with standard TabelGen operators.

llvm-svn: 137231
2011-08-10 18:27:45 +00:00
Eric Christopher 266141aceb Update comment.
llvm-svn: 137188
2011-08-10 00:02:39 +00:00
Eric Christopher 69adb3f980 clang is the new black.
llvm-svn: 137187
2011-08-09 23:59:05 +00:00
Owen Anderson ecc4ffc941 Fix an oversight in the FixedLenDecoderEmitter where we weren't correctly checking the success result of custom decoder hooks on singleton decodings.
llvm-svn: 137171
2011-08-09 23:05:23 +00:00
Owen Anderson 042619f97d Create a new register class for the set of all GPRs except the PC. Use it to tighten our decoding of BFI.
llvm-svn: 137168
2011-08-09 22:48:45 +00:00
Owen Anderson e0152a73c2 Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter.
This new disassembler can correctly decode all the testcases that the old one did, though
some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in
operand checking as the old one was.

llvm-svn: 137144
2011-08-09 20:55:18 +00:00
Owen Anderson c40303885b Fix encodings for Thumb ASR and LSR immediate operands. They encode the range 1-32, with 32 encoded as 0.
llvm-svn: 137062
2011-08-08 20:42:17 +00:00
Owen Anderson ce5190321e LDCL_POST and STCL_POST need one's-complement offsets, rather than two's complement offsets. Add an appropriate immediate type for them.
llvm-svn: 136896
2011-08-04 18:24:14 +00:00
Jim Grosbach d359571120 ARM refactoring assembly parsing of memory address operands.
Memory operand parsing is a bit haphazzard at the moment, in no small part
due to the even more haphazzard representations of memory operands in the .td
files. Start cleaning that all up, at least a bit.

The addressing modes in the .td files will be being simplified to not be
so monolithic, especially with regards to immediate vs. register offsets
and post-indexed addressing. addrmode3 is on its way with this patch, for
example.

This patch is foundational to enable going back to smaller incremental patches
for the individual memory referencing instructions themselves. It does just
enough to get the basics in place and handle the "make check" regression tests
we already have.

Follow-up work will be fleshing out the details and adding more robust test
cases for the individual instructions, starting with ARM mode and moving from
there into Thumb and Thumb2.

llvm-svn: 136845
2011-08-03 23:50:40 +00:00
Jim Grosbach 9ec152b6bf ARM: rename addrmode7 to addr_offset_none.
Use a more descriptive name so the code is more self-documenting.

llvm-svn: 136704
2011-08-02 18:07:32 +00:00
Owen Anderson 3022d6711d Make the FixedLengthDecoderEmitter smart enough to autogenerate decoders for encodings like "let Inst{11-7} = foo;", where the RHS has no bitwidth specifiers.
llvm-svn: 136660
2011-08-01 22:45:43 +00:00
Owen Anderson faee2cf9ff The FixedLenDecoder needs to gracefully handle failing per-instruction decoder hooks in addition to per-operand decoder hooks.
llvm-svn: 136645
2011-08-01 20:06:49 +00:00
Owen Anderson 37ef826040 Enhance the fixed length disassembler to better handle operand decoding failures.
llvm-svn: 136635
2011-08-01 18:44:37 +00:00
Owen Anderson e08f5b5b37 Correctly handle scattered operands where the bits of the operand are contiguous, but out of order.
llvm-svn: 136534
2011-07-29 23:01:18 +00:00
David Greene af8ee2cdee Unconstify Inits
Remove const qualifiers from Init references, per Chris' request.

llvm-svn: 136531
2011-07-29 22:43:06 +00:00