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57 Commits

Author SHA1 Message Date
Owen Anderson b75772201f Fix incorrect disassembly test. 
llvm-svn: 140423
 2011-09-23 22:05:54 +00:00
Owen Anderson f52c68f0ca Print out immediate offset versions of PC-relative load/store instructions as [pc, #123] rather than simply #123. 
llvm-svn: 140283
 2011-09-21 23:44:46 +00:00
Owen Anderson 18d17aa6b7 Create Thumb2 versions of STC/LDC, and reenable the relevant tests. 
llvm-svn: 139256
 2011-09-07 21:10:42 +00:00
James Molloy 8067df9503 Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler. 
llvm-svn: 139250
 2011-09-07 19:42:28 +00:00
Jim Grosbach 5d5f4862eb Update test for 139243 
llvm-svn: 139244
 2011-09-07 18:40:06 +00:00
Owen Anderson 924bcfc92f Fix decoding of Thumb2 prefetch instructions, which account for all the remaining Thumb2 decoding failures found by randomized testing so far. 
llvm-svn: 138341
 2011-08-23 17:51:38 +00:00
Owen Anderson 041dba6dec Fix two more instances of mis-matched operand names breaking disassembly. Found by randomized testing. 
llvm-svn: 138337
 2011-08-23 17:37:32 +00:00
Owen Anderson 1346d79b4b t2SMLAD is a four-register instruction, not a three-register one. 
llvm-svn: 138301
 2011-08-22 23:31:45 +00:00
Owen Anderson f94b7b7d57 Correct operand naming of t2USAT16 to allow proper decoding. 
llvm-svn: 138300
 2011-08-22 23:27:47 +00:00
Owen Anderson 5e9989a920 Match operand naming to allow correct decoding of t2LDRSH_POST. 
llvm-svn: 138298
 2011-08-22 23:22:05 +00:00
Owen Anderson a743409ec8 Provide a correct decoder hook for Thumb2 shifted registers. Found by randomized testing. 
llvm-svn: 138292
 2011-08-22 23:10:16 +00:00
Jim Grosbach 90103ccc05 Thumb assembly parsing and encoding for LDM instruction. 
Fix base register type and canonicallize to the "ldm" spelling rather than
"ldmia." Add diagnostics for incorrect writeback token and out-of-range
registers.

llvm-svn: 137986
 2011-08-18 21:50:53 +00:00
Owen Anderson 944f4923a4 Add a test for Thumb1 LDRSH decoding. 
llvm-svn: 137645
 2011-08-15 20:15:43 +00:00
Owen Anderson 3157f2eebe Fix decoding LDRSB and LDRSH in Thumb1 mode. Patch by James Molloy. 
llvm-svn: 137636
 2011-08-15 19:00:06 +00:00
Owen Anderson c86a5bd219 Add initial support for decoding NEON instructions in Thumb2 mode. 
llvm-svn: 137236
 2011-08-10 19:01:10 +00:00
Jim Grosbach d25c2cdad7 Tweak ARM assembly parsing and printing of MSR instruction. 
The system register spec should be case insensitive. The preferred form for
output with mask values of 4, 8, and 12 references APSR rather than CPSR.
Update and tidy up tests accordingly.

llvm-svn: 135532
 2011-07-19 22:45:10 +00:00
Johnny Chen 071634612d Disassembly of tBcc was wrongly adding 4 to the SignExtend'ed imm8:'0' immediate operand. 
llvm-svn: 131565
 2011-05-18 20:32:41 +00:00
Johnny Chen c3c7001844 Add tests for A8.6.110 NOP. 
llvm-svn: 130345
 2011-04-27 23:29:21 +00:00
Johnny Chen 57c892860e Disassembly of A8.6.59 LDR (literal) Encoding T1 (16-bit thumb instruction) should 
print out ldr, not ldr.n.

rdar://problem/9267772

llvm-svn: 130008
 2011-04-22 19:12:43 +00:00
Johnny Chen 48592ee5af Thumb2 BFC was insufficiently encoded. 
rdar://problem/9292717

llvm-svn: 129619
 2011-04-15 22:52:15 +00:00
Johnny Chen 4251b151b1 Add sanity checkings for Thumb2 Load/Store Register Exclusive family of operations. 
llvm-svn: 129531
 2011-04-14 19:13:28 +00:00
Johnny Chen d0fb04f437 Thumb disassembler did not handle tBRIND (indirect branch) properly. 
rdar://problem/9280370

llvm-svn: 129480
 2011-04-13 21:59:01 +00:00
Johnny Chen b6a37bff21 Check for unallocated instruction encodings when disassembling Thumb Branch instructions (tBcc and t2Bcc). 
rdar://problem/9280470

llvm-svn: 129471
 2011-04-13 21:35:49 +00:00
Johnny Chen 0d306a7840 Fix a bug where for t2MOVCCi disassembly, the TIED_TO register operand was not properly handled. 
rdar://problem/9276427

llvm-svn: 129456
 2011-04-13 17:51:02 +00:00
Johnny Chen 960eef3db3 The Thumb2 RFE instructions need to have their second halfword fully specified. 
In addition, the base register is not rGPR, but GPR with th exception that:

    if n == 15 then UNPREDICTABLE

rdar://problem/9273836

llvm-svn: 129391
 2011-04-12 21:41:51 +00:00
Johnny Chen ab86a519f8 The Thumb2 Ld, St, and Preload instructions with the i12 forms should have its Inst{23} 
be specified as '1' (add = TRUE).

Also add a utility function for Thumb2.

llvm-svn: 129377
 2011-04-12 18:48:00 +00:00
Johnny Chen f130b7f0f5 Add one test case (svc). 
llvm-svn: 129327
 2011-04-12 00:21:48 +00:00
Johnny Chen dc8bf9ec08 Thumb disassembler was erroneously rejecting "blx sp" instruction. 
rdar://problem/9267838

llvm-svn: 129320
 2011-04-11 23:33:30 +00:00
Johnny Chen f79d5365de Fix the bug where the immediate shift amount for Thumb logical shift instructions are incorrectly disassembled. 
rdar://problem/9266265

llvm-svn: 129298
 2011-04-11 21:14:35 +00:00
Johnny Chen 875e0e4626 Sanity check the option operand for DMB/DSB. 
PR9648
rdar://problem/9257634

llvm-svn: 129146
 2011-04-08 19:18:07 +00:00
Johnny Chen 2ac486e387 A8.6.92 MCR (Encoding A1): if coproc == '101x' then SEE "Advanced SIMD and VFP" 
Since these "Advanced SIMD and VFP" instructions have more specfic encoding bits
specified, if coproc == 10 or 11, we should reject the insn as invalid.

rdar://problem/9239922
rdar://problem/9239596

llvm-svn: 129027
 2011-04-06 20:49:02 +00:00
Johnny Chen 151582492d ARM disassembler should flag (rGPRRegClassID, r13|r15) as an error. 
llvm-svn: 128913
 2011-04-05 19:42:11 +00:00
Johnny Chen 0ae2501fd2 Add a test case for thumb stc2 instruction. 
llvm-svn: 128517
 2011-03-30 01:02:06 +00:00
Johnny Chen 923f3dac01 Fixed the t2PLD and friends disassembly and add two test cases. 
llvm-svn: 128322
 2011-03-26 01:32:48 +00:00
Johnny Chen 1572bf40b4 Add test for A8.6.246 UMULL to both arm-tests.txt amd thumb-tests.txt. 
llvm-svn: 128306
 2011-03-25 23:02:58 +00:00
Johnny Chen 6e31bf1f6f Add two test cases t2SMLABT and t2SMMULR for DisassembleThumb2Mul(). 
llvm-svn: 128305
 2011-03-25 22:43:28 +00:00
Johnny Chen 49316e40ba Fix DisassembleThumb2DPReg()'s handling of RegClass. Cannot hardcode GPRRegClassID. 
Also add some test cases.

rdar://problem/9189829

llvm-svn: 128304
 2011-03-25 22:19:07 +00:00
Johnny Chen aaf2c69400 DisassembleThumb2LdSt() did not handle t2LDRs correctly with respect to RegClass. Add two test cases. 
rdar://problem/9182892

llvm-svn: 128299
 2011-03-25 19:35:37 +00:00
Johnny Chen 4fd2194638 A8.6.226 TBB, TBH: 
Add two test cases.

llvm-svn: 128295
 2011-03-25 18:40:21 +00:00
Johnny Chen b35548f44d Modify DisassembleThumb2LdStEx() to be more robust/correct in light of recent change to 
t2LDREX/t2STREX instructions.  Add two test cases.

llvm-svn: 128293
 2011-03-25 18:29:49 +00:00
Johnny Chen a52143bff3 Modify the wrong logic in the assert of DisassembleThumb2LdStDual() (the register classes were changed), 
modify the comment to be up-to-date, and add a test case for A8.6.66 LDRD (immediate) Encoding T1.

llvm-svn: 128252
 2011-03-25 01:09:48 +00:00
Johnny Chen 72f4a95144 delegate the disassembly of t2ADR to the more generic t2ADDri12/t2SUBri12 instructions, and add a test case for that. 
llvm-svn: 128249
 2011-03-25 00:17:42 +00:00
Johnny Chen ceef55466a The opcode names ("tLDM", "tLDM_UPD") used for conflict resolution have been stale since 
the change to ("tLDMIA", "tLDMIA_UPD").  Update the conflict resolution code and add
test cases for that.

llvm-svn: 128247
 2011-03-24 23:42:31 +00:00
Johnny Chen 73193f2475 The ARM disassembler was confused with the 16-bit tSTMIA instruction. 
According to A8.6.189 STM/STMIA/STMEA (Encoding T1), there's only tSTMIA_UPD available.
Ignore tSTMIA for the decoder emitter and add a test case for that.

llvm-svn: 128246
 2011-03-24 23:21:14 +00:00
Johnny Chen 6469ca0c33 T2 Load/Store Multiple: 
These instructions were changed to not embed the addressing mode within the MC instructions
We also need to update the corresponding assert stmt.  Also add a test case.

llvm-svn: 128240
 2011-03-24 21:36:56 +00:00
Johnny Chen 122a6304ef Add disassembly test cases for: 
A8.6.292 VCMPE

llvm-svn: 128120
 2011-03-22 23:08:56 +00:00
Johnny Chen 230268261b A8.6.399 VSTM: 
VFP Load/Store Multiple Instructions used to embed the IA/DB addressing mode within the
MC instruction; that has been changed so that now, for example, VSTMDDB_UPD and VSTMDIA_UPD
are two instructions.  Update the ARMDisassemblerCore.cpp's DisassembleVFPLdStMulFrm()
to reflect the change.

Also add a test case.

llvm-svn: 128103
 2011-03-22 20:00:10 +00:00
Johnny Chen e387f8a5e9 The disassembler for Thumb was wrongly adding 4 to the computed imm32 offset. 
Remove the offending logic and update the test cases.

llvm-svn: 127843
 2011-03-18 00:38:03 +00:00
Johnny Chen 221a014ea3 It used to be that t_addrmode_s4 was used for both: 
o A8.6.195 STR (register) -- Encoding T1
o A8.6.193 STR (immediate, Thumb) -- Encoding T1

It has been changed so that now they use different addressing modes
and thus different MC representation (Operand Infos).  Modify the
disassembler to reflect the change, and add relevant tests.

llvm-svn: 127833
 2011-03-17 22:04:05 +00:00
Kevin Enderby 58775fea6f Fix the arm's disassembler for blx that was building an MCInst without the 
needed two predicate operands before the imm operand.

llvm-svn: 126662
 2011-02-28 18:46:31 +00:00