Commit Graph

498 Commits

Author SHA1 Message Date
Daniel Dunbar 38a22bffdc Replace std::iostreams with raw_ostream in TableGen.
- Sorry, I can't help myself.

 - No intended functionality change.

llvm-svn: 74742
2009-07-03 00:10:29 +00:00
Dale Johannesen 5234d3795f Revert 72707 and 72709, for the moment.
llvm-svn: 72712
2009-06-02 03:12:52 +00:00
Dale Johannesen 0b8ca79253 Make the implicit inputs and outputs of target-independent
ADDC/ADDE use MVT::i1 (later, whatever it gets legalized to)
instead of MVT::Flag.  Remove CARRY_FALSE in favor of 0; adjust
all target-independent code to use this format.

Most targets will still produce a Flag-setting target-dependent
version when selection is done.  X86 is converted to use i32
instead, which means TableGen needs to produce different code
in xxxGenDAGISel.inc.  This keys off the new supportsHasI1 bit
in xxxInstrInfo, currently set only for X86; in principle this
is temporary and should go away when all other targets have
been converted.  All relevant X86 instruction patterns are
modified to represent setting and using EFLAGS explicitly.  The
same can be done on other targets.

The immediate behavior change is that an ADC/ADD pair are no
longer tightly coupled in the X86 scheduler; they can be
separated by instructions that don't clobber the flags (MOV).
I will soon add some peephole optimizations based on using
other instructions that set the flags to feed into ADC.

llvm-svn: 72707
2009-06-01 23:27:20 +00:00
Dale Johannesen 69ee5e4cfe Slightly improve generated code in a degenerate case.
Should remove a warning from MSVC.

llvm-svn: 71603
2009-05-12 22:32:29 +00:00
Dan Gohman cfd6941cf9 Quotes are used for including llvm headers, rather than angles.
llvm-svn: 70879
2009-05-04 17:09:51 +00:00
Bill Wendling 026e5d7667 Instead of passing in an unsigned value for the optimization level, use an enum,
which better identifies what the optimization is doing. And is more flexible for
future uses.

llvm-svn: 70440
2009-04-29 23:29:43 +00:00
Bill Wendling 084669a1c9 Second attempt:
Massive check in. This changes the "-fast" flag to "-O#" in llc. If you want to
use the old behavior, the flag is -O0. This change allows for finer-grained
control over which optimizations are run at different -O levels.

Most of this work was pretty mechanical. The majority of the fixes came from
verifying that a "fast" variable wasn't used anymore. The JIT still uses a
"Fast" flag. I'll change the JIT with a follow-up patch.

llvm-svn: 70343
2009-04-29 00:15:41 +00:00
Bill Wendling 56f2987a87 r70270 isn't ready yet. Back this out. Sorry for the noise.
llvm-svn: 70275
2009-04-28 01:04:53 +00:00
Bill Wendling d0ae15946c Massive check in. This changes the "-fast" flag to "-O#" in llc. If you want to
use the old behavior, the flag is -O0. This change allows for finer-grained
control over which optimizations are run at different -O levels.

Most of this work was pretty mechanical. The majority of the fixes came from
verifying that a "fast" variable wasn't used anymore. The JIT still uses a
"Fast" flag. I'm not 100% sure if it's necessary to change it there...

llvm-svn: 70270
2009-04-28 00:21:31 +00:00
Dan Gohman 60a446ab02 Add a new TargetInstrInfo MachineInstr opcode, COPY_TO_SUBCLASS.
This will be used to replace things like X86's MOV32to32_.

Enhance ScheduleDAGSDNodesEmit to be more flexible and robust
in the presense of subregister superclasses and subclasses. It
can now cope with the definition of a virtual register being in
a subclass of a use.

Re-introduce the code for recording register superreg classes and
subreg classes. This is needed because when subreg extracts and
inserts get coalesced away, the virtual registers are left in
the correct subclass.

llvm-svn: 68961
2009-04-13 15:38:05 +00:00
Dan Gohman b425feb2aa Delete ISD::INSERT_SUBREG and ISD::EXTRACT_SUBREG, which are unused.
Note that these are distinct from TargetInstrInfo::INSERT_SUBREG
and TargetInstrInfo::EXTRACT_SUBREG, which are used.

llvm-svn: 68355
2009-04-03 00:25:26 +00:00
Jim Grosbach 975c1cb41a fix a few spelling errors and typos
llvm-svn: 67758
2009-03-26 16:17:51 +00:00
Jim Grosbach 4bae1ac5e8 Use 'bool' for FoundRC
llvm-svn: 67750
2009-03-26 14:45:34 +00:00
Jim Grosbach 292ea55130 Modify getRegisterValueType() to allow for a register being in mutliple
register classes. Before, MVT::Other would be returned anytime a reg was
in multiple register classes. Now, MVT::Other is only returned if the types
for those register classes differ.

llvm-svn: 67714
2009-03-25 23:28:33 +00:00
Dale Johannesen 9f3f72f144 Get rid of one more non-DebugLoc getNode and
its corresponding getTargetNode.  Lots of
caller changes.

llvm-svn: 63904
2009-02-06 01:31:28 +00:00
Dale Johannesen f80493bbfd Remove a non-DebugLoc version of getNode.
llvm-svn: 63889
2009-02-05 22:07:54 +00:00
Dale Johannesen f08a47bb70 Remove non-DebugLoc forms of CopyToReg and CopyFromReg.
Adjust callers.

llvm-svn: 63789
2009-02-04 23:02:30 +00:00
Bill Wendling 33dddf3235 Explain why this is here.
llvm-svn: 63342
2009-01-29 23:19:43 +00:00
Bill Wendling 50338007b9 - Add DebugLoc to getTargetNode().
- Modify TableGen to add the DebugLoc when calling getTargetNode.

(The light-weight wrappers are only temporary. The non-DebugLoc version will be
removed once the whole debug info stuff is finished with.)

llvm-svn: 63273
2009-01-29 05:27:31 +00:00
Dan Gohman 84f0165273 Move the code that starts printing the Select_* functions
after the code that sorts the patterns. This doesn't
affect the output, but it makes the code a little easier
to follow.

llvm-svn: 63265
2009-01-29 01:37:18 +00:00
Dan Gohman 3289983d69 Avoid triggering an assertion failure when an instruction pattern
is a leaf node. Patch by Brandner!

llvm-svn: 62361
2009-01-16 21:30:55 +00:00
Dan Gohman 3e35fe8968 Add support for instructions with multiple ComplexPatterns, by
adding more information to the temporary variables names so that
they don't conflict.

llvm-svn: 62296
2009-01-16 02:05:52 +00:00
Dan Gohman 49c42d5f57 Delete an unused variable and simplify the code.
llvm-svn: 61732
2009-01-05 19:31:28 +00:00
Dan Gohman f1fb65c747 Use dyn_cast intead of isa + cast in the generated DAGISel code. This
reduces the amount of code slightly when assertions are enabled.

llvm-svn: 61249
2008-12-19 18:13:39 +00:00
Dan Gohman ae3ba45eb2 Add a sanity-check to tablegen to catch the case where isSimpleLoad
is set but mayLoad is not set. Fix all the problems this turned up.

Change code to not use isSimpleLoad instead of mayLoad unless it
really wants isSimpleLoad.

llvm-svn: 60459
2008-12-03 02:30:17 +00:00
Evan Cheng 83bdb38965 On x86 favors folding short immediate into some arithmetic operations (e.g. add, and, xor, etc.) because materializing an immediate in a register is expensive in turns of code size.
e.g.
movl 4(%esp), %eax
addl $4, %eax

is 2 bytes shorter than

movl $4, %eax
addl 4(%esp), %eax

llvm-svn: 60139
2008-11-27 00:49:46 +00:00
Dan Gohman ce2417f4e1 Use an assert to check that SelectCode isn't called on
nodes that are already selected.

llvm-svn: 58763
2008-11-05 18:30:52 +00:00
Dan Gohman f14b77ebf1 Eliminate the ISel priority queue, which used the topological order for a
priority function. Instead, just iterate over the AllNodes list, which is
already in topological order. This eliminates a fair amount of bookkeeping,
and speeds up the isel phase by about 15% on many testcases.

The impact on most targets is that AddToISelQueue calls can be simply removed.

In the x86 target, there are two additional notable changes.

The rule-bending AND+SHIFT optimization in MatchAddress that creates new
pre-isel nodes during isel is now a little more verbose, but more robust.
Instead of either creating an invalid DAG or creating an invalid topological
sort, as it has historically done, it can now just insert the new nodes into
the node list at a position where they will be consistent with the topological
ordering.

Also, the address-matching code has logic that checked to see if a node was
"already selected". However, when a node is selected, it has all its uses
taken away via ReplaceAllUsesWith or equivalent, so it won't recieve any
further visits from MatchAddress. This code is now removed.

llvm-svn: 58748
2008-11-05 04:14:16 +00:00
David Greene ce2a938186 Have TableGen emit setSubgraphColor calls under control of a -gen-debug
flag.  Then in a debugger developers can set breakpoints at these calls
to see waht is about to be selected and what the resulting subgraph
looks like.  This really helps when debugging instruction selection.

llvm-svn: 58278
2008-10-27 21:56:29 +00:00
Dan Gohman 10549c29a8 Use INT64_C to emit constant values, to avoid problems with
constants that don't fit in an int. This fixes
"this decimal constant is unsigned only in ISO C90"
warnings.

llvm-svn: 57668
2008-10-17 04:40:39 +00:00
Dan Gohman ca0546facc Fun x86 encoding tricks: when adding an immediate value of 128,
use a SUB instruction instead of an ADD, because -128 can be
encoded in an 8-bit signed immediate field, while +128 can't be.
This avoids the need for a 32-bit immediate field in this case.

A similar optimization applies to 64-bit adds with 0x80000000,
with the 32-bit signed immediate field.

To support this, teach tablegen how to handle 64-bit constants.

llvm-svn: 57663
2008-10-17 01:33:43 +00:00
Dan Gohman 6e979020cd Add support for having multiple predicates on a TreePatternNode.
This will allow predicates to be composed, which will allow the
predicate definitions to become less redundant, and eventually
will allow DAGISelEmitter.cpp to emit less redundant code.

llvm-svn: 57562
2008-10-15 06:17:21 +00:00
Dan Gohman 843fe14fab Move the code that handles DAGISel error conditions into
helper functions instead of duplicating it inline each time
it is needed. This eliminates a few hundred or so copies
of this code in each target.

llvm-svn: 56759
2008-09-27 23:53:14 +00:00
Dan Gohman 6e0548336a Rename ConstantSDNode's getSignExtended to getSExtValue, for
consistancy with ConstantInt, and re-implement it in terms
of ConstantInt's getSExtValue.

llvm-svn: 56700
2008-09-26 21:54:37 +00:00
Bill Wendling 24c79f28b1 Reverting r56249. On further investigation, this functionality isn't needed.
Apologies for the thrashing.

llvm-svn: 56251
2008-09-16 21:48:12 +00:00
Bill Wendling 8bc392fb1d - Change "ExternalSymbolSDNode" to "SymbolSDNode".
- Add linkage to SymbolSDNode (default to external).
- Change ISD::ExternalSymbol to ISD::Symbol.
- Change ISD::TargetExternalSymbol to ISD::TargetSymbol

These changes pave the way to allowing SymbolSDNodes with non-external linkage.

llvm-svn: 56249
2008-09-16 21:12:30 +00:00
Dan Gohman ec270fb640 Change ConstantSDNode and ConstantFPSDNode to use ConstantInt* and
ConstantFP* instead of APInt and APFloat directly.

This reduces the amount of time to create ConstantSDNode
and ConstantFPSDNode nodes when ConstantInt* and ConstantFP*
respectively are already available, as is the case in
SelectionDAGBuild.cpp. Also, it reduces the amount of time
to legalize constants into constant pools, and the amount of
time to add ConstantFP operands to MachineInstrs, due to
eliminating ConstantInt::get and ConstantFP::get calls.

It increases the amount of work needed to create new constants
in cases where the client doesn't already have a ConstantInt*
or ConstantFP*, such as legalize expanding 64-bit integer constants
to 32-bit constants. And it adds a layer of indirection for the
accessor methods. But these appear to be outweight by the benefits
in most cases.

It will also make it easier to make ConstantSDNode and
ConstantFPNode more consistent with ConstantInt and ConstantFP.

llvm-svn: 56162
2008-09-12 18:08:03 +00:00
Dan Gohman effb894453 Rename ConstantSDNode::getValue to getZExtValue, for consistency
with ConstantInt. This led to fixing a bug in TargetLowering.cpp
using getValue instead of getAPIntValue.

llvm-svn: 56159
2008-09-12 16:56:44 +00:00
Gabor Greif f304a7aa4d erect abstraction boundaries for accessing SDValue members, rename Val -> Node to reflect semantics
llvm-svn: 55504
2008-08-28 21:40:38 +00:00
Gabor Greif abfdf928d8 disallow direct access to SDValue::ResNo, provide a getter instead
llvm-svn: 55394
2008-08-26 22:36:50 +00:00
Chris Lattner 491a930ea3 code simplification, no functionality change.
llvm-svn: 55363
2008-08-26 07:01:28 +00:00
Dan Gohman eb0cee91f6 Move the point at which FastISel taps into the SelectionDAGISel
process up to a higher level. This allows FastISel to leverage
more of SelectionDAGISel's infastructure, such as updating Machine
PHI nodes.

Also, implement transitioning from SDISel back to FastISel in
the middle of a block, so it's now possible to go back and
forth. This allows FastISel to hand individual CallInsts and other
complicated things off to SDISel to handle, while handling the rest
of the block itself.

To help support this, reorganize the SelectionDAG class so that it
is allocated once and reused throughout a function, instead of
being completely reallocated for each block.

llvm-svn: 55219
2008-08-23 02:25:05 +00:00
Dan Gohman 49e19e906f Factor out the predicate check code from DAGISelEmitter.cpp
and use it in FastISelEmitter.cpp, and make FastISel
subtarget aware. Among other things, this lets it work
properly on x86 targets that don't have SSE, where it
successfully selects x87 instructions.

llvm-svn: 55156
2008-08-22 00:20:26 +00:00
Dan Gohman 3e2225dfd6 Factor the code for determining the target-specific instruction
namespace out of the isel emitters and into common code.

llvm-svn: 55079
2008-08-20 21:45:57 +00:00
Dan Gohman e81ac0b66f Oops, check in these files too, for the FastISel -> Fast rename.
llvm-svn: 54750
2008-08-13 19:55:00 +00:00
Mon P Wang 2c839d4b1e Added support for overloading intrinsics (atomics) based on pointers
to different address spaces.  This alters the naming scheme for those
intrinsics, e.g., atomic.load.add.i32 => atomic.load.add.i32.p0i32

llvm-svn: 54195
2008-07-30 04:36:53 +00:00
Dan Gohman 2ce6f2ad5e Rename SDOperand to SDValue.
llvm-svn: 54128
2008-07-27 21:46:04 +00:00
Dan Gohman 1705968102 Add a new function, ReplaceAllUsesOfValuesWith, which handles bulk
replacement of multiple values. This is slightly more efficient
than doing multiple ReplaceAllUsesOfValueWith calls, and theoretically
could be optimized even further. However, an important property of this
new function is that it handles the case where the source value set and
destination value set overlap. This makes it feasible for isel to use
SelectNodeTo in many very common cases, which is advantageous because
SelectNodeTo avoids a temporary node and it doesn't require CSEMap
updates for users of values that don't change position.

Revamp MorphNodeTo, which is what does all the work of SelectNodeTo, to
handle operand lists more efficiently, and to correctly handle a number
of corner cases to which its new wider use exposes it.

This commit also includes a change to the encoding of post-isel opcodes
in SDNodes; now instead of being sandwiched between the target-independent
pre-isel opcodes and the target-dependent pre-isel opcodes, post-isel
opcodes are now represented as negative values. This makes it possible
to test if an opcode is pre-isel or post-isel without having to know
the size of the current target's post-isel instruction set.

These changes speed up llc overall by 3% and reduce memory usage by 10%
on the InstructionCombining.cpp testcase with -fast and -regalloc=local.

llvm-svn: 53728
2008-07-17 19:10:17 +00:00
Dan Gohman d6ec05077f Refactor the tablegen DAGISelEmitter code for outputing calls to
getTargetNode and SelectNodeTo to reduce duplication, and to
make some of the getTargetNode code available to SelectNodeTo.
Use SelectNodeTo instead of getTargetNode in several new
interesting cases, as it mutates nodes in place instead of
creating new ones.

This triggers some scheduling behavior differences due to nodes
being presented to the scheduler in a different order. Some of the
arbitrary scheduling decisions it makes are now arbitrarily made
differently. This is visible in CodeGen/PowerPC/LargeAbsoluteAddr.ll,
where a trivial scheduling difference led to a trivial register
allocation difference.

llvm-svn: 53203
2008-07-07 21:00:17 +00:00
Evan Cheng 798d9bb97f isel load folding is disabled at -fast. Now hoist the check up to the top level to save some time.
llvm-svn: 53096
2008-07-03 08:39:51 +00:00
Dan Gohman 22e9707480 Replace a few uses of SelectionDAG::getTargetNode with
SelectionDAG::SelectNodeTo in the instruction selector. This
updates existing nodes in place instead of creating new ones.

Go back to selecting ISD::DBG_LABEL nodes into
TargetInstrInfo::DBG_LABEL nodes instead of leaving them
unselected, now that SelectNodeTo allows us to update them
in place.

llvm-svn: 53057
2008-07-02 23:23:19 +00:00
Dan Gohman fb19f9402b Split ISD::LABEL into ISD::DBG_LABEL and ISD::EH_LABEL, eliminating
the need for a flavor operand, and add a new SDNode subclass,
LabelSDNode, for use with them to eliminate the need for a label id
operand.

Change instruction selection to let these label nodes through
unmodified instead of creating copies of them. Teach the MachineInstr
emitter how to emit a MachineInstr directly from an ISD label node.

This avoids the need for allocating SDNodes for the label id and
flavor value, as well as SDNodes for each of the post-isel label,
label id, and label flavor.

llvm-svn: 52943
2008-07-01 00:05:16 +00:00
Mon P Wang 6a490371c9 Added MemOperands to Atomic operations since Atomics touches memory.
Added abstract class MemSDNode for any Node that have an associated MemOperand
Changed atomic.lcs => atomic.cmp.swap, atomic.las => atomic.load.add, and
atomic.lss => atomic.load.sub

llvm-svn: 52706
2008-06-25 08:15:39 +00:00
Duncan Sands 13237ac3b9 Wrap MVT::ValueType in a struct to get type safety
and better control the abstraction.  Rename the type
to MVT.  To update out-of-tree patches, the main
thing to do is to rename MVT::ValueType to MVT, and
rewrite expressions like MVT::getSizeInBits(VT) in
the form VT.getSizeInBits().  Use VT.getSimpleVT()
to extract a MVT::SimpleValueType for use in switch
statements (you will get an assert failure if VT is
an extended value type - these shouldn't exist after
type legalization).
This results in a small speedup of codegen and no
new testsuite failures (x86-64 linux).

llvm-svn: 52044
2008-06-06 12:08:01 +00:00
Dan Gohman 92d62b43c2 Fix the position of MemOperands in nodes that use variadic_ops
in DAGISelEmitter output. This bug was recently uncovered by the
addition of patterns for CALL32m and CALL64m, which are nodes
that now have both MemOperands and variadic_ops.

This bug was especially visible with PIC in various configurations,
because the new patterns are matching the indirect call code used
in many PIC configurations.

llvm-svn: 51877
2008-06-02 17:40:38 +00:00
Dan Gohman bd3390c73a Teach the DAGISelEmitter to not compute the variable_ops operand
index for the input pattern in terms of the output pattern. Instead
keep track of how many fixed operands the input pattern actually
has, and have the input matching code pass the output-emitting
function that index value. This simplifies the code, disentangles
variables_ops from the support for predication operations, and
makes variable_ops more robust.

llvm-svn: 51808
2008-05-31 02:11:25 +00:00
Dan Gohman 96af4ddb62 Add patterns for CALL32m and CALL64m. They aren't matched in most
cases due to an isel deficiency already noted in
lib/Target/X86/README.txt, but they can be matched in this fold-call.ll
testcase, for example.

This is interesting mainly because it exposes a tricky tblgen bug;
tblgen was incorrectly computing the starting index for variable_ops
in the case of a complex pattern.

llvm-svn: 51706
2008-05-29 21:50:34 +00:00
Dan Gohman 6e582c449f Fix a tblgen problem handling variable_ops in tblgen instruction
definitions. This adds a new construct, "discard", for indicating
that a named node in the input matching pattern is to be discarded,
instead of corresponding to a node in the output pattern. This
allows tblgen to know where the arguments for the varaible_ops are
supposed to begin.

This fixes "rdar://5791600", whatever that is ;-).

llvm-svn: 51699
2008-05-29 19:57:41 +00:00
Roman Levenstein 52a005ac13 Do not generate by TableGen the hard-coded standard, target-independent part of
DAG instruction selectors. Introudce a dedicated header file for this part:
include/llvm/CodeGen/DAGISelHeader.h

TableGen now only generates the include preprocessor directive to include this
new header.

This is a preparation for supporting multiple implementations of instruction
selectors in the future.

Reviewed and approved by Evan and Dan.

llvm-svn: 51102
2008-05-14 10:17:11 +00:00
Dan Gohman c60c67fc37 Add explicit keywords.
llvm-svn: 48801
2008-03-25 22:06:05 +00:00
Evan Cheng 0e7b00d79f Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF.
llvm-svn: 48380
2008-03-15 00:03:38 +00:00
Christopher Lamb dd55d3f1b2 Get rid of a pseudo instruction and replace it with subreg based operation on real instructions, ridding the asm printers of the hack used to do this previously. In the process, update LowerSubregs to be careful about eliminating copies that have side affects.
Note: the coalescer will have to be careful about this too, when it starts coalescing insert_subreg nodes.
llvm-svn: 48329
2008-03-13 05:47:01 +00:00
Bill Wendling e65d2afdb1 De-tabify.
llvm-svn: 47595
2008-02-26 10:45:29 +00:00
Anton Korobeynikov 579f07135a Unbreak build with gcc 4.3: provide missed includes and silence most annoying warnings.
llvm-svn: 47367
2008-02-20 11:08:44 +00:00
Scott Michel a3cefeaf0c Make tblgen a little smarter about constants smaller than i32. Currently,
tblgen will complain if a sign-extended constant does not fit into a
data type smaller than i32, e.g., i16. This causes a problem when certain
hex constants are used, such as 0xff for byte masks or immediate xor
values.

tblgen will try the sign-extended value first and, if the sign extended
value would overflow, it tries to see if the unsigned value will fit.
Consequently, a software developer can now safely incant:

	(XORHIr16 R16C:$rA, 0xffff)

which is somewhat clearer and more informative than incanting:

	(XORHIr16 R16C:$rA, (i16 -1))

even if the two are bitwise equivalent.

Tblgen also outputs the 64-bit unsigned constant in the generated ISel code
when getTargetConstant() is invoked.

llvm-svn: 47188
2008-02-15 23:05:48 +00:00
Nate Begeman 53e1b3f9d5 Change how FP immediates are handled.
1) ConstantFP is now expand by default
2) ConstantFP is not turned into TargetConstantFP during Legalize
   if it is legal.

This allows ConstantFP to be handled like Constant, allowing for 
targets that can encode FP immediates as MachineOperands.

As a bonus, fix up Itanium FP constants, which now correctly match,
and match more constants!  Hooray.

llvm-svn: 47121
2008-02-14 08:57:00 +00:00
Dan Gohman 2d489b5081 Re-apply the memory operand changes, with a fix for the static
initializer problem, a minor tweak to the way the
DAGISelEmitter finds load/store nodes, and a renaming of the
new PseudoSourceValue objects.

llvm-svn: 46827
2008-02-06 22:27:42 +00:00
Evan Cheng 87fbd66f9f Fix PR1975: dag isel emitter produces patterns that isel wrong flag result.
llvm-svn: 46776
2008-02-05 22:50:29 +00:00
Evan Cheng 2cb9068c78 Dwarf requires variable entries to be in the source order. Right now, since we are recording variable information at isel time this means parameters would appear in the reverse order. The short term fix is to issue recordVariable() at asm printing time instead.
llvm-svn: 46724
2008-02-04 23:06:48 +00:00
Chris Lattner b2b9d6f0fb Change the 'global modification' APIs in SelectionDAG to take a new
DAGUpdateListener object pointer instead of just returning a vector 
of deleted nodes.  This makes the interfaces more efficient (no more
allocating a vector [at least a malloc], filling it in, then walking
it) and more clean.  This also allows the client to be notified of
nodes that are *changed* but not deleted.

llvm-svn: 46677
2008-02-03 06:49:24 +00:00
Evan Cheng efd142a920 SDIsel processes llvm.dbg.declare by recording the variable debug information descriptor and its corresponding stack frame index in MachineModuleInfo. This only works if the local variable is "homed" in the stack frame. It does not work for byval parameter, etc.
Added ISD::DECLARE node type to represent llvm.dbg.declare intrinsic. Now the intrinsic calls are lowered into a SDNode and lives on through out the codegen passes.
For now, since all the debugging information recording is done at isel time, when a ISD::DECLARE node is selected, it has the side effect of also recording the variable. This is a short term solution that should be fixed in time.

llvm-svn: 46659
2008-02-02 04:07:54 +00:00
Evan Cheng 27b32b87ed Revert 46556 and 46585. Dan please fix the PseudoSourceValue problem and re-commit.
llvm-svn: 46623
2008-01-31 21:00:00 +00:00
Evan Cheng 1c6c16ea11 Add an extra operand to LABEL nodes which distinguishes between debug, EH, or misc labels. This fixes the EH breakage. However I am not convinced this is *the* solution.
llvm-svn: 46609
2008-01-31 09:59:15 +00:00
Christopher Lamb 0592cf7e74 Allow ComplexExpressions in InstrInfo.td files to be slightly more... complex! ComplexExpressions can now have attributes which affect how TableGen interprets
the pattern when generating matchin code. 

The first (and currently, only) attribute causes the immediate parent node of the ComplexPattern operand to be passed into the matching code rather than the node at the root of the entire DAG containing the pattern.

llvm-svn: 46606
2008-01-31 07:27:46 +00:00
Dan Gohman 3646fdda67 Create a new class, MemOperand, for describing memory references
in the backend. Introduce a new SDNode type, MemOperandSDNode, for
holding a MemOperand in the SelectionDAG IR, and add a MemOperand
list to MachineInstr, and code to manage them. Remove the offset
field from SrcValueSDNode; uses of SrcValueSDNode that were using
it are all all using MemOperandSDNode now.

Also, begin updating some getLoad and getStore calls to use the
PseudoSourceValue objects.

Most of this was written by Florian Brander, some
reorganization and updating to TOT by me.

llvm-svn: 46585
2008-01-31 00:25:39 +00:00
Scott Michel 167502a508 Fix to bug 1951: tblgen gratuitously renames variables when no temporary was
generated. This feature would only show up in fairly complex patterns, such
as this one in CellSPU:

  def : Pat<(add (SPUhi tconstpool:$in, 0), (SPUlo tconstpool:$in, 0)),
	    (IOHLlo (ILHUhi tconstpool:$in), tconstpool:$in)>;

which generated the following emit code:

SDNode *Emit_0(const SDOperand &N, unsigned Opc0, unsigned Opc1, MVT::ValueType VT0, MVT::ValueType VT1) DISABLE_INLINE {
  SDOperand N0 = N.getOperand(0);
  SDOperand N00 = N0.getOperand(0);
  SDOperand N01 = N0.getOperand(1);
  SDOperand N1 = N.getOperand(1);
  SDOperand N10 = N1.getOperand(0);
  SDOperand N11 = N1.getOperand(1);
  SDOperand Tmp3(CurDAG->getTargetNode(Opc0, VT0, N00), 0);
  return CurDAG->SelectNodeTo(N.Val, Opc1, VT1, Tmp3, Tmp2); /* Tmp2 s/b N00 */
}

Tested against the test suites without incident.

llvm-svn: 46487
2008-01-29 02:29:31 +00:00
Chris Lattner f376c99ea0 rename hasVariableOperands() -> isVariadic(). Add some comments.
Evan, please review the comments I added to getNumDefs to make sure
that they are accurate, thx.

llvm-svn: 45687
2008-01-07 05:19:29 +00:00
Chris Lattner d5326def4a improve const correctness.
llvm-svn: 45646
2008-01-06 01:52:22 +00:00
Chris Lattner ab3242fd46 rename CodegenDAGPatterns -> CodeGenDAGPatterns
llvm-svn: 45641
2008-01-06 01:10:31 +00:00
Chris Lattner 7980bba549 now that computing CodegenDAGPatterns doesn't implicitly print stuff
out, DAGISelEmitter can compute it in its ctor, which simplifies some code.

Now we can use CodegenDAGPatterns in other parts of tblgen that want access
to dag pattern info, woo!

llvm-svn: 45636
2008-01-05 22:58:54 +00:00
Chris Lattner cc43e79bcd move Node Transformation printing from CodeGenDAGPatterns -> DAGISelEmitter.
The only difference in output is that we now print them in alphabetical 
order instead of reverse alphabetical order.

llvm-svn: 45635
2008-01-05 22:54:53 +00:00
Chris Lattner e7170df043 move predicate printing code from CodeGenDAGPatterns -> DAGISelEmitter.
llvm-svn: 45634
2008-01-05 22:43:57 +00:00
Chris Lattner 9abe77b2d0 fix a fixme by improving const correctness.
llvm-svn: 45633
2008-01-05 22:30:17 +00:00
Chris Lattner 8cab021ca2 change getQualifiedName to be a global function.
Split the pattern parsing code out from the dag isel emitter into it's own file.

No functionality change.

llvm-svn: 45632
2008-01-05 22:25:12 +00:00
Chris Lattner 8adcd9f32e remove attributions from utils.
llvm-svn: 45419
2007-12-29 20:37:13 +00:00
Chris Lattner 0083d8f38d switch some calls to SelectionDAG::getTargetNode to use
the one that takes an operand list instead of explicit
operands.  There is one left though, the more interesting
one :)

llvm-svn: 43290
2007-10-24 06:25:09 +00:00
Chris Lattner 3cfb56d489 One mundane change: Change ReplaceAllUsesOfValueWith to *optionally*
take a deleted nodes vector, instead of requiring it.

One more significant change:  Implement the start of a legalizer that
just works on types.  This legalizer is designed to run before the 
operation legalizer and ensure just that the input dag is transformed
into an output dag whose operand and result types are all legal, even
if the operations on those types are not.

This design/impl has the following advantages:

1. When finished, this will *significantly* reduce the amount of code in
   LegalizeDAG.cpp.  It will remove all the code related to promotion and
   expansion as well as splitting and scalarizing vectors.
2. The new code is very simple, idiomatic, and modular: unlike 
   LegalizeDAG.cpp, it has no 3000 line long functions. :)
3. The implementation is completely iterative instead of recursive, good
   for hacking on large dags without blowing out your stack.
4. The implementation updates nodes in place when possible instead of 
   deallocating and reallocating the entire graph that points to some 
   mutated node.
5. The code nicely separates out handling of operations with invalid 
   results from operations with invalid operands, making some cases
   simpler and easier to understand.
6. The new -debug-only=legalize-types option is very very handy :), 
   allowing you to easily understand what legalize types is doing.

This is not yet done.  Until the ifdef added to SelectionDAGISel.cpp is
enabled, this does nothing.  However, this code is sufficient to legalize
all of the code in 186.crafty, olden and freebench on an x86 machine.  The
biggest issues are:

1. Vectors aren't implemented at all yet
2. SoftFP is a mess, I need to talk to Evan about it.
3. No lowering to libcalls is implemented yet.
4. Various operations are missing etc.
5. There are FIXME's for stuff I hax0r'd out, like softfp.

Hey, at least it is a step in the right direction :).  If you'd like to help,
just enable the #ifdef in SelectionDAGISel.cpp and compile code with it.  If
this explodes it will tell you what needs to be implemented.  Help is 
certainly appreciated.

Once this goes in, we can do three things:

1. Add a new pass of dag combine between the "type legalizer" and "operation
   legalizer" passes.  This will let us catch some long-standing isel issues
   that we miss because operation legalization often obfuscates the dag with
   target-specific nodes.
2. We can rip out all of the type legalization code from LegalizeDAG.cpp,
   making it much smaller and simpler.  When that happens we can then 
   reimplement the core functionality left in it in a much more efficient and
   non-recursive way.
3. Once the whole legalizer is non-recursive, we can implement whole-function
   selectiondags maybe...

llvm-svn: 42981
2007-10-15 06:10:22 +00:00
Evan Cheng 2e3d609da6 Fix typos.
llvm-svn: 42896
2007-10-12 08:39:02 +00:00
Evan Cheng 43686dad3d Rename keyword "modify" -> "implicit".
llvm-svn: 42282
2007-09-25 01:48:59 +00:00
Evan Cheng ffd6995cc7 Bug fix and minor clean up of generated code.
llvm-svn: 42069
2007-09-17 22:26:41 +00:00
Evan Cheng 59c39dc197 Initial support for multi-result patterns:
1.
[(set GR32:$dst, (add GR32:$src1, GR32:$src2)),
 (modify EFLAGS)]
This indicates the source pattern expects the instruction would produce 2 values. The first is the result of the addition. The second is an implicit definition in register EFLAGS.
2.
def : Pat<(parallel (addc GR32:$src1, GR32:$src2), (modify EFLAGS)), ()>
Similar to #1 except this is used for def : Pat patterns.

llvm-svn: 41897
2007-09-12 23:30:14 +00:00
Evan Cheng c7852a689a Allow set operators with multiple destinations, i.e. (set x, y, (op a, b)).
llvm-svn: 41861
2007-09-11 19:52:18 +00:00
Evan Cheng cef2c0efcc TableGen no longer emit CopyFromReg nodes for implicit results in physical
registers. The scheduler is now responsible for emitting them.

llvm-svn: 41781
2007-09-07 23:59:02 +00:00
Evan Cheng 20711a8b9a Always check the type of node. This prevents situations such as selecting 32-bit rotate target instruction for a 64-bit node when 64-bit pattern is missing.
llvm-svn: 41710
2007-09-04 20:18:28 +00:00
Christopher Lamb cde0ee5221 Add target independent MachineInstr's to represent subreg insert/extract in MBB's. PR1350
llvm-svn: 40518
2007-07-26 07:48:21 +00:00
Dan Gohman 5a629d4cee A minor simplication in the generated code.
llvm-svn: 40479
2007-07-24 22:58:00 +00:00
Evan Cheng 869852b03e No need for noResults anymore.
llvm-svn: 40075
2007-07-20 00:21:23 +00:00
Evan Cheng 94b5a80b93 Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr  : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr  : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;

llvm-svn: 40033
2007-07-19 01:14:50 +00:00
Evan Cheng a7d41aad4f Refactor code to add initial support for OptionalDefOperand.
llvm-svn: 37933
2007-07-06 01:05:26 +00:00
Evan Cheng ffabff11c0 Teach DAGISelEmitter about zero_reg.
llvm-svn: 37900
2007-07-05 07:19:45 +00:00
Chris Lattner b4777f087a silence warning when assertions are disabled.
llvm-svn: 37654
2007-06-19 06:40:46 +00:00
Chris Lattner 2b5badc0e1 Fix CodeGen/PowerPC/2007-05-14-InlineAsmSelectCrash.ll, the other recent
patches are also needed.

llvm-svn: 37070
2007-05-15 01:36:44 +00:00
Evan Cheng b0925c0e49 PredicateOperand related bug fix.
llvm-svn: 37060
2007-05-15 01:19:51 +00:00
Evan Cheng 5162f584c7 If a PredicateOperand has an empty ExecuteAlways field, treat it as if a normal operand for isel.
llvm-svn: 36946
2007-05-08 21:04:07 +00:00
Lauro Ramos Venancio 83fc4f3c3c bugfix: remember that ResNode was declared.
llvm-svn: 36477
2007-04-26 17:03:22 +00:00
Lauro Ramos Venancio 2518889872 Implement "general dynamic", "initial exec" and "local exec" TLS models for
X86 32 bits.

llvm-svn: 36283
2007-04-20 21:38:10 +00:00
Jim Laskey 73e79b5a43 Make the constant honest.
llvm-svn: 33557
2007-01-26 23:00:54 +00:00
Jim Laskey 214c582002 Files missing from LABEL check in.
llvm-svn: 33539
2007-01-26 17:29:20 +00:00
Chris Lattner 100602d756 Make tblgen error more useful. Patch by B. Scott Michel
llvm-svn: 33295
2007-01-17 07:45:12 +00:00
Bill Wendling 9bfb1e1f29 What should be the last unnecessary <iostream>s in the library.
llvm-svn: 32333
2006-12-07 22:21:48 +00:00
Chris Lattner 55b8683d24 Fix PR1001, patch by Nikhil Patil!
llvm-svn: 31880
2006-11-20 18:54:33 +00:00
Chris Lattner c75081b7a8 restore some 'magic' code that I removed: it is needed. Add comments explaining
why.

llvm-svn: 31743
2006-11-14 22:17:10 +00:00
Chris Lattner c5dd5b11a4 minimal hack to get patterns whose result type is iPTR to be selected.
llvm-svn: 31742
2006-11-14 21:50:27 +00:00
Chris Lattner 75165d07a0 remove some dead code
llvm-svn: 31740
2006-11-14 21:41:35 +00:00
Chris Lattner 7c9f48cefb Add support for nodes that return iPTR.
llvm-svn: 31739
2006-11-14 21:32:01 +00:00
Chris Lattner 110c777f2c changes to get ptr_rc to be accepted in patterns. This is needed for ppc preinc
stores.

llvm-svn: 31738
2006-11-14 21:18:40 +00:00
Chris Lattner f8c06b335d Fix a bug handling nodes with variable arguments. The code was fixed to assume
that there were two input operands before the variable operand portion.  This
*happened* to be true for all call instructions, which took a chain and a
destination, but was not true for the PPC BCTRL instruction, whose destination
is implicit.

Making this code more general allows elimination of the custom selection logic
for BCTRL.

llvm-svn: 31732
2006-11-14 18:41:38 +00:00
Evan Cheng 7120b9e9c7 Divide select methods into groups by SelectionDAG node opcodes (ISD::ADD,
X86ISD::CMP, etc.) instead of SDNode names (add, x86cmp, etc). We now allow
multiple SDNodes to map to the same SelectionDAG node (e.g. store, indexed
store).

llvm-svn: 31575
2006-11-08 23:01:03 +00:00
Evan Cheng d715a2cbfb Always pass the root node to ComplexPattern isel matching function.
llvm-svn: 31570
2006-11-08 20:31:10 +00:00
Chris Lattner ed07f23c52 Parse PredicateOperand's. When an instruction takes one, have the generated
isel fill in the instruction operands with the 'execute always' value
automatically.

llvm-svn: 31448
2006-11-04 05:12:02 +00:00
Chris Lattner 1faa9097c7 First steps to getting PredicateOperand's to work. This handles instruction
and pat pattern definitions.  Codegen is not right for them yet.

llvm-svn: 31444
2006-11-04 01:35:50 +00:00
Chris Lattner 71f55131d4 silence warnings
llvm-svn: 31392
2006-11-03 01:11:05 +00:00
Reid Spencer 6152ad000c Revert last patch which causes tblgen to segfault (why, I'm not sure).
llvm-svn: 31383
2006-11-02 21:07:40 +00:00
Reid Spencer 2a82686563 For PR786:
Remove unused variables.

llvm-svn: 31381
2006-11-02 20:46:16 +00:00
Evan Cheng 23654935f4 Not meant to be checked in.
llvm-svn: 31334
2006-11-01 00:27:59 +00:00
Evan Cheng ac79c7c4c0 Add operand constraints to TargetInstrInfo.
llvm-svn: 31333
2006-11-01 00:27:05 +00:00
Evan Cheng a74965f15a Passing isel root and use operands to ComplexPattern functions, these should do the usual load folding checks as well.
llvm-svn: 30972
2006-10-16 06:33:44 +00:00
Evan Cheng cfb9526d61 When checking if a load can be folded, we check if there is any non-direct
way to reach the load via any nodes that would be folded. Start from the
root of the matched sub-tree.

llvm-svn: 30956
2006-10-14 08:30:15 +00:00
Evan Cheng 1d04dd3aac Really remove dead nodes from isel queue.
llvm-svn: 30923
2006-10-12 23:18:52 +00:00
Evan Cheng 8e770f5589 Use RemoveDeadNode to kill dead node.
llvm-svn: 30917
2006-10-12 20:35:19 +00:00
Evan Cheng d7125583f7 Prior load folding check on chain operand was too strict. It requires the
chain operand to point to the load being folded. Now we relax this, traversing
up the chain, if it doesn't reach the load, then it's ok. We will create a
TokenFactor (of all the chain operands and the load's chain) to capture all
the control flow dependencies.

llvm-svn: 30897
2006-10-12 02:08:53 +00:00
Evan Cheng 2022c79d7f Added properties such as SDNPHasChain to ComplexPattern.
llvm-svn: 30890
2006-10-11 21:02:01 +00:00
Chris Lattner f405928e86 Special case tblgen generated code for patterns like (and X, 255) or (or X, 42).
The dag/inst combiners often 'simplify' the masked value based on whether
or not the bits are live or known zero/one.  This is good and dandy, but
often causes special case patterns to fail, such as alpha's CMPBGE pattern,
which looks like "(set GPRC:$RC, (setuge (and GPRC:$RA, 255), (and GPRC:$RB, 255)))".
Here the pattern for (and X, 255) should match actual dags like (and X, 254) if
the dag combiner proved that the missing bits are already zero (one for 'or').

For CodeGen/Alpha/cmpbge.ll:test2 for example, this results in:

        sll $16,1,$0
        cmpbge $0,$17,$0
        ret $31,($26),1

instead of:

        sll $16,1,$0
        and $0,254,$0
        and $17,255,$1
        cmpule $1,$0,$0
        ret $31,($26),1

... and requires no target-specific code.

llvm-svn: 30871
2006-10-11 04:05:55 +00:00
Chris Lattner 66fbbca1e7 Split some code out into a new method. The generated code is exactly
identical, this is just a refactoring.

llvm-svn: 30868
2006-10-11 03:35:34 +00:00
Evan Cheng 75a1b70da8 Predicate function on the node should be matched before its childrean' matching
code. This is especially important now matching ISD::LOAD also requires a
Predicate_Load call.

llvm-svn: 30845
2006-10-09 21:02:17 +00:00
Chris Lattner 7d3fd4f888 don't allow 'imm' or specific imms, like '1' on the LHS of a binop.
This shrinks X86GenDAGISel by ~330 lines.

llvm-svn: 30574
2006-09-21 20:46:13 +00:00
Chris Lattner 99ae714459 Fit to 80 columns.
llvm-svn: 30572
2006-09-21 18:28:27 +00:00
Evan Cheng 9de003670f Allow PatFrag to be a leaf node.
llvm-svn: 30498
2006-09-19 19:08:04 +00:00
Evan Cheng 00b2848adb Add result of a Xform to isel queue.
llvm-svn: 30497
2006-09-19 18:40:15 +00:00
Chris Lattner bea5f91946 If multiple predicates are listed, they must all pass
llvm-svn: 30476
2006-09-19 00:41:36 +00:00
Chris Lattner bba17b9913 There!
llvm-svn: 30473
2006-09-18 22:41:07 +00:00
Chris Lattner 82a73a1989 Fix Regression/TableGen/2006-09-18-LargeInt.td
llvm-svn: 30472
2006-09-18 22:28:27 +00:00
Chris Lattner 3ffda067e3 Relax this check.
llvm-svn: 30381
2006-09-14 23:54:24 +00:00
Evan Cheng 1ec61ba00a 1) With X86 lowering change, the following can no longer happen since
the branch's chain is also produced by cmp.
          [ch, r : ld]
             ^ ^
             | |
      [XX]--/   \- [flag : cmp]
       ^             ^
       |             |
       \---[br flag]-

Remove an isel check which prevents loads from being folded into cmp / test
instructions.

2) Whenever possible, delete a selected node to allow more load folding
opportunities. Note not all nodes can be deleted after it has been
selected. Some may have simply morphed; some have not changed at all (e.g.
EntryToken).

llvm-svn: 30242
2006-09-11 02:24:43 +00:00
Evan Cheng 5a798b0648 Generated isel should favors explicit constant operand (+2) over an operand with a predicate (+1).
llvm-svn: 30180
2006-09-08 07:26:39 +00:00
Chris Lattner 251468e9d0 Use compiler.h instead of hand rolling our own macro
llvm-svn: 29913
2006-08-27 13:16:24 +00:00
Evan Cheng 44ce57d5c2 Do not emit getTargetNode() and SelectNodeTo() which takes more than 3
SDOperand arguments. Use the variants which take an array and number instead.

llvm-svn: 29906
2006-08-27 08:11:28 +00:00
Evan Cheng 34b70eea5c SelectNodeTo now returns a SDNode*.
llvm-svn: 29901
2006-08-26 08:00:10 +00:00
Evan Cheng b7b5ba5aaf Minor getCopyToReg() call change.
llvm-svn: 29900
2006-08-26 07:39:28 +00:00
Evan Cheng 61413a3d72 Select() no longer require Result operand by reference.
llvm-svn: 29898
2006-08-26 05:34:46 +00:00