Commit Graph

248 Commits

Author SHA1 Message Date
Evan Cheng bc153d49b7 Next round of MC refactoring. This patch factor MC table instantiations, MC
registeration and creation code into XXXMCDesc libraries.

llvm-svn: 135184
2011-07-14 20:59:42 +00:00
Owen Anderson 651b230ca0 Add a target-indepedent entry to MCInstrDesc to describe the encoded size of an opcode. Switch ARM over to using that rather than its own special MCInstrDesc bits.
llvm-svn: 135106
2011-07-13 23:22:26 +00:00
Eric Christopher 71520a867d Revert r134921, 134917, 134908 and 134907. They're causing failures
in multiple buildbots.

llvm-svn: 134936
2011-07-11 23:06:52 +00:00
David Greene af973b4f36 [AVX] Make Inits Foldable
Manage Inits in a FoldingSet.  This provides several benefits:

- Memory for Inits is properly managed

- Duplicate Inits are folded into Flyweights, saving memory

- It enforces const-correctness, protecting against certain classes
  of bugs

The above benefits allow Inits to be used in more contexts, which in
turn provides more dynamism to TableGen.  This enhanced capability
will be used by the AVX code generator to a fold common patterns
together.

llvm-svn: 134907
2011-07-11 18:25:51 +00:00
Evan Cheng 54b68e3432 - Added MCSubtargetInfo to capture subtarget features and scheduling
itineraries.
- Refactor TargetSubtarget to be based on MCSubtargetInfo.
- Change tablegen generated subtarget info to initialize MCSubtargetInfo
  and hide more details from targets.

llvm-svn: 134257
2011-07-01 20:45:01 +00:00
Evan Cheng 703a0fbf39 Hide the call to InitMCInstrInfo into tblgen generated ctor.
llvm-svn: 134244
2011-07-01 17:57:27 +00:00
Evan Cheng df8974ef2f Add MCInstrInfo registeration machinery.
llvm-svn: 134026
2011-06-28 20:29:03 +00:00
Evan Cheng 1e210d08d8 Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.inc
llvm-svn: 134024
2011-06-28 20:07:07 +00:00
Evan Cheng 6cc775f905 - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and
sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.

llvm-svn: 134021
2011-06-28 19:10:37 +00:00
Evan Cheng 105974d497 Remove RCBarriers from TargetInstrDesc.
llvm-svn: 133964
2011-06-27 23:47:21 +00:00
Owen Anderson a84be6c96b Add support for alternative register names, useful for instructions whose operands are logically equivalent to existing registers, but happen to be printed specially. For example, an instruciton that prints d0[0] instead of s0.
Patch by Jim Grosbach.

llvm-svn: 133940
2011-06-27 21:06:21 +00:00
Jakob Stoklund Olesen d7bc5c26ab Give CodeGenRegisterClass a real sorted member set.
Make the Elements vector private and expose an ArrayRef through
getOrder() instead. getOrder will eventually provide multiple
user-specified allocation orders.

Use the sorted member set for member and subclass tests. Clean up a lot
of ad hoc searches.

llvm-svn: 133040
2011-06-15 04:50:36 +00:00
Evan Cheng 880e299dcd - Add "Bitcast" target instruction property for instructions which perform
nothing more than a bitcast.
- Teach tablegen to automatically infer "Bitcast" property.

llvm-svn: 127667
2011-03-15 05:09:26 +00:00
Evan Cheng 7f8ab6ee8b Remove ARM isel hacks that fold large immediates into a pair of add, sub, and,
and xor. The 32-bit move immediates can be hoisted out of loops by machine
LICM but the isel hacks were preventing them.

Instead, let peephole optimization pass recognize registers that are defined by
immediates and the ARM target hook will fold the immediates in.

Other changes include 1) do not fold and / xor into cmp to isel TST / TEQ
instructions if there are multiple uses. This happens when the 'and' is live
out, machine sink would have sinked the computation and that ends up pessimizing
code. The peephole pass would recognize situations where the 'and' can be
toggled to define CPSR and eliminate the comparison anyway.

2) Move peephole pass to after machine LICM, sink, and CSE to avoid blocking
important optimizations.

rdar://8663787, rdar://8241368

llvm-svn: 119548
2010-11-17 20:13:28 +00:00
Chris Lattner d8adec70f3 factor the operand list (and related fields/operations) out of
CodeGenInstruction into its own helper class.  No functionality change.

llvm-svn: 117893
2010-11-01 04:03:32 +00:00
Owen Anderson 2c5df619c4 Revert r114703 and r114702, removing the isConditionalMove flag from instructions. After further
reflection, this isn't going to achieve the purpose I intended it for.  Back to the drawing board!

llvm-svn: 114710
2010-09-23 23:45:25 +00:00
Owen Anderson 6e0e8d7d64 Add an TargetInstrDesc bit to indicate that a given instruction is a conditional move.
Not intended functionality change, as nothing uses this yet.

llvm-svn: 114702
2010-09-23 22:44:10 +00:00
Bill Wendling 18e853f458 Add back in r109901, which adds a Compare flag to the target instructions. It's
useful after all.

llvm-svn: 110531
2010-08-08 01:49:35 +00:00
Bill Wendling e8bb340203 Revert r109901. The implementation of <rdar://problem/7405933> (r110423) doesn't
need the Compare flag after all.

--- Reverse-merging r109901 into '.':
U    include/llvm/Target/TargetInstrDesc.h
U    include/llvm/Target/Target.td
U    utils/TableGen/InstrInfoEmitter.cpp
U    utils/TableGen/CodeGenInstruction.cpp
U    utils/TableGen/CodeGenInstruction.h

llvm-svn: 110424
2010-08-06 01:36:09 +00:00
Bill Wendling 9b8d586039 Add a "Compare" flag to the target instruction descriptor. This will be used
later to identify and possibly remove superfluous compare instructions -- those
that are testing for and setting a status flag that should already be set.

llvm-svn: 109901
2010-07-30 22:48:39 +00:00
Dan Gohman 882bb2984e Start TargetRegisterClass indices at 0 instead of 1, so that
MachineRegisterInfo doesn't have to confusingly allocate an extra
entry.

llvm-svn: 106296
2010-06-18 18:13:55 +00:00
Eric Christopher 223c481b1c How about ULL...
llvm-svn: 105726
2010-06-09 16:16:48 +00:00
Bruno Cardoso Lopes c2f87b7bb2 Reapply r105521, this time appending "LLU" to 64 bit
immediates to avoid breaking the build.

llvm-svn: 105652
2010-06-08 22:51:23 +00:00
Jakob Stoklund Olesen b93331f3be Replace TSFlagsFields and TSFlagsShifts with a simpler TSFlags field.
When a target instruction wants to set target-specific flags, it should simply
set bits in the TSFlags bit vector defined in the Instruction TableGen class.

This works well because TableGen resolves member references late:

class I : Instruction {
  AddrMode AM = AddrModeNone;
  let TSFlags{3-0} = AM.Value;
}

let AM = AddrMode4 in
def ADD : I;

TSFlags gets the expected bits from AddrMode4 in this example.

llvm-svn: 100384
2010-04-05 03:10:20 +00:00
Jakob Stoklund Olesen f8d7eda663 Teach TableGen to understand X.Y notation in the TSFlagsFields strings.
Remove much horribleness from X86InstrFormats as a result. Similar
simplifications are probably possible for other targets.

llvm-svn: 99539
2010-03-25 18:52:01 +00:00
Chris Lattner 1802b17b65 Finally change the instruction looking map to be a densemap from
record* -> instrinfo instead of std::string -> instrinfo.

This speeds up tblgen on cellcpu from 7.28 -> 5.98s with a debug
build (20%).

llvm-svn: 98916
2010-03-19 01:07:44 +00:00
Chris Lattner 4763dbeaf6 make inst_begin/inst_end iterate over InstructionsByEnumValue.
Use CodeGenTarget::getInstNamespace in one place and fix it.

llvm-svn: 98915
2010-03-19 01:00:55 +00:00
Chris Lattner 2d822ab185 revert 98912
llvm-svn: 98914
2010-03-19 00:50:47 +00:00
Chris Lattner 45e2fc5ac1 make inst_begin/inst_end iterate over InstructionsByEnumValue.
llvm-svn: 98912
2010-03-19 00:40:22 +00:00
Chris Lattner 918be520dc change Target.getInstructionsByEnumValue to return a reference
to a vector that CGT stores instead of synthesizing it on every 
call.

llvm-svn: 98910
2010-03-19 00:34:35 +00:00
Chris Lattner a9dfb1bc07 Introduce a new CodeGenInstruction::ConstraintInfo class
for representing constraint info semantically instead of
as a c expression that will be blatted out to the .inc
file.  Fix X86RecognizableInstr to use this instead of
parsing C code :).

llvm-svn: 95753
2010-02-10 01:45:28 +00:00
Chris Lattner b06015aa69 move target-independent opcodes out of TargetInstrInfo
into TargetOpcodes.h.  #include the new TargetOpcodes.h
into MachineInstr.  Add new inline accessors (like isPHI())
to MachineInstr, and start using them throughout the 
codebase.

llvm-svn: 95687
2010-02-09 19:54:29 +00:00
Dale Johannesen 881ba0bb92 Remove DEBUG_DECLARE, looks like we don't need it.
Also, DEBUG_VALUE has side effects.

llvm-svn: 93498
2010-01-15 01:50:44 +00:00
Dale Johannesen 237254dcab Add DEBUG_DECLARE. Not used yet.
llvm-svn: 93040
2010-01-09 01:24:25 +00:00
Dale Johannesen 8f04740650 Add DEBUG_VALUE. Not used yet.
llvm-svn: 93030
2010-01-08 23:51:25 +00:00
Dan Gohman 453d64c9f5 Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a
bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.

llvm-svn: 85517
2009-10-29 18:10:34 +00:00
Evan Cheng 46668e09be Add instruction flags: hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq. When
set, these flags indicate the instructions source / def operands have special
register allocation requirement that are not captured in their register classes.
Post-allocation passes (e.g. post-alloc scheduler) should not change their
allocations. e.g. ARM::LDRD require the two definitions to be allocated
even / odd register pair.

llvm-svn: 83196
2009-10-01 08:21:18 +00:00
Jakob Stoklund Olesen dc9efe8078 Introduce the TargetInstrInfo::KILL machine instruction and get rid of the
unused DECLARE instruction.

KILL is not yet used anywhere, it will replace TargetInstrInfo::IMPLICIT_DEF
in the places where IMPLICIT_DEF is just used to alter liveness of physical
registers.

llvm-svn: 83006
2009-09-28 20:32:26 +00:00
Chris Lattner 06fa176862 prune the #includes in raw_ostream.h by moving a
member out of line. ftostr is not particularly speedy,
so that method is presumably not perf sensitive.

llvm-svn: 79885
2009-08-24 03:52:50 +00:00
Chris Lattner f3239532cc 1. Introduce a new TargetOperandInfo::getRegClass() helper method
and convert code to using it, instead of having lots of things
   poke the isLookupPtrRegClass() method directly.

2. Make PointerLikeRegClass contain a 'kind' int, and store it in
   the existing regclass field of TargetOperandInfo when the
   isLookupPtrRegClass() predicate is set.  Make getRegClass pass
   this into TargetRegisterInfo::getPointerRegClass(), allowing
   targets to have multiple ptr_rc things.

llvm-svn: 77504
2009-07-29 21:10:12 +00:00
Chris Lattner 426bc7c0ae make ptr_rc derive from a new PointerLikeRegClass tblgen class.
llvm-svn: 77503
2009-07-29 20:43:05 +00:00
Daniel Dunbar 38a22bffdc Replace std::iostreams with raw_ostream in TableGen.
- Sorry, I can't help myself.

 - No intended functionality change.

llvm-svn: 74742
2009-07-03 00:10:29 +00:00
Dan Gohman 6c1426308c Rename COPY_TO_SUBCLASS to COPY_TO_REGCLASS, and generalize
it accordingly. Thanks to Jakob Stoklund Olesen for pointing
out how this might be useful.

llvm-svn: 68986
2009-04-13 21:06:25 +00:00
Dan Gohman 60a446ab02 Add a new TargetInstrInfo MachineInstr opcode, COPY_TO_SUBCLASS.
This will be used to replace things like X86's MOV32to32_.

Enhance ScheduleDAGSDNodesEmit to be more flexible and robust
in the presense of subregister superclasses and subclasses. It
can now cope with the definition of a virtual register being in
a subclass of a use.

Re-introduce the code for recording register superreg classes and
subreg classes. This is needed because when subreg extracts and
inserts get coalesced away, the virtual registers are left in
the correct subclass.

llvm-svn: 68961
2009-04-13 15:38:05 +00:00
Dan Gohman 69cc2cbbff Rename isSimpleLoad to canFoldAsLoad, to better reflect its meaning.
llvm-svn: 60487
2008-12-03 18:15:48 +00:00
Evan Cheng 010e9b0760 Add RCBarriers to TargetInstrDesc. It's a list of register classes the given instruction can "clobber". For example, on x86 the call instruction can modify all of the XMM and fp stack registers.
TableGen has been taught to generate the lists from instruction definitions.

llvm-svn: 57722
2008-10-17 21:00:09 +00:00
Dan Gohman fb19f9402b Split ISD::LABEL into ISD::DBG_LABEL and ISD::EH_LABEL, eliminating
the need for a flavor operand, and add a new SDNode subclass,
LabelSDNode, for use with them to eliminate the need for a label id
operand.

Change instruction selection to let these label nodes through
unmodified instead of creating copies of them. Teach the MachineInstr
emitter how to emit a MachineInstr directly from an ISD label node.

This avoids the need for allocating SDNodes for the label id and
flavor value, as well as SDNodes for each of the post-isel label,
label id, and label flavor.

llvm-svn: 52943
2008-07-01 00:05:16 +00:00
Dan Gohman bd3390c73a Teach the DAGISelEmitter to not compute the variable_ops operand
index for the input pattern in terms of the output pattern. Instead
keep track of how many fixed operands the input pattern actually
has, and have the input matching code pass the output-emitting
function that index value. This simplifies the code, disentangles
variables_ops from the support for predication operations, and
makes variable_ops more robust.

llvm-svn: 51808
2008-05-31 02:11:25 +00:00
Dan Gohman 6e582c449f Fix a tblgen problem handling variable_ops in tblgen instruction
definitions. This adds a new construct, "discard", for indicating
that a named node in the input matching pattern is to be discarded,
instead of corresponding to a node in the output pattern. This
allows tblgen to know where the arguments for the varaible_ops are
supposed to begin.

This fixes "rdar://5791600", whatever that is ;-).

llvm-svn: 51699
2008-05-29 19:57:41 +00:00
Bill Wendling 3f6bb2713e Add a flag to indicate that an instruction is as cheap (or cheaper) than a move
instruction to execute. This can be used for transformations (like two-address
conversion) to remat an instruction instead of generating a "move"
instruction. The idea is to decrease the live ranges and register pressure and
all that jazz.

llvm-svn: 51660
2008-05-28 22:54:52 +00:00
Dan Gohman fc4ad7de66 Move instruction flag inference out of InstrInfoEmitter and into
CodeGenDAGPatterns, where it can be used in other tablegen backends.
This allows the inference to be done for DAGISelEmitter so that it
gets accurate mayLoad/mayStore/isSimpleLoad flags. 

This brings MemOperand functionality back to where it was before
48329. However, it doesn't solve the problem of anonymous patterns
which expand to code that does loads or stores.

llvm-svn: 49123
2008-04-03 00:02:49 +00:00
Christopher Lamb d3d0ad3f58 Make insert_subreg a two-address instruction, vastly simplifying LowerSubregs pass. Add a new TII, subreg_to_reg, which is like insert_subreg except that it takes an immediate implicit value to insert into rather than a register.
llvm-svn: 48412
2008-03-16 03:12:01 +00:00
Evan Cheng ec7533b620 Remove isImplicitDef TargetInstrDesc flag.
llvm-svn: 48381
2008-03-15 00:19:36 +00:00
Evan Cheng 0e7b00d79f Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF.
llvm-svn: 48380
2008-03-15 00:03:38 +00:00
Evan Cheng efd142a920 SDIsel processes llvm.dbg.declare by recording the variable debug information descriptor and its corresponding stack frame index in MachineModuleInfo. This only works if the local variable is "homed" in the stack frame. It does not work for byval parameter, etc.
Added ISD::DECLARE node type to represent llvm.dbg.declare intrinsic. Now the intrinsic calls are lowered into a SDNode and lives on through out the codegen passes.
For now, since all the debugging information recording is done at isel time, when a ISD::DECLARE node is selected, it has the side effect of also recording the variable. This is a short term solution that should be fixed in time.

llvm-svn: 46659
2008-02-02 04:07:54 +00:00
Chris Lattner c8226f32e9 Simplify the side effect stuff a bit more and make licm/sinking
both work right according to the new flags.

This removes the TII::isReallySideEffectFree predicate, and adds
TII::isInvariantLoad. 

It removes NeverHasSideEffects+MayHaveSideEffects and adds
UnmodeledSideEffects as machine instr flags.  Now the clients
can decide everything they need.

I think isRematerializable can be implemented in terms of the
flags we have now, though I will let others tackle that.

llvm-svn: 45843
2008-01-10 23:08:24 +00:00
Chris Lattner 317332fc2a Start inferring side effect information more aggressively, and fix many bugs in the
x86 backend where instructions were not marked maystore/mayload, and perf issues where
instructions were not marked neverHasSideEffects.  It would be really nice if we could
write patterns for copy instructions.

I have audited all the x86 instructions down to MOVDQAmr.  The flags on others and on
other targets are probably not right in all cases, but no clients currently use this
info that are enabled by default.

llvm-svn: 45829
2008-01-10 07:59:24 +00:00
Chris Lattner 86c458a178 if an instr lacks a pattern, assume it has side effects (unless never has s-e is true).
llvm-svn: 45823
2008-01-10 05:40:54 +00:00
Chris Lattner 42c63ef96e start inferring 'no side effects'.
llvm-svn: 45822
2008-01-10 05:39:30 +00:00
Chris Lattner 9e69654461 Infer mayload
llvm-svn: 45819
2008-01-10 04:44:48 +00:00
Chris Lattner 1ca2068227 realize that instructions who match intrinsics that read memory read memory.
Also, instructions with any nodes that are SDNPMayLoad also read memory.

llvm-svn: 45817
2008-01-10 04:38:57 +00:00
Chris Lattner 07fde9bde1 add a mayLoad property for machine instructions, a correlary to mayStore.
This is currently not set by anything.

llvm-svn: 45748
2008-01-08 18:05:21 +00:00
Chris Lattner 03ad885039 rename TargetInstrDescriptor -> TargetInstrDesc.
Make MachineInstr::getDesc return a reference instead
of a pointer, since it can never be null.

llvm-svn: 45695
2008-01-07 07:27:27 +00:00
Chris Lattner e99a6caee4 Rename all the M_* flags to be namespace qualified enums, and switch
all clients over to using predicates instead of these flags directly.
These are now private values which are only to be used to statically
initialize the tables.

llvm-svn: 45692
2008-01-07 06:42:05 +00:00
Chris Lattner f376c99ea0 rename hasVariableOperands() -> isVariadic(). Add some comments.
Evan, please review the comments I added to getNumDefs to make sure
that they are accurate, thx.

llvm-svn: 45687
2008-01-07 05:19:29 +00:00
Chris Lattner fd548c96cc Move M_* flags down in the file. Move SchedClass up in the
TargetInstrDescriptor class and shrink to 16-bits, saving a 
word in TargetInstrDescriptor.  Add some comments.

llvm-svn: 45686
2008-01-07 05:06:49 +00:00
Chris Lattner 6f8713decb the name field of instructions is never set to a non-empty string,
just unconditionally use the def name of the instruction.

llvm-svn: 45684
2008-01-07 04:57:31 +00:00
Chris Lattner e55e115616 Add predicates methods to TargetOperandInfo, and switch all clients
over to using them, instead of diddling Flags directly.  Change the
various flags from const variables to enums.

llvm-svn: 45677
2008-01-07 02:39:19 +00:00
Chris Lattner a4ce4f6987 rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate.
llvm-svn: 45667
2008-01-06 23:38:27 +00:00
Chris Lattner 10324d0175 rename isStore -> mayStore to more accurately reflect what it captures.
llvm-svn: 45656
2008-01-06 08:36:04 +00:00
Chris Lattner a348f55ec6 Change the 'isStore' inferrer to look for 'SDNPMayStore'
instead of "ISD::STORE".  This allows us to mark target-specific dag
nodes as storing (such as ppc byteswap stores).  This allows us to remove
more explicit isStore flags from the .td files.

Finally, add a warning for when a .td file contains an explicit 
isStore and tblgen is able to infer it.

llvm-svn: 45654
2008-01-06 06:44:58 +00:00
Chris Lattner 89c6566577 set the 'isstore' flag for instructions whose pattern is an
intrinsic that writes to memory.

llvm-svn: 45650
2008-01-06 05:36:50 +00:00
Chris Lattner e457fd1e9b remove some old hacky code that tried to infer whether a store
occured in a pattern, but failed miserably.  The new code works for
any instruction that has a store in its pattern, including all the 
x86 mem op mem instructions.

The only target-independent code that uses this is branch folding,
so this won't change anything in practice.

llvm-svn: 45648
2008-01-06 02:16:26 +00:00
Chris Lattner 27a4c1515a rearrange some code to allow inferring instr info from the pattern of the instr, but don't do so yet.
llvm-svn: 45647
2008-01-06 01:53:37 +00:00
Chris Lattner 85467a17ae final cleanups.
llvm-svn: 45644
2008-01-06 01:21:51 +00:00
Chris Lattner 626b89daa4 further simplifications and cleanup
llvm-svn: 45643
2008-01-06 01:20:13 +00:00
Chris Lattner 827efa451f simplify some code
llvm-svn: 45642
2008-01-06 01:12:44 +00:00
Chris Lattner e59a3c79e5 split enum emission out from InstrInfoEmitter into it's own tblgen backend.
llvm-svn: 45640
2008-01-06 00:49:05 +00:00
Chris Lattner dc3c9050f8 tblgen shouldn't include headers from llvm codegen.
llvm-svn: 45429
2007-12-30 00:25:23 +00:00
Chris Lattner 8adcd9f32e remove attributions from utils.
llvm-svn: 45419
2007-12-29 20:37:13 +00:00
Bill Wendling cb77f04e1f Add flags to indicate that there are "never" side effects or that there "may be"
side effects for machine instructions.

llvm-svn: 45022
2007-12-14 01:48:59 +00:00
Evan Cheng 687567bca5 Oops. Forgot these.
llvm-svn: 44969
2007-12-13 00:42:35 +00:00
Owen Anderson 933b5b7e62 Add a flag for indirect branch instructions.
Target maintainers: please check that the instructions for your target are correctly marked.

llvm-svn: 44012
2007-11-12 07:39:39 +00:00
Evan Cheng c9de9cec18 Added TargetInstrDescriptor::numDefs - num of results.
llvm-svn: 40709
2007-08-02 00:20:17 +00:00
Christopher Lamb cde0ee5221 Add target independent MachineInstr's to represent subreg insert/extract in MBB's. PR1350
llvm-svn: 40518
2007-07-26 07:48:21 +00:00
Evan Cheng 6e3c705d74 Try committing again. Add OptionalDefOperand. Remove clobbersPred.
llvm-svn: 38498
2007-07-10 18:05:01 +00:00
Evan Cheng 9835db562f ImmutablePredicateOperand is no more.
llvm-svn: 37963
2007-07-06 23:23:38 +00:00
Evan Cheng e32e7fb40d Instructions with ImmutablePredicateOperand aren't really predicable since their predicates are fixed at isel time.
llvm-svn: 37899
2007-07-05 07:19:29 +00:00
Dan Gohman e8c1e428f2 Revert the earlier change that removed the M_REMATERIALIZABLE machine
instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions that are only
trivially rematerializable with specific operands (i.e. constant pool
loads).

llvm-svn: 37728
2007-06-26 00:48:07 +00:00
Dan Gohman 9e82064924 Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad
with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.

llvm-svn: 37644
2007-06-19 01:48:05 +00:00
Evan Cheng a7ca624028 Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit.
llvm-svn: 37643
2007-06-19 01:26:51 +00:00
Evan Cheng 452a818c6a Add clobbersPred - instruction that clobbers condition code / register which are used to predicate instructions.
llvm-svn: 37465
2007-06-06 10:14:55 +00:00
Evan Cheng b99726d7a0 Rename M_PREDICATED to M_PREDICABLE; opcode can be specified isPredicable without having a PredicateOperand.
llvm-svn: 37116
2007-05-16 20:45:24 +00:00
Evan Cheng c0fb94596a Mark all (not just the first) predicate operand M_PREDICATE_OPERAND.
llvm-svn: 37061
2007-05-15 01:20:36 +00:00
Evan Cheng 9d7d130835 Recognize target instruction flag 'isReMaterializable'.
llvm-svn: 35159
2007-03-19 06:20:37 +00:00
Jim Laskey 214c582002 Files missing from LABEL check in.
llvm-svn: 33539
2007-01-26 17:29:20 +00:00
Bill Wendling 9bfb1e1f29 What should be the last unnecessary <iostream>s in the library.
llvm-svn: 32333
2006-12-07 22:21:48 +00:00
Evan Cheng 71adba6dce Add opcode to TargetInstrDescriptor.
llvm-svn: 31804
2006-11-17 01:46:27 +00:00
Chris Lattner c94f214d22 ADd support for adding constraints to suboperands
llvm-svn: 31748
2006-11-15 02:38:17 +00:00
Chris Lattner ba7b3673f9 allow ptr_rc to explicitly appear in an instructions operand list, it doesn't
have to be a subpart of a complex operand.

llvm-svn: 31618
2006-11-10 02:01:40 +00:00
Evan Cheng 1698c2999c Remove M_2_ADDR_FLAG.
llvm-svn: 31583
2006-11-09 02:22:54 +00:00
Chris Lattner f62138e792 Mark predicate operands as such in operand info.
llvm-svn: 31483
2006-11-06 23:53:31 +00:00
Chris Lattner 33f5a51020 simplify the way operand flags and constraints are handled, making it easier
to extend.

llvm-svn: 31481
2006-11-06 23:49:51 +00:00
Chris Lattner 8a9c91de33 recognize ppc's blr instruction as predicated
llvm-svn: 31480
2006-11-06 21:44:54 +00:00
Evan Cheng 3cb5bf721c Clean up some code.
llvm-svn: 31451
2006-11-04 09:40:23 +00:00
Evan Cheng ac79c7c4c0 Add operand constraints to TargetInstrInfo.
llvm-svn: 31333
2006-11-01 00:27:05 +00:00
Jim Laskey 4b49c23571 Eliminate data relocations by using NULL instead of global empty list.
llvm-svn: 29250
2006-07-21 21:15:20 +00:00
Jim Laskey 4e153f1b91 Use an enumeration to eliminate data relocations.
llvm-svn: 29249
2006-07-21 20:57:35 +00:00
Evan Cheng 55772ccfd6 Instructions with variable operands (variable_ops) can have a number required
operands. e.g.
def CALL32r : I<0xFF, MRM2r, (ops GR32:$dst, variable_ops),
                "call {*}$dst", [(X86call GR32:$dst)]>;
TableGen should emit operand informations for the "required" operands.

Added a target instruction info flag M_VARIABLE_OPS to indicate the target
instruction may have more operands in addition to the minimum required
operands.

llvm-svn: 28791
2006-06-15 07:22:16 +00:00
Evan Cheng d8e2f6ebc1 lib/Target/Target.td
llvm-svn: 28386
2006-05-18 20:42:07 +00:00
Evan Cheng 21c7c23d7e Noop instruction
llvm-svn: 28241
2006-05-12 07:47:00 +00:00
Evan Cheng 386fb9b0fd Set isStore of instructions with ISD::TRUNCSTORE root node.
llvm-svn: 28075
2006-05-03 02:08:34 +00:00
Chris Lattner 4b177f089e Put instruction names into the first non TargetInstrInfo namespace found.
llvm-svn: 28043
2006-05-01 23:46:16 +00:00
Evan Cheng 8e63393bc3 Formating
llvm-svn: 28036
2006-05-01 09:30:17 +00:00
Evan Cheng c2ef5e34a8 Mark instructions whose pattern is (store ...) isStore.
llvm-svn: 28032
2006-05-01 09:04:20 +00:00
Chris Lattner 778509c844 Don't fill in fields that no longer exist.
llvm-svn: 27898
2006-04-20 18:32:22 +00:00
Chris Lattner db2a5f09f1 If we want to emit things in enum order, use getInstructionsByEnumValue to
get the order, don't compute it ourselves.

Don't emit stuff like (14<<0), emit 14 instead.

Don't attempt to get target properties for builtin instructions.

llvm-svn: 25672
2006-01-27 01:44:09 +00:00
Duraid Madina 018da4f5ef almost got the HP-UX tester up.. :)
llvm-svn: 25051
2005-12-30 14:56:37 +00:00
Chris Lattner 6bc0304c91 Teach tblgen about instruction operands that have multiple MachineInstr
operands, digging into them to find register values (used on X86).  Patch
by Evan Cheng!

llvm-svn: 24424
2005-11-19 07:05:57 +00:00
Jim Laskey 802748cd61 Allow itineraries to be passed through the Target Machine.
llvm-svn: 24139
2005-11-01 20:06:59 +00:00
Jeff Cohen 9e1784d738 Keep VC++ happy.
llvm-svn: 24137
2005-11-01 18:04:06 +00:00
Jim Laskey 0433df136f Emit itinerary class in instruction info.
llvm-svn: 24122
2005-10-31 17:16:46 +00:00
Chris Lattner 742606ad30 Switch more code over to using getValueAsListOfDefs. Look at all the -'s. :)
llvm-svn: 24074
2005-10-28 22:59:53 +00:00
Chris Lattner 63dc7f569a spell this variable right
llvm-svn: 23095
2005-08-26 20:42:52 +00:00
Chris Lattner 3d9fbefbf7 Expose a new flag to TargetInstrInfo
llvm-svn: 23094
2005-08-26 20:40:46 +00:00
Chris Lattner c36c9bdb5d add a marker at the end of the instruction enum list
llvm-svn: 23090
2005-08-26 20:17:00 +00:00
Chris Lattner 96d0234845 Emit this:
static const TargetOperandInfo OperandInfo6[] = { { &PPC32::CRRCRegClass }, { 0 }, };

instead of this:

static const TargetOperandInfo OperandInfo6[] = { { PPC32::CRRCRegisterClass }, { 0 }, };

For operand information, which does not require dynamic (startup-time)
initialization.

llvm-svn: 22931
2005-08-19 20:29:14 +00:00
Chris Lattner d02bd5bb05 Emit real operand info for instructions. This currently works but is bad
in one way: the generated tables require dynamic initialization for the
register classes.  This will be fixed in a future patch.

llvm-svn: 22919
2005-08-19 18:46:26 +00:00
Chris Lattner 220d00109b For now, just emit empty operand info structures.
llvm-svn: 22910
2005-08-19 16:57:28 +00:00
Chris Lattner 511ee687e5 now that all of the targets are clean w.r.t. the number of operands for each
instruction defined, actually emit this to the InstrInfoDescriptor, which
allows an assert in the machineinstrbuilder to do some checking for us,
and is required by the dag->dag emitter

llvm-svn: 22895
2005-08-19 00:59:49 +00:00
Chris Lattner b015303c5e revert this change, which causes breakage, temporarily
llvm-svn: 22880
2005-08-18 22:12:31 +00:00
Chris Lattner 99df668f48 When emitting implicit use/def lists, only emit each unique list once. Though
LLVM is able to merge identical static const globals, GCC isn't, and this caused
some bloat in the generated data.  This has a marginal effect on PPC, shrinking
the implicit sets from 10->4, but shrinks X86 from 179 to 23, a much bigger
reduction.

This should speed up the register allocator as well by reducing the dcache
footprint for this static data.

llvm-svn: 22879
2005-08-18 21:36:47 +00:00
Chris Lattner 6f52a04fc7 Fill in the numOperands field of the TargetInstrDescriptor struct from the
.td file.

llvm-svn: 22873
2005-08-18 19:45:37 +00:00
Misha Brukman 650ba8eb56 Remove trailing whitespace
llvm-svn: 21428
2005-04-22 00:00:37 +00:00
Chris Lattner 945e8655dd Refactor code for numbering instructions into CodeGenTarget.
llvm-svn: 19758
2005-01-22 18:58:51 +00:00
Chris Lattner 733c82bfbf Expose isConvertibleToThreeAddress and isCommutable bits to the code generator.
llvm-svn: 19243
2005-01-02 02:29:04 +00:00
Nate Begeman 996ddbc98e Add support for the isLoad and isStore flags, needed by the instruction scheduler
llvm-svn: 16554
2004-09-28 21:01:45 +00:00
Chris Lattner 9b0dfa3c0d Turn the hasDelaySlot flag into the M_DELAY_SLOT_FLAG
llvm-svn: 16553
2004-09-28 18:38:01 +00:00
Chris Lattner c9d99efdd3 Do not #include files into the llvm namespace
llvm-svn: 15849
2004-08-17 03:08:28 +00:00
Chris Lattner 29d8ac77e1 Instructions no longer need to have names.
llvm-svn: 15399
2004-08-01 08:38:17 +00:00
Chris Lattner c860ecafe1 Add, and start using, the CodeGenInstruction class. This class represents
an instance of the Instruction tablegen class.

llvm-svn: 15385
2004-08-01 05:04:00 +00:00
Chris Lattner fce9603387 Rename CodeGenWrappers.(cpp|h) -> CodeGenTarget.(cpp|h)
llvm-svn: 15382
2004-08-01 04:04:35 +00:00
Chris Lattner 6847866400 Finegrainify namespacification
llvm-svn: 15381
2004-08-01 03:55:39 +00:00
Chris Lattner fd4558862c Support new flag
llvm-svn: 15355
2004-07-31 02:07:26 +00:00
Brian Gaeke 960707c335 Put all LLVM code into the llvm namespace, as per bug 109.
llvm-svn: 9903
2003-11-11 22:41:34 +00:00
John Criswell d3032037f1 Added LLVM copyright header.
llvm-svn: 9305
2003-10-20 20:20:30 +00:00
Alkis Evlogimenos 5f1f337d95 Change MRegisterDesc::AliasSet, TargetInstrDescriptor::ImplicitDefs
and TargetInstrDescriptor::ImplicitUses to always point to a null
terminated array and never be null. So there is no need to check for
pointer validity when iterating over those sets. Code that looked
like:

if (const unsigned* AS = TID.ImplicitDefs) {
  for (int i = 0; AS[i]; ++i) {
    // use AS[i]
  }
}

was changed to:

for (const unsigned* AS = TID.ImplicitDefs; *AS; ++AS) {
  // use *AS
}

llvm-svn: 8960
2003-10-08 05:20:08 +00:00
Chris Lattner f5bd1b7a8e Move support/tools/* back into utils
llvm-svn: 8875
2003-10-05 19:27:59 +00:00