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58 Commits

Author SHA1 Message Date
Evan Cheng c8bed03349 In thumb2 mode, add pc is unpredictable. Use add + mov pc instead (that is until more optimization goes in). 
llvm-svn: 77364
 2009-07-28 20:53:24 +00:00
David Goodwin 68bb69d6e3 Remove support for ORN to workaround <rdar://problem/7096522>. 
llvm-svn: 77363
 2009-07-28 20:51:25 +00:00
David Goodwin 865c6298d7 Add workaround for <rdar://problem/7098328>. 
llvm-svn: 77340
 2009-07-28 18:15:38 +00:00
David Goodwin e82862e24e Add Thumb-2 patterns for ARMsrl_flag and ARMsra_flag. 
llvm-svn: 77329
 2009-07-28 17:06:49 +00:00
Evan Cheng 780748d565 - More refactoring. This gets rid of all of the getOpcode calls. 
- This change also makes it possible to switch between ARM / Thumb on a
  per-function basis.
- Fixed thumb2 routine which expand reg + arbitrary immediate. It was using
  using ARM so_imm logic.
- Use movw and movt to do reg + imm when profitable.
- Other code clean ups and minor optimizations.

llvm-svn: 77300
 2009-07-28 05:48:47 +00:00
David Goodwin 57b51d9f82 ORN does not require (and can not have) the ".w" suffix. "Orthogonality" is a dirty word at ARM. 
llvm-svn: 77275
 2009-07-27 23:34:12 +00:00
David Goodwin 782f242fd7 Add ".w" suffix for wide thumb-2 instructions. 
llvm-svn: 77199
 2009-07-27 16:31:55 +00:00
Evan Cheng f3a1fce8ae Change Thumb2 jumptable codegen to one that uses two level jumps: 
Before:
      adr r12, #LJTI3_0_0
      ldr pc, [r12, +r0, lsl #2]
LJTI3_0_0:
      .long    LBB3_24
      .long    LBB3_30
      .long    LBB3_31
      .long    LBB3_32

After:
      adr r12, #LJTI3_0_0
      add pc, r12, +r0, lsl #2
LJTI3_0_0:
      b.w    LBB3_24
      b.w    LBB3_30
      b.w    LBB3_31
      b.w    LBB3_32

This has several advantages.
1. This will make it easier to optimize this to a TBB / TBH instruction +
   (smaller) table.
2. This eliminate the need for ugly asm printer hack to force the address
   into thumb addresses (bit 0 is one).
3. Same codegen for pic and non-pic.
4. This eliminate the need to align the table so constantpool island pass
   won't have to over-estimate the size.

Based on my calculation, the later is probably slightly faster as well since
ldr pc with shifter address is very slow. That is, it should be a win as long
as the HW implementation can do a reasonable job of branch predict the second
branch.

llvm-svn: 77024
 2009-07-25 00:33:29 +00:00
Evan Cheng 8c8e88bd39 Remove a duplicated test. 
llvm-svn: 77020
 2009-07-25 00:24:40 +00:00
Evan Cheng aee0e1f48c Fix these tests. 
llvm-svn: 77006
 2009-07-24 22:42:22 +00:00
Evan Cheng 3990850a7d Convert a test to FileCheck. 
llvm-svn: 76954
 2009-07-24 06:01:46 +00:00
Evan Cheng dc99f07113 Thumb2 does not allow the use of "pc" register as part of the load / store address. 
llvm-svn: 76909
 2009-07-23 23:09:51 +00:00
Evan Cheng d2919a1773 Fix up ARM constant island pass for Thumb2. 
Also fixed up code to fully use the SoImm field for ADR on ARM mode.

llvm-svn: 76890
 2009-07-23 18:27:47 +00:00
Evan Cheng 38e88cb53f Do not select tSXTB / tSXTH in thumb2 mode. 
llvm-svn: 76600
 2009-07-21 18:15:26 +00:00
Evan Cheng 0d8b0cf3b8 Fix ARM isle code that optimize multiply by constants which are power-of-2 +/- 1. 
llvm-svn: 76520
 2009-07-21 00:31:12 +00:00
Anton Korobeynikov c5df7e2dc1 Emit cross regclass register moves for thumb2. 
Minor code duplication cleanup.

llvm-svn: 76124
 2009-07-16 23:26:06 +00:00
David Goodwin 72b80ac9b1 Fix detection of valid BFC immediates. 
llvm-svn: 75576
 2009-07-14 00:57:56 +00:00
Evan Cheng 017288a4fc Don't put IT instruction before conditional branches. 
llvm-svn: 75361
 2009-07-11 07:26:20 +00:00
Chris Lattner e3c4765bac convert test to use FileCheck, which is much more precise and faster than 
the previous RUN lines.  Hopefully this will be an inspiration for future
tests :)

llvm-svn: 75261
 2009-07-10 18:34:47 +00:00
Evan Cheng 0f9cce7951 Add a thumb2 pass to insert IT blocks. 
llvm-svn: 75218
 2009-07-10 01:54:42 +00:00
David Goodwin 22c2fba978 Use common code for both ARM and Thumb-2 instruction and register info. 
llvm-svn: 75067
 2009-07-08 23:10:31 +00:00
David Goodwin 121563c615 Add rev16 test... xfail for now 
llvm-svn: 75012
 2009-07-08 16:15:06 +00:00
David Goodwin af7451b674 Checkpoint Thumb2 Instr info work. Generalized base code so that it can be shared between ARM and Thumb2. Not yet activated because register information must be generalized first. 
llvm-svn: 75010
 2009-07-08 16:09:28 +00:00
Evan Cheng d0611f9a37 Add Thumb2 movcc instructions. 
llvm-svn: 74946
 2009-07-07 20:39:03 +00:00
Evan Cheng d0f6324cdc Add Thumb2 pkhbt / pkhtb. 
llvm-svn: 74895
 2009-07-07 05:35:52 +00:00
Evan Cheng b24e51e2d9 Add some more Thumb2 multiplication instructions. 
llvm-svn: 74889
 2009-07-07 01:17:28 +00:00
Evan Cheng 0e8bde5910 Add thumb2 sign / zero extend with rotate instructions. 
llvm-svn: 74755
 2009-07-03 01:43:10 +00:00
Evan Cheng 53cdf022b6 Added indexed stores. 
llvm-svn: 74740
 2009-07-03 00:06:39 +00:00
Evan Cheng 8ecd7eb3f7 Sign extending pre/post indexed loads. 
llvm-svn: 74736
 2009-07-02 23:16:11 +00:00
Evan Cheng 84c6cda2ef Thumb2 pre/post indexed loads. 
llvm-svn: 74696
 2009-07-02 07:28:31 +00:00
David Goodwin 86c7e20ca6 Add PIC load and store patterns for Thumb-2. 
llvm-svn: 74577
 2009-07-01 00:01:13 +00:00
David Goodwin d0890a2bad Add thumb-2 store word, halfword, and byte. 
llvm-svn: 74555
 2009-06-30 22:11:34 +00:00
David Goodwin 28d6d87244 Improve Thumb-2 jump table support. 
llvm-svn: 74549
 2009-06-30 19:50:22 +00:00
Evan Cheng 57726817aa A few more load instructions. 
llvm-svn: 74500
 2009-06-30 02:15:48 +00:00
David Goodwin 17512663f5 Enhance tests to include shifted-register operand testing. 
llvm-svn: 74490
 2009-06-30 01:02:20 +00:00
David Goodwin 76b37950ca Add Thumb-2 support for TEQ amd TST. 
llvm-svn: 74468
 2009-06-29 22:49:42 +00:00
David Goodwin 911edef65b Thumb-2 tests 
llvm-svn: 74464
 2009-06-29 22:25:22 +00:00
David Goodwin dbf11ba800 Rename ARMcmpNZ to ARMcmpZ and use it to represent comparisons that set only the Z flag (i.e. eq and ne). Make ARMcmpZ commutative. 
llvm-svn: 74423
 2009-06-29 15:33:01 +00:00
Evan Cheng b23b50d54d Implement Thumb2 ldr. 
After much back and forth, I decided to deviate from ARM design and split LDR into 4 instructions (r + imm12, r + imm8, r + r << imm12, constantpool). The advantage of this is 1) it follows the latest ARM technical manual, and 2) makes it easier to reduce the width of the instruction later. The down side is this creates more inconsistency between the two sub-targets. We should split ARM LDR instruction in a similar fashion later. I've added a README entry for this.

llvm-svn: 74420
 2009-06-29 07:51:04 +00:00
David Goodwin 5285817490 When possible, use "mvn ra, rb" instead of "eor ra, rb, -1" because mvn has a narrow version and eor(i) does not. 
llvm-svn: 74355
 2009-06-26 23:13:13 +00:00
David Goodwin 3aaa751712 Thumb-2 tests 
llvm-svn: 74345
 2009-06-26 22:37:07 +00:00
David Goodwin aa294c5593 Thumb-2 has CLZ. 
llvm-svn: 74322
 2009-06-26 20:47:43 +00:00
David Goodwin 35ee722d42 Use "adcs/sbcs" only when the carry-out is live, otherwise use "adc/sbc". 
llvm-svn: 74321
 2009-06-26 20:45:56 +00:00
Daniel Dunbar a720af1370 More spelling Count as count. 
llvm-svn: 74306
 2009-06-26 18:35:07 +00:00
Daniel Dunbar 6b1678d5d8 Spell Count as count. 
llvm-svn: 74298
 2009-06-26 18:21:54 +00:00
David Goodwin 3bd42afebe Add Thumb-2 tests. 
llvm-svn: 74295
 2009-06-26 18:10:30 +00:00
David Goodwin 5960e6d974 ADC used to implement adde should use "adcs" opcode instead of "adc". 
llvm-svn: 74293
 2009-06-26 18:07:25 +00:00
David Goodwin 34f7ede9e7 ORN and BIC tests. 
llvm-svn: 74289
 2009-06-26 16:20:06 +00:00
David Goodwin 0377f737ff Currently there is a pattern for the thumb-2 MOV 16-bit immediate instruction. That instruction cannot write the flags so it should use T2I instead of T2sI. 
Also, added a pattern for the thumb-2 MOV of shifted immediate since that can encode immediates not encodable by the 16-bit immediate.

llvm-svn: 74288
 2009-06-26 16:10:07 +00:00
Evan Cheng 7779156b39 Fix tests: Count -> count. 
llvm-svn: 74282
 2009-06-26 07:05:57 +00:00