llvm-project

Commit Graph

Author	SHA1	Message	Date
Simon Pilgrim	db73dbcc7c	[SelectionDAG] Add support for BITREVERSE constant folding We were relying on constant folding of the legalized instructions to do what constant folding we had previously llvm-svn: 292114	2017-01-16 13:39:00 +00:00
James Molloy	b564098c62	[ARM] Replace ARMISD::RBIT with ISD::BITREVERSE ISD::BITREVERSE matches "rbit" completely, so remove ARMISD::RBIT and mark ISD::BITREVERSE as legal, adding a test for lowering. llvm-svn: 253047	2015-11-13 16:05:22 +00:00
Yi Kong	c655f0c898	ARM: Fix codegen for rbit intrinsic LLVM generates illegal `rbit r0, #352` instruction for rbit intrinsic. According to ARM ARM, rbit only takes register as argument, not immediate. The correct instruction should be rbit <Rd>, <Rm>. The bug was originally introduced in r211057. Differential Revision: http://reviews.llvm.org/D4980 llvm-svn: 216064	2014-08-20 10:40:20 +00:00

Author

SHA1

Message

Date

Simon Pilgrim

db73dbcc7c

[SelectionDAG] Add support for BITREVERSE constant folding

We were relying on constant folding of the legalized instructions to do what constant folding we had previously

llvm-svn: 292114

2017-01-16 13:39:00 +00:00

James Molloy

b564098c62

[ARM] Replace ARMISD::RBIT with ISD::BITREVERSE

ISD::BITREVERSE matches "rbit" completely, so remove ARMISD::RBIT and mark ISD::BITREVERSE as legal, adding a test for lowering.

llvm-svn: 253047

2015-11-13 16:05:22 +00:00

Yi Kong

c655f0c898

ARM: Fix codegen for rbit intrinsic

LLVM generates illegal `rbit r0, #352` instruction for rbit intrinsic.
According to ARM ARM, rbit only takes register as argument, not immediate.
The correct instruction should be rbit <Rd>, <Rm>.

The bug was originally introduced in r211057.

Differential Revision: http://reviews.llvm.org/D4980

llvm-svn: 216064

2014-08-20 10:40:20 +00:00

3 Commits