Commit Graph

231595 Commits

Author SHA1 Message Date
Xinliang David Li b628dd3568 [profile] Static counter allocation for value profiling (part-1)
Differential Revision: http://reviews.llvm.org/D20459

llvm-svn: 270336
2016-05-21 22:55:34 +00:00
Craig Topper 3fc3b4453d [X86] Remove unnecessary alignment check on patterns that use VEXTRACTF128 for integer types when only AVX1 is supported.
llvm-svn: 270335
2016-05-21 22:50:18 +00:00
Craig Topper db960eddfa [AVX512] Add patterns for extracting subvectors and storing to memory.
llvm-svn: 270334
2016-05-21 22:50:14 +00:00
Craig Topper 03b849eb44 [AVX512] Capitalize the Z in VEXTRACTPSzmr. Lowercase z has been primarily used to indicating the zero masking behavior which is not the case here. NFC
llvm-svn: 270333
2016-05-21 22:50:11 +00:00
Craig Topper d5da6a39f2 [AVX512] Rename vector extract instructions so 'mr' intead of 'rm' to reflect the fact that memory is the destination.
llvm-svn: 270332
2016-05-21 22:50:09 +00:00
Craig Topper 08a6857c82 [AVX512] Fix copy/paste mistake a I made in a comment.
llvm-svn: 270331
2016-05-21 22:50:04 +00:00
Simon Pilgrim 28666ce778 [X86][AVX] Ensure zero-extension of _mm256_extract_epi8 and _mm256_extract_epi16
Ensure _mm256_extract_epi8 and _mm256_extract_epi16 zero extend their i8/i16 result to i32. This matches _mm_extract_epi8 and _mm_extract_epi16.

Fix for PR27594

Differential Revision: http://reviews.llvm.org/D20468

llvm-svn: 270330
2016-05-21 21:14:35 +00:00
Chad Rosier 56def258e3 Fix 80-column violation.
llvm-svn: 270329
2016-05-21 21:12:06 +00:00
Simon Atanasyan 1c980ca5aa [ELF] Take into account offset in the output section when read addends for a non-alloc input section
llvm-svn: 270328
2016-05-21 19:48:54 +00:00
Rui Ueyama 4f798fc358 Use uintX_t instead of unsigned.
This fixes a potential bug when cross linking very large executables
on LLP64 machines such as Windows. On such platform, uintX_t is 64 bits
while unsigned is 32 bits.

llvm-svn: 270327
2016-05-21 19:22:46 +00:00
Rui Ueyama 46207cc1c9 Remove dead variable.
llvm-svn: 270326
2016-05-21 19:08:39 +00:00
Rui Ueyama 6bf7d915ac Split EHOutputSection<ELFT>::addSectionAux. NFC.
llvm-svn: 270325
2016-05-21 19:06:33 +00:00
Rui Ueyama c0449a6d84 Swap the arguments of writeAlignedCieOrFde. NFC.
Most functions take destination buffers as the first arguments
just like memcpy, so this order is easier to read.
Also simplified the function.

llvm-svn: 270324
2016-05-21 18:10:13 +00:00
Hal Finkel 7b1b3daf6e [LiveIntervalAnalysis] Don't dereference an end iterator in repairIntervalsInRange
This fixes a bug introduced in:

  r262115 - CodeGen: Take MachineInstr& in SlotIndexes and LiveIntervals, NFC

The iterator End here might == MBB->end(), and so we can't unconditionally
dereference it. This often goes unnoticed (I don't have a test case that always
crashes, and ASAN does not catch it either) because the function call arguments are
turned right back into iterators. MachineInstrBundleIterator's constructor,
however, does have an assert which might randomly fire.

llvm-svn: 270323
2016-05-21 16:03:50 +00:00
Michael Zuckerman a63a129749 [Clang][AVX512][intrinsics] Fix rcp and sqrt intrinsics.
Differential Revision: http://reviews.llvm.org/D20438

llvm-svn: 270322
2016-05-21 14:44:18 +00:00
Michael Zuckerman 11b55b29d1 [Clang][AVX512][intrinsics] Fix vscalef intrinsics.
Differential Revision: http://reviews.llvm.org/D20324

llvm-svn: 270321
2016-05-21 11:09:53 +00:00
George Rimar c13c59afa7 [llvm-readobj] - Teach readobj to recognize SHF_COMPRESSED flag.
Main problem here was that SHF_COMPRESSED has the same value with
XCORE_SHF_CP_SECTION, which was included as standart (common) flag.
As far I understand xCore is a family of controllers and it that
means it's constant should be processed separately,
only if e_machine == EM_XCORE, otherwise llvm-readobj would output
different constants twice for compressed section:

Flags [
..
SHF_COMPRESSED (0x800)
..
XCORE_SHF_CP_SECTION (0x800)
..
]

what probably does not make sence if you're not working with xcore file.

Differential revision: http://reviews.llvm.org/D20273

llvm-svn: 270320
2016-05-21 10:16:58 +00:00
Kuba Brecka 0287e17d09 [tsan] Don't abort when a deadlock detector finds a mutex cycle longer than 10
In one of the already existing apps that I'm testing TSan on, I really see a mutex path that is longer than 10 (but not by much, something like 11-13 actually). Let's raise this to 20 and weaken the assertion so we don't crash.

Differential Revision: http://reviews.llvm.org/D20427

llvm-svn: 270319
2016-05-21 08:31:13 +00:00
Craig Topper 02626c076b [AVX512] Add patterns for VEXTRACT v16i16->v8i16 and v32i8->v16i8. Disable AVX2 versions of vector extract when AVX512VL is enabled.
llvm-svn: 270318
2016-05-21 07:08:56 +00:00
Craig Topper 22ae353207 [AVX512] Disable AVX2 VPERMD, VPERMQ, VPERMPS, and VPERMPD patterns when AVX512VL is enabled. Also add shuffle comment printing for AVX512VL VPERMPD/VPERMQ to keep some tests that now use these instructions instead of the AVX2 ones.
llvm-svn: 270317
2016-05-21 06:07:18 +00:00
Craig Topper 6be70deda3 [AVX512] Disable AVX/AVX2 VBROADCASTSS/VBROADCASTSD patterns when AVX512VL is enabled.
llvm-svn: 270316
2016-05-21 05:47:25 +00:00
Craig Topper 1a23a521bb [AVX512] Use update_llc_test_checks to update some tests so we can see all the instruction encodings and ensure everything is with EVEX.
llvm-svn: 270315
2016-05-21 05:46:58 +00:00
David Majnemer 9f92f4c497 [SimplifyCFG] Remove cleanuppads which are empty except for calls to lifetime.end
A cleanuppad is not cheap, they turn into many instructions and result
in additional spills and fills.  It is not worth keeping a cleanuppad
around if all it does is hold a lifetime.end instruction.

N.B.  We first try to merge the cleanuppad with another cleanuppad to
avoid dropping the lifetime and debug info markers.

llvm-svn: 270314
2016-05-21 05:12:32 +00:00
Craig Topper 73f48f4662 [AVX512] Fix test cases I missed in r270311.
llvm-svn: 270313
2016-05-21 03:59:55 +00:00
Matt Arsenault 7f9eabd2c2 AMDGPU: Define priorities for register classes
Allocating larger register classes first should give better allocation
results (and more importantly for myself, make the lit tests more stable
with respect to scheduler changes).

Patch by Matthias Braun

llvm-svn: 270312
2016-05-21 03:55:07 +00:00
Craig Topper 97565ded80 [AVX512] Disable AVX/AVX2 patterns for VPSADBW and VPMULUDQ when the AVX512VL/AVX512BWI equivalents are available.
llvm-svn: 270311
2016-05-21 03:52:32 +00:00
Craig Topper b395105584 [X86] Convert some SSE2/AVX2 intrinsics to ISD opcodes during lowering instead of pattern matching the intrinsics. This unifies handling with AVX512 and allows these intrinsics to select EVEX encoded instructions to increase available registers.
llvm-svn: 270310
2016-05-21 03:52:28 +00:00
Sanjoy Das c5b1169de2 [IRCE] Don't use an allocator for range checks; NFC
The InductiveRangeCheck struct is only five words long; so passing these
around value is fine.  The allocator makes the code look more complex
than it is.

llvm-svn: 270309
2016-05-21 02:52:13 +00:00
Sanjoy Das 59776734a3 [IRCE] Don't pass IRBuilder<> where unnecessary; NFC
llvm-svn: 270308
2016-05-21 02:31:51 +00:00
Matt Arsenault 71e6676169 AMDGPU: Cleanup lowering actions
These are kind of a mess and hard to follow, particularly
for loads and stores. Fix various redundant, unnecessary
and dead settings.

llvm-svn: 270307
2016-05-21 02:27:49 +00:00
Sanjoy Das be6c7a12cb [GuardWidening] Fix incorrect use of remove_if
I had used `std::remove_if` under the assumption that it moves the
predicate matching elements to the end, but actaully the elements
remaining towards the end (after the iterator returned by
`std::remove_if`) are indeterminate.  Fix the bug (and make the code
more straightforward) by using a temporary SmallVector, and add a test
case demonstrating the issue.

llvm-svn: 270306
2016-05-21 02:24:44 +00:00
Matt Arsenault 81a709503d AMDGPU: Fix high bits after division optimization
This is essentially doing a 24-bit signed division with FP.
We need to truncate to the N bit result.

llvm-svn: 270305
2016-05-21 01:53:33 +00:00
Quentin Colombet f2723a2a91 [RegBankSelect] Compute the repairing cost for copies.
Prior to this patch, we were using 1 for all the repairing costs.
Now, we use the information from the target to get this information.

llvm-svn: 270304
2016-05-21 01:43:25 +00:00
Quentin Colombet f57d4a9ee7 [RegisterBankInfo] Fix the initialization of the map VT to RegBank.
Prior to this patch we could have read uninitialized memory.

llvm-svn: 270303
2016-05-21 01:41:17 +00:00
Dylan McKay 52ed0aa203 [AVR] Add AVRMCAsmInfo
llvm-svn: 270302
2016-05-21 01:06:37 +00:00
Matt Arsenault b6e1cc2a92 AMDGPU: Fix verifier error when spilling SGPRs
The current SGPR spilling test does not stress this
because it is using s_buffer_load instructions to
increase SGPR pressure and spill, but their output
operands have the same SReg_32_XM0 constraint. This fixes
an error when the SReg_32 output from most instructions
is spilled.

llvm-svn: 270301
2016-05-21 00:53:42 +00:00
Matt Arsenault 8f5e008534 AMDGPU: Fix relationship between SReg_32 and SReg_32_XM0
llvm-svn: 270300
2016-05-21 00:53:28 +00:00
Chris Bieneman f236347f54 Fix implicit type conversion. NFC.
llvm-svn: 270299
2016-05-21 00:36:47 +00:00
Dylan McKay 28ae31731e [AVR] Fix header files in MCTargetDesc
Everything now compiles successfully, but there are still undefined
references.

llvm-svn: 270298
2016-05-21 00:35:07 +00:00
Matt Arsenault 4945905f5f AMDGPU: Handle cbranch vccz/vccnz
llvm-svn: 270297
2016-05-21 00:29:40 +00:00
Matt Arsenault 72fcd5f597 AMDGPU: Implement ReverseBranchCondition
llvm-svn: 270296
2016-05-21 00:29:34 +00:00
Matt Arsenault 6d09380532 AMDGPU: Implement AnalyzeBranch
Original patch by Tom Stellard

llvm-svn: 270295
2016-05-21 00:29:27 +00:00
Dan Gohman b7c2400fa7 [WebAssembly] Optimize away return instructions using fallthroughs.
This saves a small amount of code size, and is a first small step toward
passing values on the stack across block boundaries.

Differential Review: http://reviews.llvm.org/D20450

llvm-svn: 270294
2016-05-21 00:21:56 +00:00
Matt Arsenault 2907e51246 Fix constant folding of addrspacecast of null
This should not be making assumptions on the value of
the casted pointer.

llvm-svn: 270293
2016-05-21 00:14:04 +00:00
Dylan McKay be8e2e0fa8 [AVR] Fix signuature of AVRTargetMachine constructor
llvm-svn: 270292
2016-05-20 23:39:04 +00:00
Matthias Braun 71f9564e7f LiveIntervalAnalysis: Rework constructMainRangeFromSubranges()
We now use LiveRangeCalc::extendToUses() instead of a specially designed
algorithm in constructMainRangeFromSubranges():
- The original motivation for constructMainRangeFromSubranges() were
  differences between the main liverange and subranges because of hidden
  dead definitions. This case however cannot happen anymore with the
  DetectDeadLaneMasks pass in place.
- It simplifies the code.
- This fixes a longstanding bug where we did not properly create new SSA
  values on merging control flow (the MachineVerifier missed most of
  these cases).
- Move constructMainRangeFromSubranges() to LiveIntervalAnalysis and
  LiveRangeCalc to better match the implementation/available helper
  functions.

This re-applies r269016. The fixes from r270290 and r270259 should avoid
the machine verifier problems this time.

llvm-svn: 270291
2016-05-20 23:14:56 +00:00
Matthias Braun e29b7689bd MachineVerifier: subregs so not require defs/valnos on every path
It is fine for subregister ranges to be undefined on some CFG paths as
we may have a "vregX:other_subreg<read-undef> =" def on that path. We
do not (and should not) have live segments for the subregister ranges.
The MachineVerifier should not complain about this.

This is a slight variant of http://llvm.org/PR27705

llvm-svn: 270290
2016-05-20 23:02:13 +00:00
Rui Ueyama 2a58779198 Fix struct member names and simplify. NFC.
llvm-svn: 270289
2016-05-20 22:59:05 +00:00
Alexander Kornienko 1c6d827015 Fix docs
llvm-svn: 270288
2016-05-20 22:42:03 +00:00
Tim Shen 95e84c5123 [PowerPC] Add a testcase for TCO on string rvo function
Differential Revision: http://reviews.llvm.org/D20311

llvm-svn: 270287
2016-05-20 22:42:01 +00:00