Commit Graph

2828 Commits

Author SHA1 Message Date
Tim Northover 1744d0ad83 ARM: allow .thumb_func to be separated from symbol definition
When assembling, a .thumb_func directive is supposed to be applicable to the
next symbol definition, even if there are intervening directives. We were
racing ahead to try and find it, and this commit should fix the issue.

Patch by Gabor Ballabas

llvm-svn: 193403
2013-10-25 12:49:50 +00:00
Tim Northover 41d2049180 ARM: tweak test to pass on all platforms
A TableGen indeterminacy means that the reason for the failure can
vary, and Windows gets the other option.

llvm-svn: 193394
2013-10-25 07:34:56 +00:00
Tim Northover 5620faf771 ARM: Mark double-precision instructions as such
This prevents us from silently accepting invalid instructions on (for example)
Cortex-M4 with just single-precision VFP support.

No tests for the extra Pat Requires because they're essentially assertions: the
affected code should have been lowered to libcalls before ISel.

rdar://problem/15302004

llvm-svn: 193354
2013-10-24 15:49:39 +00:00
Tim Northover 225bcbbe71 ARM: add a couple more NEON predicates.
The fused multiply instructions were added in VFPv4 but are still NEON
instructions, in particular they shouldn't be available on a Cortex-M4 not
matter how floaty it is.

llvm-svn: 193342
2013-10-24 12:48:05 +00:00
Tim Northover 64dacb2b8a ARM: mark various aliases with their architecture requirements.
If an alias inherits directly from InstAlias then it doesn't get any default
"Requires" values, so llvm-mc will allow it even on architectures that don't
support the underlying instruction.

This tidies up the obvious VFP and NEON cases I found.

llvm-svn: 193340
2013-10-24 12:22:58 +00:00
Zoran Jovanovic 2f0a712e18 Added tests for microMIPS relocations 1.
llvm-svn: 193332
2013-10-24 10:55:00 +00:00
Tim Northover 741e6ef4d4 ARM: fix assert on unpredictable POP instruction.
POP instructions are aliased to the ARM LDM variants but have different syntax.
This caused two problems: we tried to access a non-existent operand to annotate
the '!', and the error message didn't make much sense.

With some vigorous hand-waving in the error message both problems can be
fixed.

llvm-svn: 193322
2013-10-24 09:37:18 +00:00
Matheus Almeida be8681b461 [mips][msa] Direct Object Emission support for the LSA instruction.
llvm-svn: 193240
2013-10-23 13:20:07 +00:00
Artyom Skrobov fc12e7016c Make ARM hint ranges consistent, and add tests for these ranges
llvm-svn: 193238
2013-10-23 10:14:40 +00:00
David Blaikie 15b25dffc3 MC: Support multiple sections with the same name in the same comdat group
Code review by Eric Christopher and Rafael Espindola.

llvm-svn: 193209
2013-10-22 23:41:52 +00:00
Tim Northover 08a8660260 ARM: provide diagnostics on more writeback LDM/STM instructions
The set of circumstances where the writeback register is allowed to be in the
list of registers is rather baroque, but I think this implements them all on
the assembly parsing side.

For disassembly, we still warn about an ARM-mode LDM even if the architecture
revision is < v7 (the required architecture information isn't available). It's
a silly instruction anyway, so hopefully no-one will mind.

rdar://problem/15223374

llvm-svn: 193185
2013-10-22 19:00:39 +00:00
Matheus Almeida eb68d9d985 [mips][msa] Direct Object Emission support for conditional branches.
These branches have a 16-bit offset (R_MIPS_PC16).

List of conditional branch instructions:
bnz.{b,h,w,d}
bnz.v
bz.{b,h,w,d}
bz.v

llvm-svn: 193157
2013-10-22 09:43:32 +00:00
Matheus Almeida fe0bf9f618 [mips][msa] Direct Object Emission support for LD/ST instructions.
llvm-svn: 193082
2013-10-21 13:07:13 +00:00
Matheus Almeida 8ddad15177 [mips][msa] Direct Object Emission support for LDI instructions.
llvm-svn: 193081
2013-10-21 12:56:20 +00:00
Matheus Almeida 83d797de4a [mips][msa] Direct Object Emission support for MOVE.v.
llvm-svn: 193080
2013-10-21 12:43:54 +00:00
Matheus Almeida a591fdc63c [mips][msa] Direct Object Emission support for CTCMSA and CFCMSA.
These instructions are logically related as they allow read/write of MSA control registers.
Currently MSA control registers are emitted by number but hopefully that will change as soon 
as GAS starts accepting them by name as that would make the assembly easier to read.

llvm-svn: 193078
2013-10-21 12:26:50 +00:00
Matheus Almeida 5798c6f3bb [mips][msa] Direct Object Emission of SPLAT instruction.
llvm-svn: 193077
2013-10-21 12:07:26 +00:00
Matheus Almeida 70fbf77546 [mips][msa] Fix definition of SLD instruction.
The second parameter of the SLD intrinsic is the number of columns (GPR) to 
slide left the source array.

llvm-svn: 193076
2013-10-21 11:47:56 +00:00
Peter Collingbourne 588009e484 Emit DWARF line entries for all data in the instruction stream.
r182712 attempted to do this, but it failed to handle data emitted via
EmitBytes.

llvm-svn: 193041
2013-10-20 02:16:18 +00:00
Hans Wennborg ce69d77cec MC asm parser: allow ?'s in symbol names, and handle @'s in names in MS asm
This is another (final?) stab at making us able to parse our own asm output
on Windows.

Symbols on Windows often contain @'s and ?'s in their names. Our asm parser
didn't like this. ?'s were not allowed, and @'s were intepreted as trying to
reference PLT/GOT/etc.

We can't just add quotes around the bad names, since e.g. for MinGW, we use gas
to assemble, and it doesn't like quotes in some places (notably in .def
directives).

This commit makes us allow ?'s in symbol names, and @'s in symbol names for MS
assembly.

Differential Revision: http://llvm-reviews.chandlerc.com/D1978

llvm-svn: 193000
2013-10-18 20:46:28 +00:00
Richard Barton 87dacc38b8 Add hint disassembly syntax for 16-bit Thumb hint instructions.
Patch by Artyom Skrobov

llvm-svn: 192972
2013-10-18 14:09:49 +00:00
Chad Rosier fe2f58c8a1 [AArch64] Add support for NEON scalar extract narrow instructions.
llvm-svn: 192970
2013-10-18 14:03:24 +00:00
Silviu Baranga 314e58fdcc Add hardware division as a default feature on Cortex-A15. Also add test cases to check this, and change diagnostics for the hwdiv-arm feature to something useful.
llvm-svn: 192963
2013-10-18 10:18:40 +00:00
Hans Wennborg 7ddcdc82a5 Revert "Re-commit r192758 - MC: quote tricky symbol names in asm output"
This caused the clang-native-mingw32-win7 buildbot to break.

The assembler was complaining about the following lines that were showing up
in the asm for CrashRecoveryContext.cpp:

  movl  $"__ZL16ExceptionHandlerP19_EXCEPTION_POINTERS@4", 4(%eax)
  calll "_AddVectoredExceptionHandler@8"
  .def   "__ZL16ExceptionHandlerP19_EXCEPTION_POINTERS@4";
  "__ZL16ExceptionHandlerP19_EXCEPTION_POINTERS@4":
  calll "_RemoveVectoredExceptionHandler@4"

Reverting for now.

llvm-svn: 192940
2013-10-18 02:14:40 +00:00
Chad Rosier 37d29173aa [AArch64] Add support for NEON scalar three register different instruction
class.  The instruction class includes the signed saturating doubling
multiply-add long, signed saturating doubling multiply-subtract long, and
the signed saturating doubling multiply long instructions.

llvm-svn: 192908
2013-10-17 18:12:29 +00:00
Hans Wennborg 69918bccab Re-commit r192758 - MC: quote tricky symbol names in asm output
The reason this got reverted was that the @feat.00 symbol which was emitted
for every TU became quoted, and on cygwin/mingw we use the gas assembler which
couldn't handle the quotes.

This commit fixes the problem by only emitting @feat.00 for win32, where we use
clang -cc1as to assemble. gas would just drop this symbol anyway, so there is no
loss there.

With @feat.00 gone, there shouldn't be quoted symbols showing up on cygwin since
it uses the Itanium ABI, which doesn't put these funny characters in symbols.

> Because of win32 mangling, we produce symbol and section names with
> funny characters in them, most notably @ characters.
>
> MC would choke on trying to parse its own assembly output. This patch addresses
> that by:
>
> - Making @ trigger quoting of symbol names
> - Also quote section names in the same way
> - Just parse section names like other identifiers (to allow for quotes)
> - Don't assume @ signifies a symbol variant if it is in a string.

llvm-svn: 192859
2013-10-17 01:13:02 +00:00
Chad Rosier 846a72539c [AArch64] Add support for NEON scalar negate instruction.
llvm-svn: 192843
2013-10-16 21:04:39 +00:00
Chad Rosier 175601d997 [AArch64] Add support for NEON scalar absolute value instruction.
llvm-svn: 192842
2013-10-16 21:04:34 +00:00
Chad Rosier abe458d0bf Update comment.
llvm-svn: 192806
2013-10-16 16:30:10 +00:00
Chad Rosier 178b1cefc7 [AArch64] Add support for NEON scalar signed saturating accumulated of unsigned
value and unsigned saturating accumulate of signed value instructions.

llvm-svn: 192800
2013-10-16 16:09:02 +00:00
NAKAMURA Takumi 272416fda9 Revert r192758 (and r192759), "MC: Better handling of tricky symbol and section names"
GNU AS didn't like quotes in symbol names.

    Error: junk at end of line, first unrecognized character is `"'

        .def "@feat.00";
        "@feat.00" = 1

Reproduced on Cygwin's 2.23.52.20130309 and mingw32's 2.20.1.20100303.

llvm-svn: 192775
2013-10-16 08:22:49 +00:00
Hans Wennborg 6468493250 dos2unix on quoted-names.ll
llvm-svn: 192759
2013-10-16 01:22:07 +00:00
Hans Wennborg d34cf14339 MC: Better handling of tricky symbol and section names
Because of win32 mangling, we produce symbol and section names with
funny characters in them, most notably @ characters.

MC would choke on trying to parse its own assembly output. This patch addresses
that by:

- Making @ trigger quoting of symbol names
- Also quote section names in the same way
- Just parse section names like other identifiers (to allow for quotes)
- Don't assume @ signifies a symbol variant if it is in a string.

Differential Revision: http://llvm-reviews.chandlerc.com/D1945

llvm-svn: 192758
2013-10-16 01:20:40 +00:00
Chad Rosier 9d51708677 [AArch64] Add support for NEON scalar signed saturating absolute value and
scalar signed saturating negate instructions.

llvm-svn: 192733
2013-10-15 21:18:44 +00:00
Akira Hatanaka 8368b3b3df [mips] Set HI/LO registers' HWEncoding field.
llvm-svn: 192661
2013-10-15 01:00:00 +00:00
Chad Rosier d1f40d760a [AArch64] Add support for NEON scalar integer compare instructions.
llvm-svn: 192596
2013-10-14 14:37:20 +00:00
Bernard Ogden 4400cde89a Add subtarget feature support for Cortex-A53
Some previous implicit defaults have changed, for example FP and NEON
are now on by default.

llvm-svn: 192590
2013-10-14 13:16:57 +00:00
Matheus Almeida 2102188cfc [mips][msa] Direct Object Emission support for BIT instructions.
List of instructions:
bclri.{b,h,w,d}
binsli.{b,h,w,d}
binsri.{b,h,w,d}
bnegi.{b,h,w,d}
bseti.{b,h,w,d}
sat_s.{b,h,w,d}
sat_u.{b,h,w,d}
slli.{b,h,w,d}
srai.{b,h,w,d}
srari.{b,h,w,d}
srli.{b,h,w,d}
srlri.{b,h,w,d}

llvm-svn: 192589
2013-10-14 13:07:39 +00:00
Matheus Almeida 5be0cd8720 [mips][msa] Direct Object Emission support for VEC instructions.
List of instructions:
and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v.

llvm-svn: 192588
2013-10-14 12:57:18 +00:00
Matheus Almeida 7d65ea76ea [mips][msa] Direct Object Emission of INSVE.{b,h,w,d}.
llvm-svn: 192587
2013-10-14 12:38:17 +00:00
Matheus Almeida bc189eb318 [mips][msa] Direct Object Emission for the majority of the ELM instructions.
List of instructions:
copy_s.{b,h,w}
copy_u.{b,h,w}
sldi.{b,h,w,d}
splati.{b,h,w,d}

llvm-svn: 192586
2013-10-14 12:22:43 +00:00
Matheus Almeida b74293dc55 [mips][msa] Direct Object Emission of INSERT.{B,H,W} instruction.
INSERT is the first type of MSA instruction that requires a change to the way
MSA registers are parsed. This happens because MSA registers may be suffixed by
an index in the form of an immediate or a general purpose register. The changes
to parseMSARegs reflect that requirement.

llvm-svn: 192582
2013-10-14 11:49:30 +00:00
Craig Topper a422b09ae3 Allow pinsrw/pinsrb/pextrb/pextrw/movmskps/movmskpd/pmovmskb/extractps instructions to parse either GR32 or GR64 without resorting to duplicating instructions.
llvm-svn: 192567
2013-10-14 04:55:01 +00:00
Craig Topper 4432208884 Add disassembler support for SSE4.1 register/register form of PEXTRW. There is a shorter encoding that was part of SSE2, but a memory form was added in SSE4.1. This is the register form of that encoding.
llvm-svn: 192566
2013-10-14 01:42:32 +00:00
Craig Topper 7158745e55 Mark MOVMSKPS/MOVMSKPD/VPINSRWrr64i as AsmParserOnly to remove them from the disassembler tables. Add PINSRWrr64i to complement the AVX version.
llvm-svn: 192565
2013-10-14 01:21:22 +00:00
Benjamin Kramer 8a37f63714 Mips: Disassemble sign-extended 64 bit immediates properly.
This doesn't change the meaning of the output, but makes look right. PR17539.

llvm-svn: 192483
2013-10-11 19:05:08 +00:00
Amara Emerson ac6950863f [ARM] Fix FP ABI attributes with no VFP enabled.
llvm-svn: 192458
2013-10-11 16:03:43 +00:00
Matheus Almeida 3372c6adb1 This reverts 192447 because of compiler warning generated on darwin build.
llvm-svn: 192451
2013-10-11 13:58:32 +00:00
Matheus Almeida 599446af66 This reverts r192449 because of compiler warning generated on darwin build.
llvm-svn: 192450
2013-10-11 13:56:12 +00:00
Matheus Almeida aa5138b538 [mips][msa] Direct Object Emission for the majority of the ELM instructions.
llvm-svn: 192449
2013-10-11 13:39:49 +00:00