Commit Graph

29 Commits

Author SHA1 Message Date
Fangrui Song be9f363704 [AVRInstPrinter] printOperand: support llvm-objdump --print-imm-hex
Differential Revision: https://reviews.llvm.org/D83634
2020-07-12 08:14:52 -07:00
Ayke van Laethem eac4a60154
[AVR] Disassemble double register instructions
Add disassembly support for the movw, adiw, and sbiw instructions.

I had previously committed test cases for the adiw and sbiw
instructions, but had accidentally made them not runnable so they were
skipped all this time. Oops. This patch fixes that by adding support for
disassembling those instructions.

Differential Revision: https://reviews.llvm.org/D82093
2020-06-23 02:18:04 +02:00
Ayke van Laethem 9f09c29f01
[AVR] Disassemble instructions with fixed Z operand
Some instructions have a fixed Z register and don't have an explicit
register operand. This can be worked around by simply printing the
operand directly if the particular register class is detected.

The LPM and ELPM instructions also needed a custom decoder, which is
also included in this patch.

Differential Revision: https://reviews.llvm.org/D82088
2020-06-23 02:17:53 +02:00
Ayke van Laethem ec9efb856c
[AVR] Disassemble multiplication instructions
These can often only use a limited range of registers, and apparently
need special decoding support.

Differential Revision: https://reviews.llvm.org/D81971
2020-06-23 02:17:37 +02:00
Ayke van Laethem 01c2209d51
[AVR] Decode single register instructions
This is a set of instructions that take just a single register as an
operand, with no immediates. Because all instructions share the same
format, I haven't added exhaustive bit testing to all instructions but
just to the inc instruction.

Differential Revision: https://reviews.llvm.org/D81968
2020-06-23 02:17:15 +02:00
Ayke van Laethem 15bf42d503
[AVR] Implement disassembly of 32-bit instructions
This needed two fixes:

  * 32-bit instructions were read in the wrong order. The machine code
    swaps the two 16-bit instruction words, which wasn't undone when
    decoding instructions.
  * Jump and call instructions don't encode the lowest address bit,
    which is always zero. Therefore, the address needed to be shifted by
    one to fix that.

Differential Revision: https://reviews.llvm.org/D81961
2020-06-18 11:26:58 +02:00
Ayke van Laethem 1ba7809793
[AVR] Implement disassembly support for I/O instructions
The in, out, and sbi/cbi family of instructions seem to require a custom
decoder. I'm not exactly sure why and would prefer to convince TableGen
to provide the correct decoders for these, but I can't seem to convince
it to do so. They simply disassemble without any operands.

Differential Revision: https://reviews.llvm.org/D74049
2020-06-10 20:55:47 +02:00
Dylan McKay 1335737ee1 [LLVM][AVR] Support for R_AVR_6 fixup
Summary: Handle the emission of `R_AVR_6` ELF relocation type.

Reviewers: dylanmckay

Reviewed By: dylanmckay

Subscribers: hiraditya, Jim, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D78721

Patch by @LemonBoy https://reviews.llvm.org/p/LemonBoy/
2020-05-17 19:46:09 +12:00
Fangrui Song 536ba6373f [Object] Change ELFObjectFile<ELFT>::getFileFormatName() to use BFD names
Follow-up for D74433

What the function returns are almost standard BFD names, except that "ELF" is
in uppercase instead of lowercase.

This patch changes "ELF" to "elf" and changes ARM/AArch64 to use their BFD names.
MIPS and PPC64 have endianness differences as well, but this patch does not intend to address them.

Advantages:

* llvm-objdump: the "file format " line matches GNU objdump on ARM/AArch64 objects
* "file format " line can be extracted and fed into llvm-objcopy -O literally.
  (https://github.com/ClangBuiltLinux/linux/issues/779 has such a use case)

Affected tools: llvm-readobj, llvm-objdump, llvm-dwarfdump, MCJIT (internal implementation detail, not exposed)

Reviewed By: jhenderson

Differential Revision: https://reviews.llvm.org/D76046
2020-03-16 07:42:04 -07:00
Fangrui Song ecd6d7254e [test] llvm/test/: change llvm-objdump single-dash long options to double-dash options
As announced here: http://lists.llvm.org/pipermail/llvm-dev/2019-April/131786.html

Grouped option syntax (POSIX Utility Conventions) does not play well with -long-option
A subsequent change will reject -long-option.
2020-03-15 17:46:23 -07:00
Fangrui Song 71e2ca6e32 [llvm-objdump] -d: print `00000000 <foo>:` instead of `00000000 foo:`
The new behavior matches GNU objdump. A pair of angle brackets makes tests slightly easier.

`.foo:` is not unique and thus cannot be used in a `CHECK-LABEL:` directive.
Without `-LABEL`, the CHECK line can match the `Disassembly of section`
line and causes the next `CHECK-NEXT:` to fail.

```
Disassembly of section .foo:

0000000000001634 .foo:
```

Bdragon: <> has metalinguistic connotation. it just "feels right"

Reviewed By: rupprecht

Differential Revision: https://reviews.llvm.org/D75713
2020-03-05 18:05:28 -08:00
Ayke van Laethem 165f707f9d
[AVR] Don't adjust addresses by 2 for absolute values
Adjusting by 2 breaks DWARF output. With this fix, programs start to
compile and produce valid DWARF output.

Differential Revision: https://reviews.llvm.org/D74213
2020-02-26 20:32:24 +01:00
Ayke van Laethem 5b2046c95c
[AVR] Disassemble register operands
Simply by implementing a few functions I was able to correctly
disassemble a much larger amount of instructions.

Differential Revision: https://reviews.llvm.org/D74045
2020-02-24 19:35:51 +01:00
James Henderson 1e283c6028 [MC][AVR] Fix AVR test following 740bc366 2020-02-12 14:56:09 +00:00
Ayke van Laethem ea8b2cb9bf
[AVR] Add disassembly tests for supported instructions
The disassembler of the AVR backend is incomplete: most instructions do
not correctly disassemble yet.

This patch is the first in a series to add disassembly support to the
AVR backend. It starts with adding disassembler tests for instructions
that already disassemble correctly.

Differential Revision: https://reviews.llvm.org/D73911
2020-02-05 12:38:51 +01:00
David Bozier e6c55fbe01 Fixup AVR tests to reflect changes in addend format in llvm-objdump
Summary: Changes to llvm-objdump made in D69997

Reviewers: thakis, jhenderson, grimar

Reviewed By: thakis

Subscribers: dylanmckay, Jim, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D70438
2019-11-19 15:32:58 +00:00
Fangrui Song ac14f7b10c [lit] Delete empty lines at the end of lit.local.cfg NFC
llvm-svn: 363538
2019-06-17 09:51:07 +00:00
Dylan McKay 038e3b9f57 Extend the DWARFExpression address handling to support 16-bit addresses
This allows the DWARFExpression class to handle addresses without
crashing on targets with 16-bit pointers like AVR.

This is required in order to generate assembly from clang via the '-S'
flag.

This fixes an error with the following message:

clang: llvm/include/llvm/DebugInfo/DWARF/DWARFExpression.h:132: llvm::DWARFExpression::DWARFExpression(llvm::DataExtractor, uint16_t, uint8_t):
       Assertion `AddressSize == 8 || AddressSize == 4' failed.
llvm-svn: 362290
2019-06-01 09:18:26 +00:00
Dylan McKay e638a89166 [AVR] Fix 'symbol_relocations.s' MC test
This was broken in r360143, when the 'rela.' prefix was stripped from
section names.

llvm-svn: 361104
2019-05-18 16:38:48 +00:00
Dylan McKay 0154977e97 [AVR] Fix the inst-cbr test
Now that the CBR alias has lower priority than ANDI, the assembly
printer uses ANDI instead.

Original broken in r351526.

llvm-svn: 351539
2019-01-18 10:11:33 +00:00
Dylan McKay 97daa142f4 [AVR] Redefine the 'SBR' instruction as an alias
This fixes a TableGen warning about duplicate bit patterns.

SBR
===

This is an alias of 'ORI Rd, K'.

llvm-svn: 341277
2018-09-01 12:22:54 +00:00
Dylan McKay 2124bcf805 [AVR] Implement some missing code paths
This has been broken since r320009.

llvm-svn: 320348
2017-12-11 11:01:27 +00:00
Dylan McKay ba23343a45 Revert and accidentally committed revert commit
This reverts commit r320245.

llvm-svn: 320247
2017-12-09 08:01:28 +00:00
Dylan McKay f5422afdf0 Revert "[AVR] Override ParseDirective"
This reverts commit 57c16f9267969ebb09d6448607999b4a9f40c418.

llvm-svn: 320245
2017-12-09 07:51:37 +00:00
Leslie Zhai 8543d53fd9 [AVR] Override ParseDirective
Reviewers: dylanmckay, kparzysz

Reviewed By: dylanmckay

Differential Revision: https://reviews.llvm.org/D38029

llvm-svn: 320009
2017-12-07 06:56:09 +00:00
Dylan McKay d3972a8f11 [AVR] Use the short form of 'clr <reg>'
r318895 made it so that the simpler instruction aliases are printed
rather than their expanded form.

llvm-svn: 318954
2017-11-24 15:36:43 +00:00
Dylan McKay 5df526210a [AVR] Remove a bunch of now-obselete tests
The fixups in these instructions are now lowered into relocations.

llvm-svn: 306947
2017-07-01 05:23:13 +00:00
Dylan McKay 2e8718bcbb [AVR] Fix a bug so that we now emit R_AVR_16 fixups with the correct offset
Before this, the LDS/STS instructions would have their opcodes
overwritten while linking.

llvm-svn: 301782
2017-04-30 23:33:52 +00:00
Dylan McKay 3ffc449597 [AVR] Add all of the machine code test suite
Summary: This adds all of the AVR machine code tests.

Reviewers: arsenm, kparzysz

Subscribers: wdng, japaric

Differential Revision: https://reviews.llvm.org/D26387

llvm-svn: 286417
2016-11-09 23:46:25 +00:00