4a7e7620d6
[AMDGPU][MC] Improved diagnostics for instructions with missing features
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Reviewers: rampitec
Differential Revision: https://reviews.llvm.org/D88887
2020-10-07 16:31:29 +03:00
e2452f57fa
[AMDGPU][MC] Added detection of unsupported instructions
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Implemented identification of unsupported instructions; improved errors reporting.
See bug 42590.
Reviewers: rampitec
Differential Revision: https://reviews.llvm.org/D88211
2020-10-06 16:44:27 +03:00
a45cdb311f
[AMDGPU] gfx1030 test update. NFC.
2020-09-16 13:56:16 -07:00
95b7040e43
[AMDGPU][MC] Improved diagnostic messages for invalid registers
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Corrected parser to issue meaningful error messages for invalid and malformed registers.
See bug 41303: https://bugs.llvm.org/show_bug.cgi?id=41303
Reviewers: arsenm, rampitec
Differential Revision: https://reviews.llvm.org/D87234
2020-09-09 16:44:03 +03:00
ecde200209
[AMDGPU][MC] Corrected parser to avoid generation of excessive error messages
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Summary of changes:
- Changed parser to eliminate generation of excessive error messages;
- Corrected lit tests to match all expected error messages;
- Corrected lit tests to guard against unwanted extra messages (added option "--implicit-check-not=error:");
- Added missing checks and fixed some typos in tests.
See bug 46907: https://bugs.llvm.org/show_bug.cgi?id=46907
Reviewers: arsenm, rampitec
Differential Revision: https://reviews.llvm.org/D86940
2020-09-02 19:42:18 +03:00
5998baccb9
[AMDGPU][MC][GFX9+] Enabled 21-bit signed offsets for SMEM instructions
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Reviewers: arsenm, rampitec
Differential Revision: https://reviews.llvm.org/D79288
2020-05-06 14:13:10 +03:00
c43e67bfff
[AMDGPU] gfx1011/gfx1012 targets
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Differential Revision: https://reviews.llvm.org/D63307
llvm-svn: 363344
2019-06-14 00:33:31 +00:00
59399ae4cc
[AMDGPU][MC][VI][GFX9] Added s_atc_probe* instructions
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See bug 36839: https://bugs.llvm.org/show_bug.cgi?id=36839
Differential Revision: https://reviews.llvm.org/D45249
Reviewers: artem.tamazov, arsenm, timcorringham
llvm-svn: 329408
2018-04-06 15:48:39 +00:00
4732d876ee
[AMDGPU][MC][GFX9] Added s_dcache_discard* instructions
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See bug 36838: https://bugs.llvm.org/show_bug.cgi?id=36838
Differential Revision: https://reviews.llvm.org/D45247
Reviewers: artem.tamazov, arsenm, timcorringham
llvm-svn: 329397
2018-04-06 15:08:42 +00:00
6bad04ecf5
[AMDGPU][MC][GFX9] Added s_atomic_* and s_buffer_atomic_* instructions
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Fixed a bug which caused Tablegen crash.
See bug 36837: https://bugs.llvm.org/show_bug.cgi?id=36837
Differential Revision: https://reviews.llvm.org/D45085
Reviewers: artem.tamazov, arsenm, timcorringham
llvm-svn: 328983
2018-04-02 16:10:25 +00:00
f492f58182
Revert r328975, it makes TableGen assert on the bots.
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llvm-svn: 328978
2018-04-02 14:20:23 +00:00
32c450ae6a
[AMDGPU][MC][GFX9] Added s_atomic_* and s_buffer_atomic_* instructions
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See bug 36837: https://bugs.llvm.org/show_bug.cgi?id=36837
Differential Revision: https://reviews.llvm.org/D45085
Reviewers: artem.tamazov, arsenm, timcorringham
llvm-svn: 328975
2018-04-02 13:52:23 +00:00
dd2b929ffb
[AMDGPU][MC][GFX9] Added s_scratch* instructions
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See bug 36836: https://bugs.llvm.org/show_bug.cgi?id=36836
Differential Revision: https://reviews.llvm.org/D44832
Reviewers: artem.tamazov, arsenm, timcorringham
llvm-svn: 328704
2018-03-28 14:08:03 +00:00
52facf0195
AMDGPU: Allow TBA, TMA, TTMP* registers with SMEM instructions
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Fixes assembler regressions.
llvm-svn: 289230
2016-12-09 17:49:11 +00:00
83102d99ce
[AMDGPU] Disassembler: fix s_buffer_store_dword instructions
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Summary: s_buffer_store_dword instructions sdata operand was called sdst in encoding. This caused disassembler to fail.
Reviewers: tstellarAMD, vpykhtin, artem.tamazov
Subscribers: arsenm, nhaehnle, rampitec
Differential Revision: https://reviews.llvm.org/D27100
llvm-svn: 288657
2016-12-05 09:58:51 +00:00
7b6475568d
AMDGPU: Add definitions for scalar store instructions
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Also add glc bit to the scalar loads since they exist on VI
and change the caching behavior.
This currently has an assembler bug where the glc bit is incorrectly
accepted on SI/CI which do not have it.
llvm-svn: 285463
2016-10-28 21:55:15 +00:00
79af6b33e0
[AMDGPU] Assembler: SOP* instruction fixes
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s_bitset0_b64, s_bitset1_b64 has 32-bit src0, not 64-bit.
s_rfe_b64 has just one destination operand and no source.
Uncomment S_BITCMP* and S_SETVSKIP, adjust SOPC_* classes for that.
Add s_memrealtime test and change comments in smem.s to follow common style.
Change test for s_memtime to use non-zero register to make it really test encoding.
Add tests for s_buffer_load*.
Add tests for SOPC instructions (same for SI and VI)
Differential Revision: http://reviews.llvm.org/D18040
llvm-svn: 263420
2016-03-14 11:17:19 +00:00
e66621b306
AMDGPU: Add s_dcache_* instructions
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llvm-svn: 248533
2015-09-24 19:52:27 +00:00
Dmitry Preobrazhensky