0190a649e8
Mark ARM subtarget features that are available for the assembler.
...
llvm-svn: 117929
2010-11-01 16:59:54 +00:00
33fc3e095b
reapply r117858 with apparent editor malfunction fixed (somehow I
...
got a dulicated line).
llvm-svn: 117860
2010-10-31 19:10:56 +00:00
e59eef3dd1
revert r117858 while I check out a failure I missed.
...
llvm-svn: 117859
2010-10-31 19:05:32 +00:00
9293008e90
the asm matcher can't handle operands with modifiers (like ${foo:bar}).
...
Instead of silently ignoring these instructions, emit a hard error and
force the target author to either refactor the target or mark the
instruction 'isCodeGenOnly'.
Mark a few instructions in ARM and MBlaze as isCodeGenOnly the are
doing this.
llvm-svn: 117858
2010-10-31 18:48:12 +00:00
7ed597149b
Overhaul memory barriers in the ARM backend. Radar 8601999.
...
There were a number of issues to fix up here:
* The "device" argument of the llvm.memory.barrier intrinsic should be
used to distinguish the "Full System" domain from the "Inner Shareable"
domain. It has nothing to do with using DMB vs. DSB instructions.
* The compiler should never need to emit DSB instructions. Remove the
ARMISD::SYNCBARRIER node and also remove the instruction patterns for DSB.
* Merge the separate DMB/DSB instructions for options only used for the
disassembler with the default DMB/DSB instructions. Add the default
"full system" option ARM_MB::SY to the ARM_MB::MemBOpt enum.
* Add a separate ARMISD::MEMBARRIER_MCR node for subtargets that implement
a data memory barrier using the MCR instruction.
* Fix up encodings for these instructions (except MCR).
I also updated the tests and added a few new ones to check for DMB options
that were not currently being exercised.
llvm-svn: 117756
2010-10-30 00:54:37 +00:00
74ef9e184e
Encode the register list operands for ARM mode LDM/STM instructions.
...
llvm-svn: 117753
2010-10-30 00:37:59 +00:00
58018e62a8
s/getNEONVcvtImm32/getNEONVcvtImm32OpValue/ to be consistent with other operand
...
encoder functions.
llvm-svn: 117738
2010-10-29 23:19:55 +00:00
4a0c2d73c3
Convert ARM::MOVi2pieces to a true pseudo-instruction and expand it in
...
the ARMExpandPseudos pass rather than during the asm lowering.
llvm-svn: 117714
2010-10-29 21:35:25 +00:00
cb8aec8ec9
Fix typo.
...
llvm-svn: 117703
2010-10-29 20:21:49 +00:00
3b7e05bb97
ARM encoding information for CLREX, SWP and SWPB. Add comment for sjlj pseudos and a FIXME for TLS.
...
llvm-svn: 117702
2010-10-29 20:21:36 +00:00
4e57b52394
ARM mode LDREX*/STREX* binary encodings.
...
llvm-svn: 117695
2010-10-29 19:58:57 +00:00
6ae3fba7c8
Encoding information for ARM conditional move instructions.
...
llvm-svn: 117687
2010-10-29 19:28:17 +00:00
5d6f6a061b
add simple support for addrmode5 operands, allowing
...
vldr.64 to work. I have no idea if this is fully right, but
it is in the right direction.
llvm-svn: 117626
2010-10-29 00:27:31 +00:00
505607e4c6
PLD, PLDW, PLI encodings, plus refactor their use of addrmode2.
...
llvm-svn: 117571
2010-10-28 18:34:10 +00:00
ff310737e5
Re-commit 117518 and 117519 now that ARM MC test failures are out of the way.
...
llvm-svn: 117531
2010-10-28 06:47:08 +00:00
e2c211c1b9
Revert 117518 and 117519 for now. They changed scheduling and cause MC tests to fail. Ugh.
...
llvm-svn: 117520
2010-10-28 02:00:25 +00:00
ff1c862f8e
- Assign load / store with shifter op address modes the right itinerary classes.
...
- For now, loads of [r, r] addressing mode is the same as the
[r, r lsl/lsr/asr #] variants. ARMBaseInstrInfo::getOperandLatency() should
identify the former case and reduce the output latency by 1.
- Also identify [r, r << 2] case. This special form of shifter addressing mode
is "free".
llvm-svn: 117519
2010-10-28 01:49:06 +00:00
59bbc545e0
Shifter ops are not always free. Do not fold them (especially to form
...
complex load / store addressing mode) when they have higher cost and
when they have more than one use.
llvm-svn: 117509
2010-10-27 23:41:30 +00:00
338de3ee56
Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, like
...
the LDR instructions have. This makes the literal/register forms of the
instructions explicit and allows us to assign scheduling itineraries
appropriately. rdar://8477752
llvm-svn: 117505
2010-10-27 23:12:14 +00:00
fadb951e5b
Provide correct encodings for NEON vcvt, which has its own special immediate encoding
...
for specifying fractional bits for fixed point conversions.
llvm-svn: 117501
2010-10-27 22:49:00 +00:00
333b0a9e74
ARM JIT fix for LDRi12 and company.
...
llvm-svn: 117478
2010-10-27 19:55:59 +00:00
5a7c715470
Split ARM::LDRB into LDRBi12 and LDRBrs. Adjust accordingly. Continuing on
...
rdar://8477752.
llvm-svn: 117419
2010-10-27 00:19:44 +00:00
a92801b695
Since I parameterized this bit, I should probably actually use said parameter.
...
llvm-svn: 117418
2010-10-26 23:58:04 +00:00
1e4d9a17c2
First part of refactoring ARM addrmode2 (load/store) instructions to be more
...
explicit about the operands. Split out the different variants into separate
instructions. This gives us the ability to, among other things, assign
different scheduling itineraries to the variants. rdar://8477752.
llvm-svn: 117409
2010-10-26 22:37:02 +00:00
696fe9d36c
Trailing whitespace.
...
llvm-svn: 117188
2010-10-22 23:48:29 +00:00
2c9ae05c67
ARM mode encoding information for CLZ, RBIT, REV*, and PKH*.
...
llvm-svn: 117165
2010-10-22 22:12:16 +00:00
2b80543fc2
Add the encoding information for the rest of the ARM mode multiply instructions.
...
llvm-svn: 117133
2010-10-22 19:15:30 +00:00
6956a60563
More ARM multiply instuction binary encodings.
...
llvm-svn: 117121
2010-10-22 18:35:16 +00:00
f98df0849f
Parameterize a bit of ARM encoding information, simplifying some instruction
...
definitions.
llvm-svn: 117114
2010-10-22 17:42:06 +00:00
22261600a8
More ARM multiply instruction encoding information.
...
llvm-svn: 117108
2010-10-22 17:16:17 +00:00
e2ec62e252
ARM binary encoding for some of the multiply instructions.
...
llvm-svn: 117080
2010-10-21 22:52:30 +00:00
a97becfaac
ARM binary encodings for MVN variants.
...
llvm-svn: 117076
2010-10-21 22:19:32 +00:00
5edb03ee57
ARM Binary encoding information for BFC/BFI instructions.
...
llvm-svn: 117072
2010-10-21 22:03:21 +00:00
bbdc5d2ef9
Add a pre-dispatch SjLj EH hook on the unwind edge for targets to do any
...
setup they require. Use this for ARM/Darwin to rematerialize the base
pointer from the frame pointer when required. rdar://8564268
llvm-svn: 116879
2010-10-19 23:27:08 +00:00
1c6fd774f7
ARM encoding information for [SU]SAT* instructions.
...
llvm-svn: 116768
2010-10-18 23:35:38 +00:00
90f74fe16a
Encoding information for the various ARM saturating add/sub instructions.
...
llvm-svn: 116612
2010-10-15 19:49:46 +00:00
00ce8deae6
ARM binary encoding information for RSB and RSC instructions.
...
llvm-svn: 116604
2010-10-15 18:42:41 +00:00
68a335e185
ARM mode encoding information for UBFX and SBFX instructions.
...
llvm-svn: 116588
2010-10-15 17:15:16 +00:00
3b1db392fc
Remove unused ARMISD::AND selection DAG node.
...
llvm-svn: 116566
2010-10-15 04:34:40 +00:00
118c4238ff
Encoding info for extension instructions.
...
llvm-svn: 116560
2010-10-15 02:29:58 +00:00
19c6cb978b
Add missing Rd encoding for MOVs instruction.
...
llvm-svn: 116537
2010-10-14 23:28:31 +00:00
8b6a9c1574
Refactor the MOVsr[al]_flag and RRX pseudo-instructions to really be pseudos
...
and let the ARMExpandPseudoInsts pass fix them up into the real (MOVs)
instruction form.
llvm-svn: 116534
2010-10-14 22:57:13 +00:00
062749cb25
Tweak the ARM backend to use the RRX mnemonic instead of the 'mov a, b, rrx'
...
pseudonym.
llvm-svn: 116512
2010-10-14 20:43:44 +00:00
eafcb27ded
MOVi16 and MOVT ARM mode encodings.
...
llvm-svn: 116498
2010-10-14 18:54:27 +00:00
8229153629
Simplify encoding information and add 'dst' operand info for TAILJMP.
...
llvm-svn: 116488
2010-10-14 17:24:28 +00:00
348013f829
Add a FIXME.
...
llvm-svn: 116449
2010-10-13 22:55:33 +00:00
0708e74a95
Add operand encoding bits for SMC and SVC in ARM mode.
...
llvm-svn: 116447
2010-10-13 22:38:23 +00:00
16db3287c0
More encoding cleanup. Also add register Rd operands for indirect branches.
...
llvm-svn: 116444
2010-10-13 22:09:34 +00:00
2a4d99ab62
Simplify some ARM encoding information.
...
llvm-svn: 116440
2010-10-13 21:48:54 +00:00
9874b7de58
Add a FIXME. The ADR instruction is a bit odd.
...
llvm-svn: 116437
2010-10-13 21:32:30 +00:00
7e72ec6626
Refactor the ARM 'setend' instruction pattern. Use a single instruction pattern
...
and handle the operand explicitly. Flesh out encoding information. Add an
explicit disassembler testcase for the instruction.
llvm-svn: 116432
2010-10-13 21:00:04 +00:00
fb07ef19cc
Add a FIXME.
...
llvm-svn: 116428
2010-10-13 20:38:04 +00:00
efc066829b
Make a few more bits of some simple instructions explicit. nop, yield, wfe,
...
wfi, sel, sev and bkpt. All would disassemble properly before, but more
explicitness is good, especially with the integrated assembler coming in
the future.
llvm-svn: 116427
2010-10-13 20:30:55 +00:00
1e7db68774
Add ARM mode encoding for [SU]XT[BH] and [SU]XTA[BH] instructions.
...
llvm-svn: 116421
2010-10-13 19:56:10 +00:00
142e3cbb26
Fix encoding for compares. No Rd register.
...
llvm-svn: 116414
2010-10-13 18:05:25 +00:00
651dc7c9e9
Add ARM mode operand encoding information for ADDE/SUBE instructions.
...
llvm-svn: 116412
2010-10-13 18:00:52 +00:00
8c519c0d4b
Add ARM encoding information for comparisons, forced-cc-out arithmetics, and
...
arithmetic-with-carry-in instructions.
llvm-svn: 116384
2010-10-13 00:50:27 +00:00
efd5369749
Add the rest of the ARM so_reg encoding options (register shifted register)
...
and move to a custom operand encoder. Remove the last of the special handling
stuff from ARMMCCodeEmitter::EncodeInstruction.
llvm-svn: 116377
2010-10-12 23:53:58 +00:00
12e493ace4
Move the ARM so_imm encoding into a custom operand encoder and remove the
...
explicit handling of the instructions referencing it from the MC code
emitter.
llvm-svn: 116367
2010-10-12 23:18:08 +00:00
0e57a9f7a9
Add MOVi ARM encoding.
...
llvm-svn: 116321
2010-10-12 18:09:12 +00:00
6fead930af
Add encoding information for the remainder of the generic arithmetic
...
ARM instructions.
llvm-svn: 116313
2010-10-12 17:11:26 +00:00
b7c2962d20
MC machine encoding for simple aritmetic instructions that use a shifted
...
register operand.
llvm-svn: 116259
2010-10-11 23:16:21 +00:00
5476a274c8
More binary encoding stuff, taking advantage of the new "by name" operand
...
matching in tblgen to do the predicate operand.
llvm-svn: 116213
2010-10-11 18:51:51 +00:00
c43c930690
Implement a few more binary encoding bits. Still very early stage proof-of-
...
concept level stuff at this point, but it is generally working for those
instructions that know how to map the operands.
This patch fills in the register operands for add/sub/or/etc instructions
and adds the conditional execution predicate encoding.
llvm-svn: 116112
2010-10-08 21:45:55 +00:00
742adc328a
Allow use of the 16-bit literal move instruction in CMOVs for ARM mode.
...
llvm-svn: 115884
2010-10-07 00:42:42 +00:00
24ab1ce8c2
Clean up MOVi32imm and t2MOVi32imm pseudo instruction definitions.
...
llvm-svn: 115853
2010-10-06 22:01:26 +00:00
f49540cb4f
Kill of the vestiges of the 'call' Modifier (no longer needed for PLT).
...
llvm-svn: 115845
2010-10-06 21:36:43 +00:00
49d4c0bd18
- Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This
...
allow target to correctly compute latency for cases where static scheduling
itineraries isn't sufficient. e.g. variable_ops instructions such as
ARM::ldm.
This also allows target without scheduling itineraries to compute operand
latencies. e.g. X86 can return (approximated) latencies for high latency
instructions such as division.
- Compute operand latencies for those defined by load multiple instructions,
e.g. ldm and those used by store multiple instructions, e.g. stm.
llvm-svn: 115755
2010-10-06 06:27:31 +00:00
c13194254b
Nuke a bunch of no-longer-needed comment-only asm strings.
...
llvm-svn: 115370
2010-10-01 23:09:33 +00:00
c8e2e9d830
Nuke a few more unused asm strings
...
llvm-svn: 115193
2010-09-30 19:53:58 +00:00
b9429179f9
The asm strings are never used at all, so just nuke 'em entirely.
...
llvm-svn: 115160
2010-09-30 16:56:53 +00:00
4a9cb8f10e
Go ahead and jump!
...
Now that the MC lowering handles the expansion of the pseudos, kill the horrible
blobs of text.
llvm-svn: 115130
2010-09-30 02:18:06 +00:00
2fb20b1d37
ARM instruction itinerary fixes:
...
1. Cortex-a9 8-bit and 16-bit loads / stores AGU cycles are 1 cycle longer than 32-bit ones.
2. Cortex-a9 is out-of-order so model all read cycles as cycle 1.
3. Lots of other random fixes for A8 and A9.
llvm-svn: 115121
2010-09-30 01:08:25 +00:00
0860520527
Add specializations of addrmode2 that allow differentiating those forms
...
which require the use of the shifter-operand. This will be used to split
the ldr/str instructions such that those versions needing the shifter operand
can get a different scheduling itenerary, as in some cases, the use of the
shifter can cause different scheduling than the simpler forms.
llvm-svn: 115066
2010-09-29 19:03:54 +00:00
2259d67a33
Separate itinerary classes for mvn from mov; for tst / teq from cmp / cmn.
...
llvm-svn: 115010
2010-09-29 00:49:25 +00:00
c35d7bbe43
Assign bitwise binary instructions different itinerary classes from ALU instructions such as add / sub.
...
llvm-svn: 115008
2010-09-29 00:27:46 +00:00
62d626ce86
Fix zero and sign extension instructions scheduling itineraries.
...
llvm-svn: 114780
2010-09-25 00:49:35 +00:00
1d35ad62cc
Fix scheduling itinerary for pseudo mov immediate instructions which expand into two real instructions.
...
llvm-svn: 114766
2010-09-24 22:03:46 +00:00
2c5df619c4
Revert r114703 and r114702, removing the isConditionalMove flag from instructions. After further
...
reflection, this isn't going to achieve the purpose I intended it for. Back to the drawing board!
llvm-svn: 114710
2010-09-23 23:45:25 +00:00
2f3728f576
#+4 --> #4 for consistency with other asm output
...
llvm-svn: 114706
2010-09-23 23:32:38 +00:00
07f07290d8
Fix formatting of output .s code
...
llvm-svn: 114705
2010-09-23 23:03:26 +00:00
bd57e0ce3d
Add isConditionalMove bits to X86 and ARM instructions.
...
llvm-svn: 114703
2010-09-23 22:57:01 +00:00
8503054410
Clean up the 'trap' instruction printing a bit. Non-Darwin assemblers don't
...
(yet) recognize the 'trap' mnemonic, so we use .short/.long to emit the
opcode directly. On Darwin, however, we do want the mnemonic for more
readable assembly code and better disassembly.
Adjust the .td file to use the 'trap' mnemonic and handle using the binutils
workaround in the assembly printer. Also tweak the formatting of the opcode
values to make them consistent between the MC printer and the old printer.
llvm-svn: 114679
2010-09-23 18:05:37 +00:00
0e023ea02a
fix a long standing wart: all the ComplexPattern's were being
...
passed the root of the match, even though only a few patterns
actually needed this (one in X86, several in ARM [which should
be refactored anyway], and some in CellSPU that I don't feel
like detangling). Instead of requiring all ComplexPatterns to
take the dead root, have targets opt into getting the root by
putting SDNPWantRoot on the ComplexPattern.
llvm-svn: 114471
2010-09-21 20:31:19 +00:00
ac0ad0f634
Reword since this may not be a bug but intended behavior.
...
llvm-svn: 113584
2010-09-10 10:31:11 +00:00
722cd122dc
Fix LDM_RET schedule itinery.
...
llvm-svn: 113435
2010-09-08 22:57:08 +00:00
39eccb4754
temporarily revert r112664, it is causing a decoding conflict, and
...
the testcases should be merged.
llvm-svn: 112711
2010-09-01 16:00:50 +00:00
6789f8b6ae
We have a chance for an optimization. Consider this code:
...
int x(int t) {
if (t & 256)
return -26;
return 0;
}
We generate this:
tst.w r0, #256
mvn r0, #25
it eq
moveq r0, #0
while gcc generates this:
ands r0, r0, #256
it ne
mvnne r0, #25
bx lr
Scandalous really!
During ISel time, we can look for this particular pattern. One where we have a
"MOVCC" that uses the flag off of a CMPZ that itself is comparing an AND
instruction to 0. Something like this (greatly simplified):
%r0 = ISD::AND ...
ARMISD::CMPZ %r0, 0 @ sets [CPSR]
%r0 = ARMISD::MOVCC 0, -26 @ reads [CPSR]
All we have to do is convert the "ISD::AND" into an "ARM::ANDS" that sets [CPSR]
when it's zero. The zero value will all ready be in the %r0 register and we only
need to change it if the AND wasn't zero. Easy!
llvm-svn: 112664
2010-08-31 22:41:22 +00:00
d657d82597
And ANDS pattern to match the t2ANDS pattern.
...
llvm-svn: 112654
2010-08-31 22:05:37 +00:00
fef37287a8
Make ARM add rN, sp, #imm instructions rematerializable. That's how the address of locals is calculated, so this should
...
help relieve register pressure a bit. Recalculating the local address is
almost always going to be better than spilling.
llvm-svn: 112503
2010-08-30 19:49:58 +00:00
8fc2b590b9
Fix whitespaces. No functionality changes.
...
llvm-svn: 112421
2010-08-29 11:31:07 +00:00
ac64ed0923
File missing from last commit.
...
llvm-svn: 112394
2010-08-29 03:02:28 +00:00
a9c03f4fae
Reapply r112176 without removing the other CMN patterns (that was unintentional).
...
llvm-svn: 112206
2010-08-26 18:33:51 +00:00
e2cbaf6ed7
Don't call tablegen'ed Predicate_* functions in the ARM target.
...
llvm-svn: 111277
2010-08-17 20:39:04 +00:00
62800a990b
80 column cleanup.
...
llvm-svn: 111266
2010-08-17 18:39:16 +00:00
942b10f511
Change ARM PKHTB and PKHBT instructions to use a shift_imm operand to avoid
...
printing "lsl #0". This fixes the remaining parts of pr7792. Make
corresponding changes for encoding/decoding these instructions.
llvm-svn: 111251
2010-08-17 17:23:19 +00:00
804f6159f1
Generalize a pattern for PKHTB: an SRL of 16-31 bits will guarantee
...
that the high halfword is zero. The shift need not be exactly 16 bits.
llvm-svn: 111196
2010-08-16 22:26:55 +00:00
481d7a9ab4
Rename sat_shift operand to shift_imm, in preparation for using it for other
...
instructions besides saturate instructions. No functional changes.
llvm-svn: 111168
2010-08-16 18:27:34 +00:00
8303fbbcf9
Remove unused code.
...
llvm-svn: 111154
2010-08-16 17:06:03 +00:00
8e8f1c133a
Cleaned up the for-disassembly-only entries in the arm instruction table so that
...
the memory barrier variants (other than 'SY' full system domain read and write)
are treated as one instruction with option operand.
llvm-svn: 110951
2010-08-12 20:46:17 +00:00
d59c73f998
Changed the format of DMBsy, DSBsy, and friends from Pseudo to MiscFrm.
...
Added two test cases to arm-tests.txt.
llvm-svn: 110880
2010-08-11 23:35:12 +00:00
add513112a
Move the ARM SSAT and USAT optional shift amount operand out of the
...
instruction opcode. This also fixes part of PR7792.
llvm-svn: 110875
2010-08-11 23:10:46 +00:00
91033bed94
Really control isel of barrier instructions with cpu feature.
...
llvm-svn: 110787
2010-08-11 06:36:31 +00:00
6e809de90c
- Add subtarget feature -mattr=+db which determine whether an ARM cpu has the
...
memory and synchronization barrier dmb and dsb instructions.
- Change instruction names to something more sensible (matching name of actual
instructions).
- Added tests for memory barrier codegen.
llvm-svn: 110785
2010-08-11 06:22:01 +00:00
920f74aaab
Mark ARM compare instructions as isCompare.
...
llvm-svn: 110761
2010-08-11 00:22:27 +00:00
9664984be8
Add a separate ARM instruction format for Saturate instructions.
...
(I discovered 2 more copies of the ARM instruction format list, bringing the
total to 4!! Two of them were already out of sync. I haven't yet gotten into
the disassembler enough to know the best way to fix this, but something needs
to be done.) Add support for encoding these instructions.
llvm-svn: 110754
2010-08-11 00:01:18 +00:00
b1021395b8
Fix indentation.
...
llvm-svn: 110363
2010-08-05 19:00:21 +00:00
72de307116
Add an ARM RSCrr instruction for disassembly only.
...
Partial fix for PR7792.
llvm-svn: 110361
2010-08-05 18:59:36 +00:00
adb93e56a3
Add an ARM RSBrr instruction for disassembly only.
...
Partial fix for PR7792.
llvm-svn: 110358
2010-08-05 18:23:43 +00:00
b128824b60
Move newlines before inline jumptables from the asm strings in .td files to
...
the jtblock_operand print methods. This avoids extra newlines in the
disassembler's output. PR7757.
llvm-svn: 109948
2010-07-31 06:28:10 +00:00
c4a96c0e8c
Add builtins for ssat/usat, similar to RealView's __ssat and __usat intrinsics.
...
llvm-svn: 109813
2010-07-29 22:48:09 +00:00
7010a71ac4
Add intrinsics __builtin_arm_qadd & __builtin_arm_qsub to allow access to the QADD & QSUB instructions.
...
Behave identically to __qadd & __qsub RealView instruction intrinsics.
llvm-svn: 109770
2010-07-29 17:56:55 +00:00
c445a7d29b
ARM mode version of r109693. Remove incorrect substitution pattern for UXTB16. It wrongly assumed the input shift was actually a rotate. rdar://8240138
...
llvm-svn: 109696
2010-07-28 23:25:44 +00:00
11013eda5a
Add basic support to code-gen the ARM/Thumb2 bit-field insert (BFI) instruction
...
and a combine pattern to use it for setting a bit-field to a constant
value. More to come for non-constant stores.
llvm-svn: 108570
2010-07-16 23:05:05 +00:00
a90af1ba38
Improve 64-subtraction of immediates when parts of the immediate can fit
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in the literal field of an instruction. E.g.,
long long foo(long long a) {
return a - 734439407618LL;
}
rdar://7038284
llvm-svn: 108339
2010-07-14 17:45:16 +00:00
0cc4ad983d
Extend the r107852 optimization which turns some fp compare to code sequence using only i32 operations. It now optimize some f64 compares when fp compare is exceptionally slow (e.g. cortex-a8). It also catches comparison against 0.0.
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llvm-svn: 108258
2010-07-13 19:27:42 +00:00
e2289285ae
Changes to ARM tail calls, mostly cosmetic.
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Add explicit testcases for tail calls within the same module.
Duplicate some code to humor those who think .w doesn't apply on ARM.
Leave this disabled on Thumb1, and add some comments explaining why it's hard
and won't gain much.
llvm-svn: 107851
2010-07-08 01:18:23 +00:00
523e554afa
LEApcrelJT shouldn't be marked as neverHasSideEffects, as we don't want it
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being moved around away from the jump table it references. rdar://8104340
llvm-svn: 106483
2010-06-21 21:27:27 +00:00
d5c58b76ab
Fix PR 7433. Silly typo in non-Darwin ARM tail call
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handling, plus correct R9 handling in that mode.
llvm-svn: 106434
2010-06-21 18:21:49 +00:00
e5fcd333da
Indentation and remove dead code.
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llvm-svn: 106362
2010-06-19 00:11:54 +00:00
589ffb4902
Fix ARM/Thumb reversal in previous attempt.
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llvm-svn: 106314
2010-06-18 21:07:47 +00:00
a06c2f79fc
An attempt to fix the problem Anton reported with
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ARM tail calls. Don't know if it works, but it
doesn't break Darwin.
llvm-svn: 106309
2010-06-18 20:44:28 +00:00
3ac52b3e43
Last round of changes for ARM tail calls.
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Not turning them on yet.
llvm-svn: 106295
2010-06-18 18:13:11 +00:00
438c35b5d1
Add file missing from previous commit.
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llvm-svn: 106058
2010-06-15 22:24:08 +00:00
d679ff7330
Early implementation of tail call for ARM.
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A temporary flag -arm-tail-calls defaults to off,
so there is no functional change by default.
Intrepid users may try this; simple cases work
but there are bugs.
llvm-svn: 105413
2010-06-03 21:09:53 +00:00
84511e1526
Clean up 80 column violations. No functional change.
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llvm-svn: 105350
2010-06-02 21:53:11 +00:00
b342e09b5e
correct retattr
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llvm-svn: 104980
2010-05-28 18:03:48 +00:00
37eb2c24b9
make sure accesses to set up the jmpbuf don't get moved after it by the scheduler. Add a missing \n.
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llvm-svn: 104967
2010-05-28 17:37:40 +00:00
faa3abbe39
Update the saved stack pointer in the sjlj function context following either
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an alloca() or an llvm.stackrestore(). rdar://8031573
llvm-svn: 104900
2010-05-27 23:49:24 +00:00
c98892fdaa
Adjust eh.sjlj.setjmp to properly have a chain and to have an opcode entry in
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ISD::. No functional change.
llvm-svn: 104734
2010-05-26 20:22:18 +00:00
bd9485db63
Implement eh.sjlj.longjmp for ARM. Clean up the intrinsic a bit.
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Followups: docs patch for the builtin and eh.sjlj.setjmp cleanup to match
longjmp.
llvm-svn: 104419
2010-05-22 01:06:18 +00:00
b7704fee4c
Use 'adr' for LEApcrel and LEApcrel. Mark LEApcrel re-materializable.
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llvm-svn: 104114
2010-05-19 07:26:50 +00:00
dd7f566597
Mark pattern-less mayLoad / mayStore instructions neverHasSideEffects. These do not have other un-modeled side effects.
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llvm-svn: 104111
2010-05-19 06:07:03 +00:00
2c452fcd14
Mark a few more pattern-less instructions with neverHasSideEffects. This is especially important on instructions like t2LEApcreal which are prime candidate for machine LICM.
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llvm-svn: 104102
2010-05-19 01:52:25 +00:00
497d831966
Chris said that the comment char should be escaped. Fix all the occurences of "@" in *.td
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llvm-svn: 103903
2010-05-16 09:15:36 +00:00
2b7aace2e0
"trap" pseudo-op turned out to be apple-local.
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Temporary emit it as raw bytes until it will be added to binutils as well.
llvm-svn: 103878
2010-05-15 17:19:20 +00:00
2fa5a7e7e4
Select @llvm.trap to the special B with 1111 condition (i.e. trap) instruction.
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llvm-svn: 103459
2010-05-11 07:26:32 +00:00
151cd8f159
Cleanup of ARMv7M support. Move hardware divide and Thumb2 extract/pack
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instructions to subtarget features and update tests to reflect.
PR5717.
llvm-svn: 103136
2010-05-05 23:44:43 +00:00
92d999001c
Add initial support for ARMv7M subtarget and cortex-m3 cpu. Patch by
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Jordy <snhjordy@gmail.com>.
Followup patches will add some tests and adjust to use Subtarget features
for the instructions.
llvm-svn: 103119
2010-05-05 20:44:35 +00:00
807e1748fc
Multiclass LdStCop was using pre-UAL syntax LDC<c>L for the L fragment. Changed
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to the UAL syntax of LDCL<c>, instead.
Add a test case for this change which also tests the removal of assert() from
printAddrMode2OffsetOperand().
llvm-svn: 101527
2010-04-16 19:33:23 +00:00
acbc06c2a3
Fixed a bug in ARM disassembly where LDRSBT should have am3offset operand, not
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am2offset. Modified the instruction table entry and added a new test case.
llvm-svn: 101415
2010-04-15 23:12:47 +00:00
0106063556
Provide versions of the ARM eh_sjlj_setjmp instructions for non-VFP subtargets
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such that the non-VFP versions have no implicit defs of VFP registers.
If any callee-saved VFP registers are marked as having been defined, the
prologue/epilogue code will try to save and restore them.
Radar 7770432.
llvm-svn: 100892
2010-04-09 20:41:18 +00:00
34de7768bf
Make the use of the vmla and vmls VFP instructions controllable via cmd line.
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Preliminary testing shows significant performance wins by not using these
instructions.
llvm-svn: 99436
2010-03-24 22:31:46 +00:00
ae08a736d6
Re-commit r98683 ("remove redundant writeback flag from ARM address mode 6")
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with changes to add a separate optional register update argument. Change all
the NEON instructions with address register writeback to use it.
llvm-svn: 99095
2010-03-20 22:13:40 +00:00
053e3510a3
Revert r98679. The disassembler will be updated to depend on the existence of
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IndexModeUpd and then populates the Inst{21}=1 while populating the instructions
for disassembly.
llvm-svn: 99013
2010-03-19 23:50:27 +00:00
e4191e719b
Revert this change, since it was causing ARM performance regressions.
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--- Reverse-merging r98889 into '.':
U lib/Target/ARM/ARMInstrNEON.td
U lib/Target/ARM/ARMISelLowering.h
U lib/Target/ARM/ARMInstrInfo.td
U lib/Target/ARM/ARMInstrVFP.td
U lib/Target/ARM/ARMISelLowering.cpp
U lib/Target/ARM/ARMInstrFormats.td
llvm-svn: 99010
2010-03-19 22:51:32 +00:00
0433699ef0
set SDNPVariadic on nodes throughout the rest of the targets that
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need them.
llvm-svn: 98937
2010-03-19 05:33:51 +00:00
f11aa9e7b4
Get rid of target-specific fp <-> int nodes when still I'm here.
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llvm-svn: 98889
2010-03-18 22:35:45 +00:00
c7ba918b84
Revert 98683. It is breaking something in the disassembler.
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llvm-svn: 98692
2010-03-16 23:01:13 +00:00
c953bca10b
Remove redundant writeback flag from ARM address mode 6. Also remove the
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optional register update argument, which is currently unused -- when we add
support for that, it can just be a separate operand.
llvm-svn: 98683
2010-03-16 21:44:40 +00:00
Jim Grosbach