9c65e4d69c
Add ORR and EOR to the CMP peephole optimizer. It's hard to get isel to generate
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a case involving EOR, so I only added a test for ORR.
llvm-svn: 129610
2011-04-15 21:24:38 +00:00
0829b3065a
The AND instruction leaves the V flag unmodified, so it falls victim to the same
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problem as all of the other instructions we fold with CMPs.
llvm-svn: 129602
2011-04-15 20:45:00 +00:00
93eae1571c
Add missing register forms of instructions to the ARM CMP-folding code. This
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fixes <rdar://problem/9287901>.
llvm-svn: 129599
2011-04-15 20:28:28 +00:00
0ab5e2cded
Fix a ton of comment typos found by codespell. Patch by
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Luis Felipe Strano Moraes!
llvm-svn: 129558
2011-04-15 05:18:47 +00:00
12bb05b75b
Fix another fcopysign lowering bug. If src is f64 and destination is f32, don't
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forget to right shift the source by 32 first. rdar://9287902
llvm-svn: 129556
2011-04-15 01:31:00 +00:00
681fef5986
For t2BFI, both Inst{26} and Inst{5} "should" be 0.
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Ref: I.1 Instruction encoding diagrams and pseudocode
llvm-svn: 129552
2011-04-15 00:35:08 +00:00
421316178e
The ARM disassembler did not handle the alignment correctly for VLD*DUP* instructions
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(single element or n-element structure to all lanes).
llvm-svn: 129550
2011-04-15 00:10:45 +00:00
44887f9c7e
Follow up on r127913. Fix Thumb revsh isel. rdar://9286766
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llvm-svn: 129548
2011-04-14 23:27:44 +00:00
4251b151b1
Add sanity checkings for Thumb2 Load/Store Register Exclusive family of operations.
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llvm-svn: 129531
2011-04-14 19:13:28 +00:00
d0fb04f437
Thumb disassembler did not handle tBRIND (indirect branch) properly.
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rdar://problem/9280370
llvm-svn: 129480
2011-04-13 21:59:01 +00:00
b6a37bff21
Check for unallocated instruction encodings when disassembling Thumb Branch instructions (tBcc and t2Bcc).
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rdar://problem/9280470
llvm-svn: 129471
2011-04-13 21:35:49 +00:00
ffa6378fd6
The LDR*T/STR*T (unpriviledged load/store) operations don't take SP or PC as Rt.
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rdar://problem/9279440
llvm-svn: 129469
2011-04-13 21:04:32 +00:00
415b5e8341
Fix a typo in an ARM-specific DAG combine. This fixes <rdar://problem/9278274>.
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llvm-svn: 129468
2011-04-13 21:01:19 +00:00
70591cbc60
Check the corner cases for t2LDRSHi12 correctly and mark invalid encodings as such.
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rdar://problem/9276651
llvm-svn: 129462
2011-04-13 19:46:05 +00:00
0d306a7840
Fix a bug where for t2MOVCCi disassembly, the TIED_TO register operand was not properly handled.
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rdar://problem/9276427
llvm-svn: 129456
2011-04-13 17:51:02 +00:00
b2f9fa1fce
Forgot to add this change for http://llvm.org/viewvc/llvm-project?view=rev&revision=129387 .
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llvm-svn: 129451
2011-04-13 16:56:08 +00:00
8001850ee8
Fix a typo.
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llvm-svn: 129429
2011-04-13 06:39:16 +00:00
3c2f74c9f3
Add sanity check for Ld/St Dual forms of Thumb2 instructions.
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rdar://problem/9273947
llvm-svn: 129411
2011-04-12 23:31:00 +00:00
987164043c
Add @earlyclobber constraints to the writeback register of all ARM store instructions.
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The ARMARM specifies these instructions as unpredictable when storing the
writeback register. This shouldn't affect code generation much since storing a
pointer to itself is quite rare.
llvm-svn: 129409
2011-04-12 23:27:48 +00:00
960eef3db3
The Thumb2 RFE instructions need to have their second halfword fully specified.
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In addition, the base register is not rGPR, but GPR with th exception that:
if n == 15 then UNPREDICTABLE
rdar://problem/9273836
llvm-svn: 129391
2011-04-12 21:41:51 +00:00
01637b9acb
Add bad register checks for Thumb2 Ld/St instructions.
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rdar://problem/9269047
llvm-svn: 129387
2011-04-12 21:17:51 +00:00
ab86a519f8
The Thumb2 Ld, St, and Preload instructions with the i12 forms should have its Inst{23}
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be specified as '1' (add = TRUE).
Also add a utility function for Thumb2.
llvm-svn: 129377
2011-04-12 18:48:00 +00:00
d0e2be39ea
Print out a debug message when the reglist fails the sanity check for Thumb Ld/St Multiple.
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llvm-svn: 129365
2011-04-12 17:09:04 +00:00
fbcd69b96a
Split a store of a VMOVDRR into two integer stores to avoid mixing NEON and ARM
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stores of arguments in the same cache line. This fixes the second half of
<rdar://problem/8674845>.
llvm-svn: 129345
2011-04-12 02:24:17 +00:00
672ef14a62
A8.6.16 B
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Encoding T1 (tBcc)
if cond == '1110' then UNDEFINED;
rdar://problem/9268681
llvm-svn: 129325
2011-04-12 00:14:49 +00:00
dc8bf9ec08
Thumb disassembler was erroneously rejecting "blx sp" instruction.
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rdar://problem/9267838
llvm-svn: 129320
2011-04-11 23:33:30 +00:00
f79d5365de
Fix the bug where the immediate shift amount for Thumb logical shift instructions are incorrectly disassembled.
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rdar://problem/9266265
llvm-svn: 129298
2011-04-11 21:14:35 +00:00
5140802cd9
Fix another using-CPSR-twice bug in my ADCS/SBCS cleanups, and make proper use of the Commutable bit.
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llvm-svn: 129294
2011-04-11 20:12:19 +00:00
74adbddade
Trivial comment fix.
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llvm-svn: 129288
2011-04-11 18:51:50 +00:00
66fab75920
Check invalid register encodings for LdFrm/StFrm ARM instructions and flag them as
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invalid instructions.
llvm-svn: 129286
2011-04-11 18:34:12 +00:00
9377a52c12
Adding support for printing operands symbolically to llvm's public 'C'
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disassembler API. Hooked this up to the ARM target so such tools as Darwin's
otool(1) can now print things like branch targets for example this:
blx _puts
instead of this:
blx #-36
And even print the expression encoded in the Mach-O relocation entried for
things like this:
movt r0, :upper16:((_foo-_bar)+1234)
llvm-svn: 129284
2011-04-11 18:08:50 +00:00
7c14a558fe
Don't include Operator.h from InstrTypes.h.
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llvm-svn: 129271
2011-04-11 09:35:34 +00:00
4e1796e8d1
Fix an apparent typo that made GCC complain
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llvm-svn: 129160
2011-04-08 21:59:49 +00:00
74d92c1924
Change -arm-trap-func= into a non-arm specific option. Now Intrinsic::trap is lowered into a call to the specified trap function at sdisel time.
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llvm-svn: 129152
2011-04-08 21:37:21 +00:00
f2faf4e53a
Check opcoe (dmb, dsb) instead of bitfields matching.
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llvm-svn: 129148
2011-04-08 20:03:46 +00:00
a9570f77d5
Hanlde the checking of bad regs for SMMLAR properly, instead of asserting.
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PR9650
rdar://problem/9257565
llvm-svn: 129147
2011-04-08 19:41:22 +00:00
875e0e4626
Sanity check the option operand for DMB/DSB.
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PR9648
rdar://problem/9257634
llvm-svn: 129146
2011-04-08 19:18:07 +00:00
a5dcd98a47
Mark hasExtraDefRegAllocReq=1 on LDRD.
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The previous cleanup of LDRD got overzealous and removed it, causing post-RA
scheduling to get overzealous in breaking antidependencies and invalidate these instructions. Hilarity and invalid assembly ensued.
rdar://9244161
llvm-svn: 129144
2011-04-08 18:47:05 +00:00
7e51b4640f
Add sanity checking for bad register specifier(s) for the DPFrm instructions.
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Add more test cases to exercise the logical branches related to the above change.
llvm-svn: 129117
2011-04-08 00:29:09 +00:00
9a3f2772f0
Add option to emit @llvm.trap as a function call instead of a trap instruction. rdar://9249183.
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llvm-svn: 129107
2011-04-07 20:31:12 +00:00
27f3330132
Fixed encoding for VEXTqf
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llvm-svn: 129101
2011-04-07 19:56:12 +00:00
04efb8f6ce
Add sanity checking for invalid register encodings for signed/unsigned extend instructions.
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Add some test cases.
llvm-svn: 129098
2011-04-07 19:28:58 +00:00
07606661f9
Add sanity checking for invalid register encodings for saturating instructions.
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llvm-svn: 129096
2011-04-07 19:02:08 +00:00
194a2267ad
Add some more comments about checkings of invalid register numbers.
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And two test cases.
llvm-svn: 129090
2011-04-07 18:33:19 +00:00
266792a55a
Prevent ARM DAG Combiner from doing an AND or OR combine on an illegal vector type (vectors of size 3). Also included test cases.
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llvm-svn: 129074
2011-04-07 15:24:20 +00:00
313ec7953a
Sanity check MSRi for invalid mask values and reject it as invalid.
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rdar://problem/9246844
llvm-svn: 129050
2011-04-07 01:37:34 +00:00
c0e86fb965
The ARM disassembler was not recognizing USADA8 instruction. Need to add checking for register values
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for USAD8 and USADA8.
rdar://problem/9247060
llvm-svn: 129047
2011-04-07 01:05:52 +00:00
a7c7b54dde
Change -arm-divmod-libcall to a target neutral option.
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llvm-svn: 129045
2011-04-07 00:58:44 +00:00
d4cced54b3
Should also check SMLAD for invalid register values.
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rdar://problem/9246650
llvm-svn: 129042
2011-04-07 00:50:25 +00:00
bdff1c997a
Teach the ARM peephole optimizer that RSB, RSC, ADC, and SBC can be used for folded comparisons, just like ADD and SUB.
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llvm-svn: 129038
2011-04-06 23:35:59 +00:00
Cameron Zwarich