9c65e4d69c
Add ORR and EOR to the CMP peephole optimizer. It's hard to get isel to generate
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a case involving EOR, so I only added a test for ORR.
llvm-svn: 129610
2011-04-15 21:24:38 +00:00
d56f2d910b
Fix lines that exceed 80 columns. There is no change in functionality.
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llvm-svn: 129608
2011-04-15 21:06:38 +00:00
aef55c8801
Fix lines that have incorrect indentation or exceed 80 columns. There is no change in functionality.
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llvm-svn: 129606
2011-04-15 21:00:26 +00:00
0829b3065a
The AND instruction leaves the V flag unmodified, so it falls victim to the same
...
problem as all of the other instructions we fold with CMPs.
llvm-svn: 129602
2011-04-15 20:45:00 +00:00
7583dbdc88
Fix cmake build.
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llvm-svn: 129601
2011-04-15 20:34:45 +00:00
93eae1571c
Add missing register forms of instructions to the ARM CMP-folding code. This
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fixes <rdar://problem/9287901>.
llvm-svn: 129599
2011-04-15 20:28:28 +00:00
279169771b
Add pass that expands pseudo instructions into target instructions after register allocation. Define pseudos that get expanded into mtc1 or mfc1 instructions.
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llvm-svn: 129594
2011-04-15 19:52:08 +00:00
a2e61292f0
Increase SubtargetFeatureKV Value and Implies fields to 64 bits since some targets are getting very close to 32 subtarget features. Also teach tablegen to error when there are more than 64 features to guard against undefined behavior. rdar://9282332
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llvm-svn: 129590
2011-04-15 19:35:46 +00:00
a01cdb0e37
Add 129518 back with a fix for when we are producing eh just because of debug info.
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Change ELF systems to use CFI for producing the EH tables. This reduces the
size of the clang binary in Debug builds from 690MB to 679MB.
llvm-svn: 129571
2011-04-15 15:11:06 +00:00
0ab5e2cded
Fix a ton of comment typos found by codespell. Patch by
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Luis Felipe Strano Moraes!
llvm-svn: 129558
2011-04-15 05:18:47 +00:00
b5e3e9dd27
Revert r129518, "Change ELF systems to use CFI for producing the EH tables. This reduces the"
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It broke several builds.
llvm-svn: 129557
2011-04-15 03:35:57 +00:00
12bb05b75b
Fix another fcopysign lowering bug. If src is f64 and destination is f32, don't
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forget to right shift the source by 32 first. rdar://9287902
llvm-svn: 129556
2011-04-15 01:31:00 +00:00
681fef5986
For t2BFI, both Inst{26} and Inst{5} "should" be 0.
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Ref: I.1 Instruction encoding diagrams and pseudocode
llvm-svn: 129552
2011-04-15 00:35:08 +00:00
30088ba110
Add 3DNow! intrinsics.
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llvm-svn: 129551
2011-04-15 00:32:41 +00:00
421316178e
The ARM disassembler did not handle the alignment correctly for VLD*DUP* instructions
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(single element or n-element structure to all lanes).
llvm-svn: 129550
2011-04-15 00:10:45 +00:00
44887f9c7e
Follow up on r127913. Fix Thumb revsh isel. rdar://9286766
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llvm-svn: 129548
2011-04-14 23:27:44 +00:00
4251b151b1
Add sanity checkings for Thumb2 Load/Store Register Exclusive family of operations.
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llvm-svn: 129531
2011-04-14 19:13:28 +00:00
6f195469b1
move PR9661 out to here.
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llvm-svn: 129527
2011-04-14 18:47:18 +00:00
aa2a7cd828
Change ELF systems to use CFI for producing the EH tables. This reduces the
...
size of the clang binary in Debug builds from 690MB to 679MB.
llvm-svn: 129518
2011-04-14 15:18:53 +00:00
b88784c185
Fix whitespace and tabs.
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llvm-svn: 129517
2011-04-14 14:33:36 +00:00
1d313c6f6d
add a minor missed dag combine that is blocking mid-level optimization
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improvements, that will lead to fixing PR6627.
llvm-svn: 129504
2011-04-14 04:21:42 +00:00
410ec4aad1
As Dan pointed out, movzbl, movsbl, and friends are nicer than their alias
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(movzx/movsx) because they give more information. Revert that part of the patch.
llvm-svn: 129498
2011-04-14 01:46:37 +00:00
7e07d6fb69
Have the X86 back-end emit the alias instead of what's being aliased. In most
...
cases, it's much nicer and more informative reading the alias.
llvm-svn: 129497
2011-04-14 01:11:51 +00:00
6dd69d9241
Add an option to not print the alias of an instruction. It defaults to "print
...
the alias".
llvm-svn: 129485
2011-04-13 23:36:21 +00:00
d0fb04f437
Thumb disassembler did not handle tBRIND (indirect branch) properly.
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rdar://problem/9280370
llvm-svn: 129480
2011-04-13 21:59:01 +00:00
b6a37bff21
Check for unallocated instruction encodings when disassembling Thumb Branch instructions (tBcc and t2Bcc).
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rdar://problem/9280470
llvm-svn: 129471
2011-04-13 21:35:49 +00:00
ffa6378fd6
The LDR*T/STR*T (unpriviledged load/store) operations don't take SP or PC as Rt.
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rdar://problem/9279440
llvm-svn: 129469
2011-04-13 21:04:32 +00:00
415b5e8341
Fix a typo in an ARM-specific DAG combine. This fixes <rdar://problem/9278274>.
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llvm-svn: 129468
2011-04-13 21:01:19 +00:00
9398197ef1
Fix a regression caused by r102515 where explicit alignment on globals is
...
ignored. There was a test to catch this, but it was just blindly updated in
a large change. This fixes another part of <rdar://problem/9275290>.
llvm-svn: 129466
2011-04-13 20:36:04 +00:00
70591cbc60
Check the corner cases for t2LDRSHi12 correctly and mark invalid encodings as such.
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rdar://problem/9276651
llvm-svn: 129462
2011-04-13 19:46:05 +00:00
0d306a7840
Fix a bug where for t2MOVCCi disassembly, the TIED_TO register operand was not properly handled.
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rdar://problem/9276427
llvm-svn: 129456
2011-04-13 17:51:02 +00:00
b2f9fa1fce
Forgot to add this change for http://llvm.org/viewvc/llvm-project?view=rev&revision=129387 .
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llvm-svn: 129451
2011-04-13 16:56:08 +00:00
70be27e913
Fix an obvious problem with an alignment computation. AsmPrinter actually does
...
the max itself, so it is not easy to write a test case for this, but I added a
test case that would fail if the code in AsmPrinter were removed.
llvm-svn: 129432
2011-04-13 09:02:43 +00:00
8001850ee8
Fix a typo.
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llvm-svn: 129429
2011-04-13 06:39:16 +00:00
cdf59f7016
If a global variable has a specified alignment that is less than the preferred
...
alignment for its type, use the minimum of the specified alignment and the ABI
alignment. This fixes <rdar://problem/9275290>.
llvm-svn: 129428
2011-04-13 06:03:16 +00:00
b902f1dd88
Reapply r129401 with patch for clang.
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llvm-svn: 129419
2011-04-13 00:36:11 +00:00
3c2f74c9f3
Add sanity check for Ld/St Dual forms of Thumb2 instructions.
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rdar://problem/9273947
llvm-svn: 129411
2011-04-12 23:31:00 +00:00
987164043c
Add @earlyclobber constraints to the writeback register of all ARM store instructions.
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The ARMARM specifies these instructions as unpredictable when storing the
writeback register. This shouldn't affect code generation much since storing a
pointer to itself is quite rare.
llvm-svn: 129409
2011-04-12 23:27:48 +00:00
dbfde42468
Revert r129401 for now. Clang is using the old way of doing things.
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llvm-svn: 129403
2011-04-12 22:59:27 +00:00
47c24875a1
Remove the unaligned load intrinsics in favor of using native unaligned loads.
...
Now that we have a first-class way to represent unaligned loads, the unaligned
load intrinsics are superfluous.
First part of <rdar://problem/8460511>.
llvm-svn: 129401
2011-04-12 22:46:31 +00:00
960eef3db3
The Thumb2 RFE instructions need to have their second halfword fully specified.
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In addition, the base register is not rGPR, but GPR with th exception that:
if n == 15 then UNPREDICTABLE
rdar://problem/9273836
llvm-svn: 129391
2011-04-12 21:41:51 +00:00
01637b9acb
Add bad register checks for Thumb2 Ld/St instructions.
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rdar://problem/9269047
llvm-svn: 129387
2011-04-12 21:17:51 +00:00
ab86a519f8
The Thumb2 Ld, St, and Preload instructions with the i12 forms should have its Inst{23}
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be specified as '1' (add = TRUE).
Also add a utility function for Thumb2.
llvm-svn: 129377
2011-04-12 18:48:00 +00:00
d0e2be39ea
Print out a debug message when the reglist fails the sanity check for Thumb Ld/St Multiple.
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llvm-svn: 129365
2011-04-12 17:09:04 +00:00
fbcd69b96a
Split a store of a VMOVDRR into two integer stores to avoid mixing NEON and ARM
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stores of arguments in the same cache line. This fixes the second half of
<rdar://problem/8674845>.
llvm-svn: 129345
2011-04-12 02:24:17 +00:00
672ef14a62
A8.6.16 B
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Encoding T1 (tBcc)
if cond == '1110' then UNDEFINED;
rdar://problem/9268681
llvm-svn: 129325
2011-04-12 00:14:49 +00:00
dc8bf9ec08
Thumb disassembler was erroneously rejecting "blx sp" instruction.
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rdar://problem/9267838
llvm-svn: 129320
2011-04-11 23:33:30 +00:00
f30a0e2d80
Fix an error in the MBlaze delay slot filler.
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llvm-svn: 129313
2011-04-11 22:45:02 +00:00
1914c39bd4
Add scheduling information for the MBlaze backend.
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llvm-svn: 129311
2011-04-11 22:31:52 +00:00
e3685217d0
Don't crash on invalid instructions when disassembling MBlaze code.
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This fixes http://llvm.org/bugs/show_bug.cgi?id=9653
llvm-svn: 129303
2011-04-11 21:35:21 +00:00
Cameron Zwarich