David Goodwin
af7451b674
Checkpoint Thumb2 Instr info work. Generalized base code so that it can be shared between ARM and Thumb2. Not yet activated because register information must be generalized first.
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llvm-svn: 75010
2009-07-08 16:09:28 +00:00
Evan Cheng
d0611f9a37
Add Thumb2 movcc instructions.
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llvm-svn: 74946
2009-07-07 20:39:03 +00:00
Evan Cheng
d0f6324cdc
Add Thumb2 pkhbt / pkhtb.
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llvm-svn: 74895
2009-07-07 05:35:52 +00:00
Evan Cheng
b24e51e2d9
Add some more Thumb2 multiplication instructions.
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llvm-svn: 74889
2009-07-07 01:17:28 +00:00
Evan Cheng
0e8bde5910
Add thumb2 sign / zero extend with rotate instructions.
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llvm-svn: 74755
2009-07-03 01:43:10 +00:00
Evan Cheng
53cdf022b6
Added indexed stores.
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llvm-svn: 74740
2009-07-03 00:06:39 +00:00
Evan Cheng
8ecd7eb3f7
Sign extending pre/post indexed loads.
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llvm-svn: 74736
2009-07-02 23:16:11 +00:00
Evan Cheng
84c6cda2ef
Thumb2 pre/post indexed loads.
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llvm-svn: 74696
2009-07-02 07:28:31 +00:00
David Goodwin
86c7e20ca6
Add PIC load and store patterns for Thumb-2.
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llvm-svn: 74577
2009-07-01 00:01:13 +00:00
David Goodwin
d0890a2bad
Add thumb-2 store word, halfword, and byte.
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llvm-svn: 74555
2009-06-30 22:11:34 +00:00
David Goodwin
28d6d87244
Improve Thumb-2 jump table support.
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llvm-svn: 74549
2009-06-30 19:50:22 +00:00
Evan Cheng
57726817aa
A few more load instructions.
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llvm-svn: 74500
2009-06-30 02:15:48 +00:00
David Goodwin
17512663f5
Enhance tests to include shifted-register operand testing.
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llvm-svn: 74490
2009-06-30 01:02:20 +00:00
David Goodwin
76b37950ca
Add Thumb-2 support for TEQ amd TST.
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llvm-svn: 74468
2009-06-29 22:49:42 +00:00
David Goodwin
911edef65b
Thumb-2 tests
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llvm-svn: 74464
2009-06-29 22:25:22 +00:00
David Goodwin
dbf11ba800
Rename ARMcmpNZ to ARMcmpZ and use it to represent comparisons that set only the Z flag (i.e. eq and ne). Make ARMcmpZ commutative.
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llvm-svn: 74423
2009-06-29 15:33:01 +00:00
Evan Cheng
b23b50d54d
Implement Thumb2 ldr.
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After much back and forth, I decided to deviate from ARM design and split LDR into 4 instructions (r + imm12, r + imm8, r + r << imm12, constantpool). The advantage of this is 1) it follows the latest ARM technical manual, and 2) makes it easier to reduce the width of the instruction later. The down side is this creates more inconsistency between the two sub-targets. We should split ARM LDR instruction in a similar fashion later. I've added a README entry for this.
llvm-svn: 74420
2009-06-29 07:51:04 +00:00
David Goodwin
5285817490
When possible, use "mvn ra, rb" instead of "eor ra, rb, -1" because mvn has a narrow version and eor(i) does not.
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llvm-svn: 74355
2009-06-26 23:13:13 +00:00
David Goodwin
3aaa751712
Thumb-2 tests
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llvm-svn: 74345
2009-06-26 22:37:07 +00:00
David Goodwin
aa294c5593
Thumb-2 has CLZ.
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llvm-svn: 74322
2009-06-26 20:47:43 +00:00
David Goodwin
35ee722d42
Use "adcs/sbcs" only when the carry-out is live, otherwise use "adc/sbc".
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llvm-svn: 74321
2009-06-26 20:45:56 +00:00
Daniel Dunbar
a720af1370
More spelling Count as count.
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llvm-svn: 74306
2009-06-26 18:35:07 +00:00
Daniel Dunbar
6b1678d5d8
Spell Count as count.
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llvm-svn: 74298
2009-06-26 18:21:54 +00:00
David Goodwin
3bd42afebe
Add Thumb-2 tests.
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llvm-svn: 74295
2009-06-26 18:10:30 +00:00
David Goodwin
5960e6d974
ADC used to implement adde should use "adcs" opcode instead of "adc".
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llvm-svn: 74293
2009-06-26 18:07:25 +00:00
David Goodwin
34f7ede9e7
ORN and BIC tests.
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llvm-svn: 74289
2009-06-26 16:20:06 +00:00
David Goodwin
0377f737ff
Currently there is a pattern for the thumb-2 MOV 16-bit immediate instruction. That instruction cannot write the flags so it should use T2I instead of T2sI.
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Also, added a pattern for the thumb-2 MOV of shifted immediate since that can encode immediates not encodable by the 16-bit immediate.
llvm-svn: 74288
2009-06-26 16:10:07 +00:00
Evan Cheng
7779156b39
Fix tests: Count -> count.
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llvm-svn: 74282
2009-06-26 07:05:57 +00:00
Evan Cheng
34c8c7414f
Fix a CodeGenDAGPatterns bug. Check if top level predicates match when it's looking for duplicates.
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llvm-svn: 74276
2009-06-26 05:59:16 +00:00
Daniel Dunbar
07025e2c02
Fix spelling of 'count'
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llvm-svn: 74249
2009-06-26 01:33:02 +00:00
Evan Cheng
97727a61f9
Select ADC, SBC, and RSC instead of the ADCS, SBCS, and RSCS when the carry bit def is not used.
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llvm-svn: 74228
2009-06-25 23:34:10 +00:00
David Goodwin
16f357cccf
Use MVN for ~t2_so_imm immediates.
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llvm-svn: 74223
2009-06-25 23:11:21 +00:00
Evan Cheng
c7ea8df67e
ISD::ADDE / ISD::SUBE updates the carry bit so they should isle to ADCS and SBCS / RSCS.
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llvm-svn: 74200
2009-06-25 20:59:23 +00:00
Evan Cheng
83f979a48b
Add Thumb2 pc relative add.
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llvm-svn: 74141
2009-06-24 23:47:58 +00:00
Evan Cheng
ff1a4a7271
We should run these tests as well.
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llvm-svn: 74121
2009-06-24 21:36:26 +00:00
Evan Cheng
d76d0aa68a
Move thumb and thumb2 tests into separate directories.
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llvm-svn: 74068
2009-06-24 06:36:07 +00:00