ca88b4abec
Prevent generation of redundant addiu instructions that compute address of
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static variables or functions.
llvm-svn: 133803
2011-06-24 17:55:19 +00:00
6cdd72a9ca
PTX: Always use registers for return values, but use .param space for device
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parameters if SM >= 2.0
- Update test cases to be more robust against register allocation changes
- Bump up the number of registers to 128 per type
- Include Python script to re-generate register file with any number of
registers
llvm-svn: 133736
2011-06-23 18:10:13 +00:00
a4aecf3dc4
PTX: Fixup test cases for device param changes
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llvm-svn: 133735
2011-06-23 18:10:08 +00:00
67ff0718a4
lit support for REQUIRES: asserts.
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Take #2 . Don't piggyback on the existing config.build_mode. Instead,
define a new lit feature for each build feature we need (currently
just "asserts"). Teach both autoconf'd and cmake'd Makefiles to define
this feature within test/lit.site.cfg. This doesn't require any lit
harness changes and should be more robust across build systems.
llvm-svn: 133664
2011-06-22 23:23:19 +00:00
2496c1f1f8
Reenable tail duplication of bb with just an unconditional jump, but
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don't remove blocks that have their address taken.
llvm-svn: 133659
2011-06-22 22:31:57 +00:00
90e6a4e5d5
Needs a triple.
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llvm-svn: 133634
2011-06-22 19:42:14 +00:00
6208a2fd66
Emit trailing padding on constant vectors when TargetData says that the vector
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is larger than the sum of the elements (including per-element padding).
llvm-svn: 133631
2011-06-22 18:55:03 +00:00
6fafebfb6a
PTX: Add signed integer comparisons
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llvm-svn: 133599
2011-06-22 02:09:50 +00:00
54e3c0f5d9
PTX: Add .address_size directive if PTX version >= 2.3
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Patch by Wei-Ren Chen
llvm-svn: 133589
2011-06-22 00:43:56 +00:00
c93ef81e24
Test case for r133560.
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llvm-svn: 133585
2011-06-22 00:03:42 +00:00
646dd0f4d1
Revert r133452: "Emit movq for 64-bit register to XMM register moves..."
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This is breaking compiler-rt and llvm-gcc builds on MacOSX when not using
the integrated assembler.
llvm-svn: 133524
2011-06-21 17:35:13 +00:00
083f0b5a7e
Add support for sadd.with.overflow and uadd.with.overflow intrinsics to the CBackend by emitting definitions for each intrinsic that occurs in the module.
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llvm-svn: 133522
2011-06-21 17:18:15 +00:00
4c0bd9629d
Teach dag combine to match halfword byteswap patterns.
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1. (((x) & 0xFF00) >> 8) | (((x) & 0x00FF) << 8)
=> (bswap x) >> 16
2. ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0xff000000)>>8)|((x&0x00ff0000)<<8))
=> (rotl (bswap x) 16)
This allows us to eliminate most of the def : Pat patterns for ARM rev16
revsh instructions. It catches many more cases for ARM and x86.
rdar://9609108
llvm-svn: 133503
2011-06-21 06:01:08 +00:00
4c406e7457
Re-apply 132758 and 132768 which were speculatively reverted in 132777.
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llvm-svn: 133494
2011-06-21 00:40:49 +00:00
cd4484d25d
PTX: Fix conversion between predicates and value types
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llvm-svn: 133454
2011-06-20 18:42:48 +00:00
c7df192279
Emit movq for 64-bit register to XMM register moves, but continue to accept
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movd when assembling.
llvm-svn: 133452
2011-06-20 18:33:26 +00:00
254f82112d
Don't apply on PPC64 the 32bit ADDIC optimizations as there's no overflow
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with 32bit values.
llvm-svn: 133439
2011-06-20 15:28:39 +00:00
d34ce4344b
Fix PromoteIntRes_TRUNCATE: Add support for cases where the
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source vector type is to be split while the target vector is to be promoted.
(eg: <4 x i64> -> <4 x i8> )
llvm-svn: 133424
2011-06-20 07:15:58 +00:00
f3c6d6def5
Update test.
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llvm-svn: 133390
2011-06-19 12:14:34 +00:00
6d0036e259
Reduce the runtime of the test. Keep only the interesting cases.
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llvm-svn: 133381
2011-06-19 08:12:43 +00:00
8936d2bfbc
Remove support for parsing the "type i32" syntax for defining a numbered
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top level type without a specified number. This syntax isn't documented
and blocks forward progress.
llvm-svn: 133371
2011-06-19 00:03:46 +00:00
80ed9dc9e5
rip out a ton of intrinsic modernization logic from AutoUpgrade.cpp, which is
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for pre-2.9 bitcode files. We keep x86 unaligned loads, movnt, crc32, and the
target indep prefetch change.
As usual, updating the testsuite is a PITA.
llvm-svn: 133337
2011-06-18 06:05:24 +00:00
831ae0105a
Switch ARM to using AltOrders instead of MethodBodies.
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This slightly changes the GPR allocation order on Darwin where R9 is not
a callee-saved register:
Before: %R0 %R1 %R2 %R3 %R12 %R9 %LR %R4 %R5 %R6 %R8 %R10 %R11
After: %R0 %R1 %R2 %R3 %R9 %R12 %LR %R4 %R5 %R6 %R8 %R10 %R11
llvm-svn: 133326
2011-06-18 01:14:46 +00:00
197ea52d4b
Moved to the right place.
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llvm-svn: 133324
2011-06-18 00:59:37 +00:00
e4a1266a9a
Fix UMULO support for 2x register width to allow the full
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range without a libcall to a new mulo<mode> libcall
that we'd have to create.
Finishes the rest of rdar://9090077 and rdar://9210061
llvm-svn: 133318
2011-06-18 00:09:57 +00:00
ea7822685a
Fix a bug in the type-lowering of integer-promoted elements. Add a check that
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the newly created simple type is valid before checking its legality.
Re-commit the test file.
llvm-svn: 133291
2011-06-17 20:54:12 +00:00
7552a62af5
Add an alternative rev16 pattern. We should figure out a better way to handle these complex rev patterns. rdar://9609108
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llvm-svn: 133289
2011-06-17 20:47:21 +00:00
5bbb2bdb46
Lower multiply with overflow checking to __mulo<mode>
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calls if we haven't been able to lower them any
other way.
Fixes rdar://9090077 and rdar://9210061
llvm-svn: 133288
2011-06-17 20:41:29 +00:00
ac6bc75030
est 2008-06-04-indirectmem.ll is X86-specific. Move to X86 folder.
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llvm-svn: 133275
2011-06-17 18:26:23 +00:00
6bc5c89093
Stop accepting and ignoring attributes in function types. Attributes are applied
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to functions and call/invokes, not to types.
llvm-svn: 133266
2011-06-17 17:37:13 +00:00
d041962c20
Fix a few places where 32bit instructions/registerset were used on PPC64.
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llvm-svn: 133260
2011-06-17 15:21:10 +00:00
3604d9a421
PTX: Adjust rounding modes
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* rounding modes for fp add, mul, sub now use .rn
* float -> int rounding correctly uses .rzi not .rni
* 32bit fdiv for sm13 uses div.rn (instead of div.approx)
* 32bit fdiv for sm10 now uses div (instead of div.approx)
Approx is not IEEE 754 compatible (and should be optionally set by a flag to the backend instead). The .rn rounding modifier is the PTX default anyway, but it's better to be explicit.
All these modifiers should be available by using __fmul_rz functions for example, but support will need to be added for this in the backend.
Patch by Dan Bailey
llvm-svn: 133253
2011-06-17 12:12:42 +00:00
5756c16cdf
make the asmparser reject function and type redefinitions. 'Merging' hasn't been
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needed since llvm-gcc 3.4 days.
llvm-svn: 133248
2011-06-17 07:06:44 +00:00
59345c8b65
remove asmparser support for the old getresult instruction, which has been subsumed by extractvalue.
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llvm-svn: 133247
2011-06-17 06:57:15 +00:00
33de427cd6
remove parser support for the obsolete "multiple return values" syntax, which
...
was replaced with return of a "first class aggregate".
llvm-svn: 133245
2011-06-17 06:49:41 +00:00
def1949c00
Remove support for using "foo" as symbols instead of %"foo". This is ancient
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syntax and has been long obsolete. As usual, updating the tests is the nasty
part of this.
llvm-svn: 133242
2011-06-17 06:36:20 +00:00
b90ed2233c
manually upgrade a bunch of tests to modern syntax, and remove some that
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are either unreduced or only test old syntax.
llvm-svn: 133228
2011-06-17 03:14:27 +00:00
033026ffc0
Update an insertion point iterator after replacing a return instruction with a
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tail call pseudoinstruction. This fixes <rdar://problem/9624333>.
llvm-svn: 133227
2011-06-17 02:16:43 +00:00
c826df9506
Don't use register classes larger than TLI->getRegClassFor(VT).
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In Thumb mode we cannot handle GPR virtual registers, even though some
instructions can. When isel is lowering a CopyFromReg, it should limit
itself to subclasses of getRegClassFor(VT).
<rdar://problem/9624323>
llvm-svn: 133210
2011-06-16 22:50:38 +00:00
65c47187f2
There's no need to be so picky about the particular register.
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llvm-svn: 133189
2011-06-16 21:00:00 +00:00
7f191b2a3b
PTX: Finish new calling convention implementation
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llvm-svn: 133172
2011-06-16 17:50:00 +00:00
bbf2ab990f
Add AVX suport for fpextend.
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Original patch by Syoyo Fujita with more comments by me.
llvm-svn: 133153
2011-06-16 07:03:21 +00:00
9b3d779537
FileCheck-ize test, and make it work on EABI hosts, like clang-native-arm-cortex-a9.
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llvm-svn: 133139
2011-06-16 02:36:32 +00:00
575d0163bb
Force a triple here so this test doesn't fail on EABI hosts (like clang-native-arm-cortex-a9).
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llvm-svn: 133134
2011-06-16 01:49:31 +00:00
27d604cbf3
Commit the right set of tests for r133124. Sorry 'bout that!
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llvm-svn: 133133
2011-06-16 01:35:45 +00:00
41369d5e8a
Reenabling this test with REQUIRES: Asserts
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llvm-svn: 133132
2011-06-16 01:34:41 +00:00
aed609da92
Typos.
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llvm-svn: 133128
2011-06-16 01:24:24 +00:00
2730162bee
Revision r128665 added an optimization to make use of NEON multiplier
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accumulator forwarding. Specifically (from SVN log entry):
Distribute (A + B) * C to (A * C) + (B * C) to make use of NEON multiplier
accumulator forwarding:
vadd d3, d0, d1
vmul d3, d3, d2
=>
vmul d3, d0, d2
vmla d3, d1, d2
Make sure it catches cases where operand 1 is add/fadd/sub/fsub, which was
intended in the original revision.
llvm-svn: 133127
2011-06-16 01:21:54 +00:00
6d677cfdd8
Add a DAGCombine for (ext (binop (load x), cst)).
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llvm-svn: 133124
2011-06-16 01:15:49 +00:00
a56e84e439
Rename the test. Thanks Cameron! Use shorter/generic names.
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llvm-svn: 133115
2011-06-16 00:34:10 +00:00
Akira Hatanaka